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YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_2a58c59b-da1"},"title":"ASIC Design Verification, Sr Staff Engineer - DDR","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.</p>\n<p>They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are seeking a highly skilled and experienced ASIC verification professional to lead technical teams and drive excellence in digital design.</p>\n<p>As a Sr Staff Engineer - DDR, you will be responsible for technically leading and driving ownership of critical areas of verification alongside a team of talented verification engineers.</p>\n<p>You will specify, design, and implement state-of-the-art verification environments for the DesignWare family of synthesizable cores.</p>\n<p>You will perform verification tasks for IP cores, working closely with RTL designers and architects to ensure functional correctness.</p>\n<p>You will develop and implement advanced test plans and test environments at both unit and system levels.</p>\n<p>You will code and debug test cases, including the creation of complex checkers and assertions using System Verilog/UVM.</p>\n<p>You will extract and review functional coverage (FC) and code coverage metrics to ensure quality metric goals are met.</p>\n<p>You will manage regressions and contribute to the continuous improvement of verification strategies and test environments.</p>\n<p>This role requires a deep understanding of verification methodologies, serial interface protocols, and the intricacies of IP core development.</p>\n<p>You should have demonstrated experience in technically leading a team for DDR IP projects, with a track record of successful collaboration and stakeholder management.</p>\n<p>You should have proven expertise in developing HVL (System Verilog/UVM) based test environments for complex ASIC designs.</p>\n<p>You should have advanced skills in developing and implementing rigorous test plans, checkers, and assertions.</p>\n<p>You should have strong proficiency in extracting and analyzing verification metrics such as functional coverage and code coverage.</p>\n<p>You should have experience with serial interface protocols and IP design/verification processes; knowledge of DDR/LPDDR is highly desirable.</p>\n<p>You should have hands-on experience in owning end-to-end verification deliverables for IPs, including planning, execution, DV metrics closure, and review/signoff.</p>\n<p>You will join the DesignWare IP Verification R&amp;D team, a group of talented and passionate engineers committed to advancing Synopsys&#39; leadership in semiconductor IP.</p>\n<p>The team focuses on delivering world-class verification solutions for a broad portfolio of synthesizable IP cores, leveraging the latest methodologies and technologies to ensure our products meet the most rigorous quality and performance standards.</p>\n<p>Collaboration, innovation, and a drive for excellence define our culture.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2a58c59b-da1","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/asic-design-verification-sr-staff-engineer-ddr/44408/89681053968","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC verification","System Verilog/UVM","HVL","Serial interface protocols","IP core development","Verification methodologies","Test plans and test environments","Functional coverage and code coverage metrics","Regressions and continuous improvement"],"x-skills-preferred":["DDR/LPDDR","RTL designers and architects","Chip architecture and circuit design","Semiconductor products"],"datePosted":"2026-03-10T12:07:42.010Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru, Karnataka, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC verification, System Verilog/UVM, HVL, Serial interface protocols, IP core development, Verification methodologies, Test plans and test environments, Functional coverage and code coverage metrics, Regressions and continuous improvement, DDR/LPDDR, RTL designers and architects, Chip architecture and circuit design, Semiconductor products"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_03c25570-d79"},"title":"ASIC Design Engineer, Hardware Tools and Methodology Development","description":"<p>We are looking for an ASIC Design Engineer with proven hardware design and methodology expertise to join our world-class team. You will develop and deploy in-house tools and workflows to support engineering business units across NVIDIA. You will take ownership of tools that verify common design blocks used in all products at NVIDIA. You will act as a &#39;DevOps&#39; engineer for automated RTL generation by developing new features and maintaining efficient operations for existing users. You will build new workflows and methodologies to ensure smooth integration into various IP development environments.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Develop and deploy in-house tools and workflows to support engineering business units across NVIDIA.</li>\n<li>Take ownership of tools that verify common design blocks used in all products at NVIDIA.</li>\n<li>Act as a &#39;DevOps&#39; engineer for automated RTL generation by developing new features and maintaining efficient operations for existing users.</li>\n<li>Build new workflows and methodologies to ensure smooth integration into various IP development environments.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering or Computer Engineering (or equivalent experience).</li>\n<li>3+ years of proven experience preferred.</li>\n<li>Solid understanding of fundamental digital design concepts with hands-on experience in Verilog.</li>\n<li>Proficiency in scripting using modern Python and/or Perl.</li>\n<li>Experience with Unix/Linux shell scripting and Makefiles.</li>\n<li>Strong ability to collaborate with multi-functional teams and effectively communicate technical details.</li>\n</ul>\n<p>Preferred qualifications:</p>\n<ul>\n<li>Prior experience in ASIC verification.</li>\n<li>Knowledge of Clocks/Resets design and verification.</li>\n<li>Exposure to CDC related design/verification flows.</li>\n<li>Exposure to backend flows (Synthesis, Timing, etc).</li>\n</ul>\n<p>NVIDIA is widely considered to be one of the technology world&#39;s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of constant innovation and creating the highest performance products in the industry? If so, we want to hear from you.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_03c25570-d79","directApply":true,"hiringOrganization":{"@type":"Organization","name":"NVIDIA","sameAs":"https://nvidia.wd5.myworkdayjobs.com","logo":"https://logos.yubhub.co/nvidia.com.png"},"x-apply-url":"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-TX-Austin/ASIC-Design-Engineer--Hardware-Tools-and-Methodology-Development_JR2008177","x-work-arrangement":"hybrid","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC Design","Hardware Tools","Methodology Development","Verilog","Python","Perl","Unix/Linux shell scripting","Makefiles"],"x-skills-preferred":["ASIC verification","Clocks/Resets design and verification","CDC related design/verification flows","Backend flows (Synthesis, Timing, etc)"],"datePosted":"2026-03-09T20:46:52.411Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"US, TX, Austin"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC Design, Hardware Tools, Methodology Development, Verilog, Python, Perl, Unix/Linux shell scripting, Makefiles, ASIC verification, Clocks/Resets design and verification, CDC related design/verification flows, Backend flows (Synthesis, Timing, etc)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_3a6efc4b-131"},"title":"ASIC Security Staff Engineer","description":"<p><strong>Overview</strong></p>\n<p>We are seeking a highly skilled ASIC Security Staff Engineer to join our team at Synopsys. As a key member of our Security IP team, you will be responsible for designing and implementing secure ASIC solutions for various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>What You&#39;ll Be Doing:</strong></p>\n<ul>\n<li>Designing and implementing RTL in Verilog and/or System Verilog for Security Applications.</li>\n<li>Creating and designing test environments for digital hardware Security IP cores and subsystems using System Verilog and UVM.</li>\n<li>Conducting hardware verification of IP cores and subsystems utilizing modern verification techniques such as UVM or formal verification.</li>\n<li>Collaborating with hardware and software security experts to perform functional and performance analysis of embedded hardware/software IP solutions.</li>\n<li>Working within an international team setup, contributing to global projects.</li>\n<li>Ensuring adherence to high-quality standards and best practices in digital design and verification processes.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Enhancing the performance and security of our IP cores and subsystems.</li>\n<li>Contributing to the rapid integration of advanced capabilities into SoCs, meeting unique performance, power, and size requirements.</li>\n<li>Reducing time-to-market for differentiated products with minimized risk.</li>\n<li>Driving innovation in the fields of CyberSecurity, High Performance Computing, Artificial Intelligence, and Automotive.</li>\n<li>Collaborating with a diverse team to deliver leading-edge solutions that shape the future of technology.</li>\n<li>Playing a key role in maintaining Synopsys&#39; position as a leader in chip design and software security.</li>\n</ul>\n<p><strong>What You&#39;ll Need:</strong></p>\n<ul>\n<li>3+ years Experience in RTL design of hardware IP components.</li>\n<li>Proficiency in ASIC verification using System Verilog, UVM, and or Verilog</li>\n<li>Ability to create detailed specifications for test environments.</li>\n<li>MSc or PhD in Electrical Engineering or Computer Science.</li>\n<li>Strong understanding of IC Design flows and exceptional problem-solving and debugging skills.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>A strong communicator with excellent written and verbal skills.</li>\n<li>A team player who thrives in a collaborative international environment.</li>\n<li>An innovative thinker who is passionate about technology and continuous improvement.</li>\n<li>Detail-oriented and committed to delivering high-quality work.</li>\n<li>Adaptable and able to manage multiple tasks effectively.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You will be joining the Security IP team in Eindhoven at the High Tech Campus, a dynamic and innovative group dedicated to extending the Security IP business in markets such as CyberSecurity, High Performance Computing, Artificial Intelligence, and Automotive. Our team is composed of experts in hardware and software security, working together to develop state-of-the-art IP cores and subsystems. We value collaboration, creativity, and a commitment to excellence.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_3a6efc4b-131","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/eindhoven/asic-security-staff-engineer/44408/91940192192","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design","Verilog","System Verilog","UVM","Formal verification","IC Design flows","Problem-solving and debugging skills"],"x-skills-preferred":["ASIC verification","Digital hardware Security IP cores and subsystems","Embedded hardware/software IP solutions"],"datePosted":"2026-03-09T11:09:25.644Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Eindhoven"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design, Verilog, System Verilog, UVM, Formal verification, IC Design flows, Problem-solving and debugging skills, ASIC verification, Digital hardware Security IP cores and subsystems, Embedded hardware/software IP solutions"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_6b2407ad-352"},"title":"ASIC Verification- Staff Engineer","description":"<p>We are seeking an accomplished verification engineer with a passion for excellence and a track record of delivering robust, high-quality IP solutions. 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