We Are:
\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.
\nYou Are:
\nAn experienced and visionary ASIC Digital Architect, who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in design methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of protocols such as DDR, PCIe/CXL, UCIe, AMBA and its applications. You can define and executing a new architecture for protocols such as UAL (Universal Accelerator Link). You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects.
\nWhat You’ll Be Doing:
\nDefining and developing ASIC RTL design and verification at both chip and block levels.\nCreating and executing design plans for complex digital designs, particularly focusing on DDR, PCIe,CXL,UAL, UCIe IO protocols.\nCollaborating with cross-functional teams to ensure seamless integration and functionality of designs.\nUtilizing advanced design and verification methodologies and tools to achieve high-quality results.\nMentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement.\nCommunicating with internal and external stakeholders to align on project goals and deliverables.
\nThe Impact You Will Have:
\nEnhancing the reliability and performance of Synopsys’ digital design processes.\nDriving innovations in DDR, PCIe, UAL, UCIe technology, contributing to the development of cutting-edge semiconductor solutions.\nImproving time-to-market for high-performance silicon chips through efficient methodologies.\nBuilding and nurturing a highly skilled development team, elevating overall project quality.\nInfluencing strategic decisions that shape the future of Synopsys’ capabilities.\nEnsuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements.
\nWhat You’ll Need:
\nExtensive experience in ASIC RTL design.\nIn-depth knowledge of DDR, PCIe, UAL, UCIe and similar IO protocols and their applications.\nProficiency in advanced digital design tools and methodologies.\nStrong problem-solving skills and the ability to work independently.\nExcellent communication skills for effective collaboration with diverse teams.
\nWho You Are:
\nA visionary leader with a strategic mindset.\nA mentor who fosters talent and encourages innovation.\nA proactive problem solver who thrives in complex environments.\nAn effective communicator with the ability to convey technical concepts to a broad audience.\nA team player who values collaboration and diversity.
\nThe Team You’ll Be A Part Of:
\nYou will join a dynamic and innovative team focused on advancing Synopsys' design technologies. Our team is dedicated to excellence, collaboration, and continuous improvement. We work closely with various departments to ensure the successful integration and performance of our solutions. Together, we drive the future of semiconductor technology and make a significant impact on the industry.
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
\nBenefits:
\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nVisit Benefits Page
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\nYou Are:
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\nWe Are:
\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.
\nYou Are:
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\nOur Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
\nJob Description
\nWe Are:
\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.
\nYou Are:
\nYou are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelor’s or Master’s degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures.
\nResponsibilities
\nArchitecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.
\nTranslating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features.
\nLeading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.
\nCollaborating with global teams and engaging directly with customers to understand and refine specification requirements.
\nDriving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&R-aware synthesis using tools such as Fusion Compiler.
\nMentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies.
\nUtilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency.
\nRequirements
\nBachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field.
\n4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.
\nDeep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.
\nProficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.
\nFamiliarity with high-speed design (>600MHz), P&R-aware synthesis, and EDA tools such as Fusion Compiler.
\nExperience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation.
\nKnowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI).
\nExposure to quality processes in IP design and verification is an advantage.
\nPrior experience as a technical lead or mentor is highly desirable.
\nWho We Are Looking For
\nInnovative thinker with a solutions-oriented mindset and a passion for technology.
\nExcellent communicator who thrives in collaborative, multicultural, and multi-site environments.
\nNatural leader with mentoring abilities, fostering inclusion and diversity within the team.
\nDetail-oriented professional with strong analytical and problem-solving skills.
\nSelf-motivated, adaptable, and eager to drive technical excellence and process improvements.
\nCommitted to continuous learning and staying ahead of industry trends.
\nThe Team You’ll Be A Part Of
\nYou will join the R&D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys’ global customers to achieve their design goals.
\nRewards and Benefits
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.
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