{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/asic-rtl-design-flow"},"x-facet":{"type":"skill","slug":"asic-rtl-design-flow","display":"Asic Rtl Design Flow","count":1},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_40a899dc-af8"},"title":"Senior/Staff ASIC Design Verification Engineer","description":"<p>Our organisation is seeking a skilled Senior/Staff ASIC Design Verification Engineer to join our team in Ho Chi Minh City, Vietnam. As a key member of our engineering team, you will be responsible for designing and developing cutting-edge semiconductor solutions. Your expertise in ASIC RTL design flow, RTL and GLS verification, and high-speed interface protocols will be essential in advancing our technology and enabling innovations in various industries.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Collaborate with digital design teams to develop high-speed mixed-signal PHY IPs.</li>\n<li>Participate in RTL and Gate-Level Simulation (GLS) verification for mixed-signal designs.</li>\n<li>Define, develop, and execute functional verification plans and test strategies.</li>\n<li>Conduct RTL and SDF-annotated gate-level simulations using UVM-based methodologies.</li>\n<li>Generate VCD files and perform power analysis/reporting using PrimeTime PX.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Minimum of 2 years of experience in ASIC RTL design flow.</li>\n<li>Proficiency in RTL and GLS verification, with strong debugging capabilities.</li>\n<li>Excellent teamwork and communication skills, with professional proficiency in English.</li>\n<li>Strong knowledge of high-speed interface protocols (e.g., DDR, HBM, or PCIe PHYs) is a distinct advantage.</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</li>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n<li>Competitive salaries.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_40a899dc-af8","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/senior-staff-asic-design-verification-engineer/44408/92568976592","x-work-arrangement":"onsite","x-experience-level":"senior/staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["ASIC RTL design flow","RTL and GLS verification","High-speed interface protocols","UVM-based methodologies","PrimeTime PX"],"x-skills-preferred":["High-speed interface protocols"],"datePosted":"2026-03-10T12:09:27.363Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC RTL design flow, RTL and GLS verification, High-speed interface protocols, UVM-based methodologies, PrimeTime PX, High-speed interface protocols"}]}