{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/asic-physical-design"},"x-facet":{"type":"skill","slug":"asic-physical-design","display":"Asic Physical Design","count":3},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5be91f86-bf9"},"title":"ASIC Physical Design, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.</p>\n<p>They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p>As a Senior ASIC Physical Design Engineer, you will be responsible for implementing and integrating state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below).</p>\n<p>You will drive timing closure for high-frequency designs (above ~4GHz), ensuring optimal performance and reliability.</p>\n<p>You will collaborate with local and US-based teams, engaging in daily technical discussions to align on project goals and challenges.</p>\n<p>You will integrate mixed-signal hard macro IPs and address unique integration requirements with innovative solutions.</p>\n<p>You will design and build efficient clock trees, focusing on tight skew balancing and robust clock distribution.</p>\n<p>You will participate in design reviews, debug issues, and contribute to continuous improvement of physical design methodologies.</p>\n<p>You will support the implementation of best practices in floorplanning, placement, routing, and power optimization.</p>\n<p>You will mentor junior engineers and contribute to team knowledge sharing initiatives.</p>\n<p><strong>Impact</strong></p>\n<p>You will enable delivery of high-performance DDR IPs that power next-generation consumer and enterprise products.</p>\n<p>You will advance Synopsys&#39; leadership in IP implementation at cutting-edge technology nodes.</p>\n<p>You will champion best-in-class timing closure and integration practices, raising the bar for design excellence.</p>\n<p>You will facilitate seamless cross-site collaboration, ensuring global project success.</p>\n<p>You will drive innovation in clock tree synthesis and mixed-signal integration, contributing to differentiated product offerings.</p>\n<p>You will accelerate time-to-market for customers by delivering robust, silicon-proven IP solutions.</p>\n<p><strong>Requirements</strong></p>\n<p>Bachelor&#39;s or Master&#39;s degree in Electronics, Electrical Engineering, or related field.</p>\n<p>3+ years of experience in ASIC physical design, especially at advanced technology nodes (10nm, 7nm, 6nm or below).</p>\n<p>Proficiency with physical design tools (such as Synopsys ICC2, PrimeTime, StarRC, etc.).</p>\n<p>Solid understanding of timing closure, clock tree synthesis, and skew balancing for high-frequency designs.</p>\n<p>Experience with DDR interface implementation and/or mixed-signal IP integration is highly desirable.</p>\n<p>Familiarity with scripting languages (Tcl, Perl, Python) for automation and workflow optimization.</p>\n<p>Strong analytical and debugging skills for addressing complex design challenges.</p>\n<p><strong>Team</strong></p>\n<p>You will join the Synopsys DDR IP implementation team, a group of passionate engineers focused on delivering world-class memory interface solutions at the leading edge of semiconductor technology.</p>\n<p>The team fosters a culture of innovation, technical excellence, and collaboration, working closely with global counterparts to achieve ambitious project goals.</p>\n<p>Together, you will help shape the future of high-performance silicon and enable the next wave of intelligent systems.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_5be91f86-bf9","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/asic-physical-design-sr-engineer/44408/92159183392","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","DDR IP implementation","Timing closure","Clock tree synthesis","Skew balancing","Mixed-signal IP integration","Scripting languages (Tcl, Perl, Python)","Physical design tools (Synopsys ICC2, PrimeTime, StarRC)"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:17:24.614Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, DDR IP implementation, Timing closure, Clock tree synthesis, Skew balancing, Mixed-signal IP integration, Scripting languages (Tcl, Perl, Python), Physical design tools (Synopsys ICC2, PrimeTime, StarRC)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_84c32509-79a"},"title":"ASIC Physical Design, Principal Engineer","description":"<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>You are a visionary and seasoned engineering leader, driven by a passion for innovation in ASIC physical design. Seeking a highly motivated and innovative ASIC Physical Design Implementation Engineer to lead the Test Chip PHY development. You will lead a team of engineers to develop Test Chips for DDR/HBM/UCIe protocols. The position offers an excellent opportunity to work on mixed-signal IPs with a focus on digital design.</p>\n<p>What You’ll Be Doing:</p>\n<p>Lead Test Chip Physical Design Implementation: Oversee all aspects of physical implementation for test chips, including integration of IP blocks and custom logic for validation purposes. Candidate will lead multiple test chips that will be developed in parallel to tape-out for various foundry shuttles.</p>\n<p>Resource &amp; Project Leadership: Lead a team of physical design engineers; allocate resources, schedule tasks, and manage priorities for on-time project execution.</p>\n<p>Floor planning &amp; Power Planning: Develop overall floorplan and power/ground strategy tailored for the test chip architecture.</p>\n<p>Synthesis to GDSII: Own and drive the entire RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.</p>\n<p>Timing Closure: Execute and oversee static timing analysis (STA) for the test chip, ensuring robust timing signoff.</p>\n<p>Design Integrity Checks: Conduct and resolve EM/IR drop analysis and physical verification (ERC/DRC/LVS), as well as PERC/ESD analysis specific to test chips.</p>\n<p>Block/Chip-level Integration: Integrate updated covercells, circuit/IP/PLL/hard-macros, abutment checking, and QA/review/release of hard-macros.</p>\n<p>Tool Flow Enhancements &amp; Debug: Drive tool flow automation and debugging to improve productivity and design reliability.</p>\n<p>Collaboration: Work closely with Architecture, FE RTL, Circuit and Covercell teams before and during the TC development</p>\n<p>Release &amp; Documentation: Prepare and release all supporting views necessary for the tape out of the test chips on to the foundry portal. File, update and maintain the mask tooling form on the foundry website and fill out the necessary checklists</p>\n<p>What You’ll Need:</p>\n<ul>\n<li>12+ years of proven experience in ASIC physical Design, with expertise in leading complex SoC or test chip implementations at advanced process nodes.</li>\n<li>Deep knowledge of the entire ASIC physical design flow, including floor planning, synthesis, place and route, timing closure, IR-drop/EM analysis, LVS/DRC, and related methodologies.</li>\n<li>Demonstrated experience leading engineering teams and managing cross-functional projects in high-pressure environments.</li>\n<li>Familiarity with test chip methodology, IP integration, and advanced verification flows.</li>\n<li>Proficiency with state-of-the-art CAD tools such as DC, PT, ICC2/FC, ICV, Calibre, RedHawk, and advanced technologies like FinFet.</li>\n<li>Strong communication, problem-solving, and project management skills.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Elevate Synopsys’ leadership in advanced ASIC and IP development by delivering high-performance, reliable test chips.</li>\n<li>Enable rapid validation and integration of DDR/HBM/UCIe protocols, supporting next-generation silicon innovation.</li>\n<li>Enhance cross-functional collaboration, accelerating project timelines and improving overall design quality.</li>\n<li>Drive process improvements through tool flow automation, setting new standards for productivity and design reliability.</li>\n<li>Ensure robust manufacturability and performance, reducing risk and increasing success rates in foundry tape-outs.</li>\n<li>Mentor and develop junior engineers, fostering a culture of technical excellence and continuous learning.</li>\n<li>Contribute to the creation of industry-leading mixed-signal IPs, elevating Synopsys’ portfolio and market position.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>Innovative thinker with a passion for solving complex engineering challenges.</li>\n<li>Inspirational leader who empowers teams and fosters collaborative, inclusive environments.</li>\n<li>Meticulous and detail-oriented, committed to quality and design integrity.</li>\n<li>Adaptable and resilient, thriving in fast-paced, dynamic settings.</li>\n<li>Excellent communicator, able to articulate technical concepts to diverse audiences.</li>\n<li>Continuous learner, eager to stay at the forefront of technology and industry trends.</li>\n</ul>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You’ll join a highly skilled, multidisciplinary team focused on developing industry-leading test chips for cutting-edge protocols like DDR, HBM, and UCIe. The team values collaboration, innovation, and technical excellence, working closely with architecture, RTL, circuit, and verification experts to deliver best-in-class mixed-signal IP solutions. Together, you’ll shape the next generation of silicon technology and drive Synopsys’ continued success in the semiconductor industry.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>#LI-NK4</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.</p>\n<p>Back to nav</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our 401(k) and 401(k) matching program.</p>\n<ul>\n<li>### Other Benefits</li>\n</ul>\n<p>Flexible work arrangements, employee discounts, and more.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_84c32509-79a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/boxborough/asic-physical-design-principal-engineer-15046/44408/91661594048","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$170,000-$255,000","x-skills-required":["ASIC physical design","CAD tools","FinFet","IP integration","test chip methodology","verification flows"],"x-skills-preferred":["leadership","project management","communication","problem-solving"],"datePosted":"2026-03-09T11:05:54.042Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Boxborough, Massachusetts"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, CAD tools, FinFet, IP integration, test chip methodology, verification flows, leadership, project management, communication, problem-solving","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":170000,"maxValue":255000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_358b5046-c5a"},"title":"ASIC Physical Design, Sr Engineer","description":"<p>Opening.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>You will be responsible for designing and developing cutting-edge semiconductor solutions. You will work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<ul>\n<li>Implement and integrate state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below).</li>\n<li>Drive timing closure for high-frequency designs (above ~4GHz), ensuring optimal performance and reliability.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or related field.</li>\n<li>3+ years of experience in ASIC physical design, especially at advanced technology nodes (10nm, 7nm, 6nm or below).</li>\n<li>Proficiency with physical design tools (such as Synopsys ICC2, PrimeTime, StarRC, etc.).</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_358b5046-c5a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/asic-physical-design-sr-engineer/44408/92159183376","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","DDR IPs","Timing closure","Physical design tools"],"x-skills-preferred":["Scripting languages (Tcl, Perl, Python)","Automation and workflow optimization"],"datePosted":"2026-03-04T17:09:16.214Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad, Telangana, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, DDR IPs, Timing closure, Physical design tools, Scripting languages (Tcl, Perl, Python), Automation and workflow optimization"}]}