With a solid foundation in ASIC design, VLSI, and CAD engineering, you continuously expand your knowledge to stay ahead of industry trends. You possess a keen analytical mind, capable of troubleshooting and resolving intricate issues efficiently. Your creative problem-solving skills and meticulous attention to detail ensure that projects are executed flawlessly from conception through completion. You enjoy mentoring others and contributing to moderately complex aspects of projects, enhancing team performance.

You embrace diversity, respect different perspectives, and believe in the power of inclusion to foster innovation. Your dedication, resilience, and positive attitude enable you to thrive in dynamic environments, and you’re motivated by the opportunity to support key foundry customers and help shape the future of electronic design automation.

What You’ll Be Doing:

• Managing and providing ICV runset support for key foundry partners, ensuring seamless integration and optimal performance of Synopsys products.
• Delivering post-sales technical expertise throughout the runset programming, implementation, and ongoing maintenance cycles.
• Translating detailed customer installation requirements into actionable solutions, customizing product configurations as needed.
• Collaborating with clients to ensure their needs are fully met and Synopsys solutions function according to specifications.
• Offering pre-sales technical support, contributing to sales efforts by addressing technical queries and demonstrating product capabilities.
• Serving as a subject matter expert in EDA tool products, guiding customers through verification, place and route, design reuse, and physical design challenges.

The Impact You Will Have:

• Enhancing customer satisfaction by delivering tailored, high-quality technical solutions and ongoing support.
• Driving successful adoption of Synopsys products within key foundries, solidifying long-term partnerships and business growth.
• Contributing to the continuous improvement of runset programming and installation processes, raising industry standards.
• Supporting the sales team with technical insights, helping to win new business and expand Synopsys’s market reach.
• Identifying opportunities for innovation and improvement in EDA tools, directly influencing product development and competitiveness.
• Mentoring junior team members and sharing best practices, fostering a collaborative and high-performing work environment.

What You’ll Need:

• Basic understanding of the design process; familiarity with Design Rule Manuals (DRM) is preferred.
• Strong communication skills, capable of conveying technical concepts clearly to diverse audiences.
• Solid grasp of ASIC design flows, VLSI, and/or CAD engineering principles.
• Experience or knowledge of competitive EDA tool products, with expertise in verification, place and route, design reuse, and/or physical design.
• Demonstrated ability to manage projects from start to completion, contributing to moderately complex aspects of technical initiatives.

Who You Are:

• Creative and resourceful problem solver, able to think outside the box and address challenges proactively.
• Judicious decision-maker, skilled in selecting effective methods and techniques for optimal solutions.
• Collaborative team player with a strong sense of ownership and accountability.
• Adaptable and resilient, comfortable navigating evolving priorities and customer requirements.
• Inclusive and respectful, valuing diverse perspectives and fostering a positive team culture.

The Team You’ll Be A Part Of: You’ll join a dynamic Customer Application Services team based in Taiwan, dedicated to supporting key foundry partners and advancing Synopsys’s leadership in EDA solutions. The team is composed of experienced engineers and technical experts who collaborate closely with customers, sales, and product development groups. Together, you’ll tackle complex challenges, drive innovation, and ensure the successful implementation of industry-leading design automation tools.

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As a Senior ASIC Verification Engineer, you will be responsible for developing and executing comprehensive verification plans for complex ASIC designs, focusing on next-generation HBM (High Bandwidth Memory) products. You will write and maintain advanced testcases using SystemVerilog and UVM methodologies to ensure thorough coverage and robust verification.

You will also debug and analyze complex testbench and design-related issues, collaborating closely with design and mixed-signal engineering teams. Additionally, you will automate verification flows and processes using scripting languages such as Python or Perl to enhance productivity and coverage.

You will review and provide feedback on design specifications, contributing to architecture and design discussions to improve product quality. You will participate in code reviews, mentor junior engineers, and share best practices within the verification team.

You will document verification results, methodologies, and lessons learned to support knowledge sharing and process improvement.

The impact you will have includes accelerating the development of high-performance, reliable HBM solutions that power the next generation of computing and AI applications. You will ensure the delivery of robust, high-quality silicon products through meticulous verification and debugging.

You will drive innovation in verification methodologies and contribute to the continuous improvement of engineering processes. You will reduce time-to-market for cutting-edge products by identifying and resolving issues early in the design cycle.

You will enhance team capabilities by sharing knowledge, mentoring peers, and fostering a collaborative engineering environment. You will influence the direction of future product development by providing valuable insights into design and verification challenges.

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You are a passionate analog design engineer eager to make a tangible impact in pioneering semiconductor technologies. You thrive in fast-paced environments and enjoy collaborating with diverse, talented teams. Your expertise in CMOS circuit design and deep submicron process technologies makes you a valuable contributor to high-performance chip solutions. You are detail-oriented, analytical, and consistently deliver quality results. Your curiosity drives you to explore industry standards such as JEDEC DDR interfaces, and you are comfortable navigating the complexities of ASIC design flows. You communicate clearly and effectively, bridging technical discussions between cross-functional teams. You embrace continuous learning and are always ready to tackle new challenges, leveraging your experience in analog/mixed signal circuitry and ESD concepts. You are motivated by the opportunity to influence the next generation of silicon products and are committed to excellence in every aspect of your work. Your collaborative spirit, adaptability, and drive for innovation make you a perfect fit for Synopsys' world-class engineering community.

Designing DDR I/O circuits for advanced semiconductor products, ensuring alignment with JEDEC interface standards. Implementing CMOS circuit design and layout methodologies to optimize performance and reliability. Collaborating with internal development teams to integrate analog/mixed signal circuitry into ASIC designs. Analyzing and resolving issues related to deep submicron process technologies. Executing assigned circuit design tasks with a focus on product quality and efficiency. Documenting design solutions and communicating technical details clearly to cross-functional stakeholders. Participating in design reviews and contributing to continuous improvement of design flows and practices.

Advance Synopsys' leadership in high-performance DDR interface design for cutting-edge chips. Enhance product reliability and scalability through robust analog design methodologies. Drive innovation in deep submicron process technology applications. Strengthen integration of mixed signal and analog circuitry in ASIC products. Support cross-team collaboration to accelerate product development and delivery. Contribute to Synopsys' reputation for technical excellence and quality in semiconductor solutions.

BTech/MTech in Electrical Engineering or related field (MTech+3 years / BTech+5 years experience). Strong knowledge of CMOS processes and deep submicron process technology issues. Expertise in CMOS circuit design and layout methodology; familiarity with analog/mixed signal circuitry. Understanding of basic ESD concepts (a plus). Experience with ASIC design flow and integration. Knowledge of JEDEC DDR interface requirements, DDR timing, ODT, and SDRAM functionality (preferred).

Analytical thinker with strong problem-solving skills. Effective communicator, both written and verbal, for internal team interactions. Collaborative team player, eager to learn and share knowledge. Detail-oriented and quality-focused in all aspects of design. Adaptable and resilient in dynamic project environments.

You will join a highly skilled Analog/Mixed Signal Design team in Bangalore, focused on delivering innovative DDR I/O circuit solutions for ASIC products. The team values creativity, technical rigor, and collaborative problem-solving, working closely with cross-functional groups to drive product excellence and meet industry standards.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Your primary focus will be on collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes. You will also be responsible for automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.

In addition, you will troubleshoot and resolve complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges. You will interface directly with customers and Field Application Engineers (FAEs) to gather requirements, provide technical support, and ensure successful deployment of PV solutions.

As a natural collaborator and mentor, you will guide junior team members and foster a supportive team environment. Your excellent communication skills will enable you to engage confidently with customers and FAEs, translating complex requirements into innovative solutions.

Key Responsibilities:

• Develop and validate DRC, LVS, and Fill runsets for the Synopsys IC Validator tool
• Collaborate with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes
• Automate qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python
• Troubleshoot and resolve complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges
• Interface directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions
• Mentor junior team members and foster a supportive team environment

Requirements:

• B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field
• 5-8 years of hands-on experience in the Physical Verification (PV) domain
• Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS
• Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development
• Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements
• Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks
• Exposure to competitive EDA tools and awareness of their strengths and limitations

Ideal Candidate:

• Analytical thinker with strong problem-solving abilities and meticulous attention to detail
• Collaborative team player who fosters knowledge sharing and mentorship
• Effective communicator, capable of translating technical concepts to diverse audiences
• Adaptable and proactive, with a passion for continuous learning and innovation
• Customer-focused, with a commitment to delivering high-quality solutions on time
• Self-driven, organized, and able to manage multiple priorities in a fast-paced environment

Experience Level: senior Employment Type: full-time Workplace Type: onsite Category: Engineering Industry: Technology Salary Range: Not stated Salary Min: Not stated Salary Max: Not stated Salary Currency: USD Salary Period: year Required Skills: IC Validator, Calibre, Pegasus, Perl, Tcl, Python, CMOS layout, ASIC design flows, foundry process requirements Preferred Skills: None

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Applications Engineering, Staff Engineer

Seongnam-si, Gyeonggi-do, South Korea

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Hire Type EmployeeJob ID 17125Date posted 04/23/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly motivated Staff Engagement Applications Engineer with over 6~ 8 years of hands-on experience in synthesis or formal verification for Tape out project. Your technical expertise helps customer to succeedfor most of Tape out projects to our worldwide key customers to accelerate business growth. You thrive in dynamic environments and possess excellent communication skills, including a strong command of English. Your background in EE/CS, coupled with your experience with EDA tools like DC, Formality, RTLA, and Fusion Compiler, makes you an ideal fit for this role.

What You’ll Be Doing:

• Providing front-end (Synthesis, Equivalence Check) technical support to field engineers, technicians, and product support personnel.

• Diagnosing, troubleshooting, and debugging complex electro/mechanical equipment, computer systems, and software.

• Collaborating with customers to understand their technical requirements and deliver tailored solutions.

• Conductingtraining sessions and workshops for both customers and internal teams.

• Developing andmaintainingtechnical documentation and support materials.

• Working closely with the development team toidentifyand resolve product issues.

The Impact You Will Have:

• Enhancing customer satisfaction by deliveringtimelyand effective technical support.

• Contributing to the development and enhancement of Synopsys products.

• Helping customers maximize the value of Synopsys technologies.

• Reducing downtime and increasing the efficiency of customer operations.

• Strengthening customer relationships and building trust in Synopsys.

• Driving continuous improvement in support processes and best practices.

What You’ll Need:

• Bachelor’s degree orMaster's degree in Electrical Engineering, Computer Science, or a related field.

• Solid understanding of semiconductor and software technologies.

• Minimum6~8 years of hands-on experience with tape-out project execution.

• Experience in troubleshooting and debugging complex systems.

• Experience with scripting languages likeC/C++,PerlandTcl.

• Strong understanding of ASIC design flow, VLSI, and CAD development.

• Excellent analytical and problem-solving skills.

Who You Are:

• Excellent communicator with strong interpersonal skills.

• Detail-oriented and highly organized.

• Proactive and self-motivated.

• Adaptable and able to thrive in a fast-paced environment.

• Collaborative team player with a positive attitude.

The Team You’ll Be A Part Of:

You will join a dynamic and innovative team focused on supporting and driving customer success. Our team collaborates closely with customer to drive technological advancements and provide top-tier support to our customers. We are passionate about pushing the boundaries of what's possible in chip design and software security, and we are looking for like-minded individuals to join us on this exciting journey.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You are a highly motivated Principal Engagement Applications Engineer with over 15 years of hands-on experience in synthesis or place and route (P&R). You have a robust understanding of the most advanced CPU/GPU/NPU designs and are eager to work closely with R&D on driving product development and developing advanced HPC reference flow.

What You’ll Be Doing: Collaborating with R&D teams to drive product development and advanced HPC reference flow development for wide deployment. Demonstrating differentiated PPA results on CPU/GPU/NPU designs to showcase our technology’s superiority. Providing technical support to key global customers to address PPA bottlenecks and design challenges on the most advanced HPC designs. Aggressively engaging in worldwide critical benchmarks and deployments to ensure the highest quality and performance of designs. Utilizing scripting languages such as Perl and Tcl for automation and optimization tasks. Staying updated with the latest advancements in ASIC design flow, VLSI, and CAD development to continually improve processes.

The Impact You Will Have: Enhancing the performance and efficiency of advanced CPU, GPU, and NPU designs. Driving innovations that contribute to the success of Synopsys’ cutting-edge technologies. Providing critical support that helps key customers overcome their PPA challenges. Contributing to the development of new features that keep Synopsys at the forefront of the industry. Improving the overall quality and reliability of our products through meticulous design and optimization. Fostering strong relationships with global customers, reinforcing Synopsys’ reputation as a leader in chip design and software security.

What You’ll Need: Application Engineer working with customer on project enablement. PD Engineer with 5+ Yrs of experience worked on Synopsys tools in Placement, CTS and Route areas. Good communication and presentation skills as this is a customer facing role

Who You Are: Excellent communicator with strong command of English. Highly motivated and self-driven. Detail-oriented with a focus on quality and performance. A team player who thrives in collaborative environments. Adaptable and eager to learn new technologies and methodologies.

The Team You’ll Be A Part Of: You will join a dynamic and innovative team focused on developing and optimizing advanced HPC designs. Our team collaborates closely with R&D to drive technological advancements and provide top-tier support to our global customers. We are passionate about pushing the boundaries of what’s possible in chip design and software security, and we are looking for like-minded individuals to join us on this exciting journey.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Job Description

As an Analog Mixed-Signal Engineer at Synopsys, you will be responsible for designing and developing high-performance memory interface solutions that power next-generation technologies. You will work closely with cross-functional teams to meet complex design specifications and project goals.

Responsibilities

• Design and develop DDR/HBM Memory Interface I/O circuits, including GPIO and special I/Os, ensuring robust performance and reliability.
• Collaborate closely with DDR/HBM PHY teams, package engineers, and system engineers to meet stringent design specifications and project milestones.
• Execute circuit design tasks with a focus on quality, efficiency, and adherence to industry standards.
• Apply deep knowledge of CMOS processes and analog/mixed-signal circuitry to innovate and refine design methodologies.
• Review and optimize circuit layouts, ensuring compliance with ESD and JEDEC standards for DDR interfaces.
• Participate in design reviews, provide technical input, and contribute to the continuous improvement of design flows and best practices.
• Document design processes, test plans, and results, supporting knowledge sharing and future project success.

Impact

• Drive the development of high-performance memory interface solutions that power next-generation technologies.
• Enhance the robustness and reliability of Synopsys' analog and mixed-signal IP portfolio.
• Ensure products meet or exceed industry standards, supporting customer success and market leadership.
• Influence cross-functional teams by sharing insights and best practices in circuit design and layout.
• Contribute to the delivery of cutting-edge silicon solutions for global semiconductor leaders.
• Support continuous innovation, helping Synopsys stay ahead in a competitive, fast-moving industry.

Requirements

• BTech/MTech in Electronics or Electrical Engineering.
• 1–3 years of experience in analog/mixed-signal circuit design, with expertise in CMOS processes and deep submicron technologies.
• Proficiency in CMOS circuit design and layout methodologies; experience with ESD concepts is a plus.
• Familiarity with ASIC design flows and JEDEC DDR interface requirements, including DDR Timing, ODT, and SDRAM functionality.
• Ability to work with cross-disciplinary teams to meet complex design specifications and project goals.

Team

You will join a world-class engineering team focused on analog and mixed-signal IP development for cutting-edge memory interfaces. Our team thrives on innovation, collaboration, and technical excellence, working closely with global experts to deliver industry-leading solutions for top-tier semiconductor clients. We foster an inclusive and supportive culture where every member's contributions are valued and professional growth is encouraged.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As we extend our project management team for High-Performance Computing (HPC) developments, we have a great job opportunity for you. In this interesting and challenging position as a project engineering manager (PEM) you will be responsible for the planning and execution of development projects which deliver leading-edge products for HPC applications.

You are a seasoned engineering professional with a passion for innovation and excellence. With a solid background in project management and engineering (at least 6 years of experience), you thrive in dynamic environments and excel at leading cross-functional teams to success. Your analytical mindset allows you to navigate complex challenges, and your communication skills ensure that all stakeholders are aligned and informed. You possess a deep understanding of engineering principles and are adept at applying them to real-world scenarios. Your proactive approach and attention to detail set you apart, and you are always looking for ways to improve processes and outcomes. You are not just a manager but a mentor and a leader, inspiring your team to achieve their best.

Key Responsibilities: Collaborate with cross-functional teams to define project requirements, scope, and objectives; Develop detailed project plans, including timelines, resource allocation, and risk management strategies; Monitor project progress and performance, identifying potential issues, and implementing corrective actions as needed; Communicate project status, updates, and milestones to stakeholders, ensuring transparency and alignment; Represent R&D on customer relationships, tracking execution to plan, aligning with senior leadership of team on mitigation and escalation management; Mentor and guide team members, fostering a collaborative and innovative work environment.

Impact: Driving the successful execution of engineering projects, contributing to Synopsys' reputation for excellence and innovation; Enhancing the efficiency and effectiveness of project management processes, leading to improved project outcomes; Facilitating cross-functional collaboration, ensuring that all teams are working towards common goals; Providing leadership and mentorship to team members, fostering their professional growth and development; Ensuring that projects are delivered on time, within scope, and within budget, contributing to the overall success of the organization; Identifying opportunities for process improvements and implementing best practices to enhance project delivery.

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You are an inventive and detail-oriented engineer with a strong foundation in Computer Science or Electronics, and a passion for advancing the frontiers of Design for Test (DFT) technology. With 3+ years of hands-on experience in DFT, scripting, and software automation, you are eager to take on complex challenges in the rapidly evolving semiconductor industry.

As a candidate, you possess a keen analytical mindset and enjoy problem solving, particularly when it comes to troubleshooting and root cause analysis. You are comfortable working closely with cross-functional teams, providing valuable feedback, and contributing to product readiness.

Your experience with scripting languages, RTL coding, and a variety of DFT technologies enables you to deliver scalable solutions tailored to customer architectures and methodologies. You embrace the opportunity to work with cutting-edge tools, including AI-enabled agents, and take pride in producing high-quality documentation and pragmatic solutions.

Elevate the quality and performance of Synopsys' industry-leading DFT tools, directly contributing to customer success and business growth.

Enable customers to implement robust test methodologies that improve silicon quality and accelerate time-to-market for advanced chips.

Drive innovation in DFT automation, making cutting-edge solutions accessible across diverse industry segments, from AI to mobile networking.

Strengthen Synopsys' reputation as a trusted partner in delivering scalable, reliable, and high-performance test solutions.

Facilitate cross-team knowledge sharing by providing actionable feedback and creating comprehensive documentation.

Advance the adoption of AI-driven testing and automation, keeping Synopsys at the forefront of technological advancement.

Support the seamless integration of new features and methodologies, ensuring Synopsys products remain competitive and future-ready.

Develop detailed test plans, incorporating new features into test cases, and executing/automating these test cases using Verilog, System Verilog, or VHDL.

Review specifications and test plans from other teams, offering feedback to ensure feature completeness and product readiness.

Collaborate with Product Engineering and R&D teams to create in-house test cases and implement scalable DFT solutions based on customer requirements.

Perform Quality of Results (QOR) analysis, troubleshooting, and root cause analysis to resolve complex technical issues across multiple aspects of the ASIC flow.

Focus on tool features such as DFT compression, ATPG for various fault models (SSAF, Transition Delay Fault, Cell-aware faults), and architecting solutions for Memory and Logic BIST.

Conduct diagnostics analysis and debugging to enhance tool reliability and performance.

Work with AI agents to review and create assistive or generative AI documentation for test products.

Manage performance, installation, and license testing to ensure seamless customer experience.

Bachelor's, Master's, or MTech in Electrical/Electronics Engineering, Computer Science, or a related field with 3+ years of relevant experience.

Hands-on expertise in DFT technologies such as JTAG, MBIST, Scan, and related test architectures.

Proficiency in RTL coding using Verilog, System Verilog, and/or VHDL.

Advanced scripting skills in Perl, Tcl/Tk, Python, or similar languages for automation and tool integration.

Familiarity with change management tools (e.g., Perforce) for collaborative development and version control.

Solid understanding of ASIC design flow, including design planning, synthesis, physical design, and sign-off verification tools.

Analytical thinker with exceptional problem-solving skills and a passion for troubleshooting complex technical challenges.

Effective communicator who excels in cross-functional team environments and can articulate technical concepts to varied audiences.

Collaborative team player who values diverse perspectives and actively contributes to group success.

Proactive and adaptable, with a strong desire to learn and innovate in a fast-paced, evolving technological landscape.

Detail-oriented and organized, able to manage multiple priorities and deliver high-quality results on schedule.

You'll join the Synopsys Test Group, a dynamic team focused on developing cutting-edge Design for Test (DFT) solutions.

The team is composed of passionate engineers and innovators who collaborate across product engineering and R&D to create industry-leading methodologies and tools.

Together, you will address challenges in diverse domains such as autonomous systems, AI, high-performance computing, and mobile networking, driving the next wave of silicon innovation.

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Applications Engineering, Principal Engineer

Sunnyvale, California, United States

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Hire Type EmployeeJob ID 17080Base Salary Range $184000-$276000Date posted 04/21/2026

You Are:

You are a seasoned professional with a passion for cutting-edge technology and a drive to solve complex technical challenges. With over 8 years of experience in IC design, verification, emulation, or FPGA prototyping, you have a deep understanding of ASIC design verification methodologies and are proficient with HDLs such as Verilog and VHDL. Your skillset extends to HVLs like SystemVerilog and you have a working knowledge of C/C++. You possess excellent problem-solving skills and can analyze and resolve intricate design verification and software validation issues. Your strong communication abilities enable you to work effectively with customers, sales, marketing, and R&D teams, ensuring the successful deployment and evaluation of Synopsys' emulation solutions.

What You’ll Be Doing:

• Deploying and evaluating Synopsys' emulation solutions to meet customer needs.

• Collaborating closely with customers to resolve complex technical issues related to ASIC/SoC designs.

• Providing pre-sales evaluations and post-sales support to ensure customer success.

• Developing technical collaterals to assist in the adoption of Synopsys products.

• Working with sales, marketing, and R&D teams to align on customer requirements and product enhancements.

• Continuously learning and staying updated with state-of-the-art verification flows from Synopsys.

The Impact You Will Have:

• Enabling customers to successfully deploy and utilize Synopsys' emulation solutions.

• Enhancing customer satisfaction by resolving complex technical issues efficiently.

• Driving the adoption of Synopsys' industry-leading verification solutions.

• Contributing to the development of cutting-edge ASIC/SoC designs.

• Supporting sales efforts by providing technical expertise during pre-sales evaluations.

• Shaping product enhancements based on customer feedback and market needs.

What You’ll Need:

• 8+ years of experience in IC design, verification, emulation, or FPGA prototyping.

• Strong knowledge of ASIC design verification methodologies.

• Proficiency in HDLs (Verilog/VHDL) and HVLs (SystemVerilog).

• Familiarity with C/C++ programming languages.

• Excellent communication and problem-solving skills.

The Team You’ll Be A Part Of:

You will join a dynamic and innovative team focused on providing the most complete verification solutions in the market. The team leverages Synopsys' industry-leading emulation platform, ZeBu, to deliver unparalleled performance and capacity in emulation. Collaborating with customers, sales, marketing, and R&D teams, you will play a crucial role in driving the successful deployment and adoption of Synopsys' emulation solutions.

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You are a highly motivated Principal Engagement Applications Engineer with over 15 years of hands-on experience in synthesis or place and route (P&R). You have a robust understanding of the most advanced CPU/GPU/NPU designs and are eager to work closely with R&D on driving product development and developing advanced HPC reference flow.

Your technical expertise allows you to demonstrate differentiated PPA results on the most advanced IP cores to win benchmarking and deploy HPC methodologies to our worldwide key customers to accelerate business growth. You thrive in dynamic environments and possess excellent communication skills, including a strong command of English.

Collaborate with R&D teams to drive product development and advanced HPC reference flow development for wide deployment. Demonstrate differentiated PPA results on CPU/GPU/NPU designs to showcase our technology's superiority. Provide technical support to key global customers to address PPA bottlenecks and design challenges on the most advanced HPC designs. Aggressively engage in worldwide critical benchmarks and deployments to ensure the highest quality and performance of designs. Utilize scripting languages such as Perl and Tcl for automation and optimization tasks. Stay updated with the latest advancements in ASIC design flow, VLSI, and CAD development to continually improve processes.

Enhance the performance and efficiency of advanced CPU, GPU, and NPU designs. Drive innovations that contribute to the success of Synopsys' cutting-edge technologies. Provide critical support that helps key customers overcome their PPA challenges. Contribute to the development of new features that keep Synopsys at the forefront of the industry. Improve the overall quality and reliability of our products through meticulous design and optimization. Foster strong relationships with global customers, reinforcing Synopsys' reputation as a leader in chip design and software security.

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As a Staff Engineer in our ASIC Digital Design team, you will be responsible for leading and driving ownership of critical areas of verification alongside a team of talented verification engineers. You will define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for Subsystem.

Your responsibilities will include specifying, building, enhancing, and maintaining state-of-the-art Subsystem top-level UVM-based System Verilog testbenches, integrating RTL and behavioral models. You will also code and debug test cases, including the creation of complex checkers and assertions using System Verilog/UVM.

In addition, you will extract and review functional coverage (FC) and code coverage metrics to ensure quality metric goals are met. You will manage regressions and contribute to the continuous improvement of verification strategies and test environments.

You will work closely with RTL designers and architects to ensure functional correctness and collaborate with a global team of experienced verification engineers, fostering knowledge sharing and professional growth.

As a Staff Engineer, you will have the opportunity to make a significant impact on the success of our Subsystem and contribute to the early detection and resolution of critical design issues, reducing time-to-market and silicon re-spins.

You will also enhance Synopsys' reputation as the premier provider of high-speed connectivity IP Subsystem through engineering excellence and innovation, and bolster Synopsys' leadership in chip design by ensuring our IP verification methodologies set industry standards.

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Staff DFT Applications Engineer

Bengaluru, Karnataka, India

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Hire Type EmployeeJob ID 16891Date posted 04/12/2026

A peek inside our office

Po Popal

Workplace Resources, Sr Director

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an inventive and detail-oriented engineer with a strong foundation in Computer Science or Electronics, and a passion for advancing the frontiers of Design for Test (DFT) technology. With 3+ years of hands-on experience in DFT, scripting, and software automation, you are eager to take on complex challenges in the rapidly evolving semiconductor industry. You excel in both independent and collaborative environments, thriving in project-oriented settings where you can develop, automate, and validate sophisticated DFT flows and methodologies. Your curiosity and drive for continuous learning make you adept at keeping up with the latest advancements in Autonomous Transportation, Mission Critical AI, High Performance Computing, and Mobile Networking.

As a candidate, you possess a keen analytical mindset and enjoy problem solving, particularly when it comes to troubleshooting and root cause analysis. You are comfortable working closely with cross-functional teams, providing valuable feedback, and contributing to product readiness. Your experience with scripting languages, RTL coding, and a variety of DFT technologies enables you to deliver scalable solutions tailored to customer architectures and methodologies. You embrace the opportunity to work with cutting-edge tools, including AI-enabled agents, and take pride in producing high-quality documentation and pragmatic solutions. Your exceptional communication and networking skills allow you to bridge gaps between engineering and R&D, ensuring the highest standards in test solutions.

What You’ll Be Doing:

• Developing detailed test plans, incorporating new features into test cases, and executing/automating these test cases using Verilog, System Verilog, or VHDL.

• Reviewing specifications and test plans from other teams, offering feedback to ensure feature completeness and product readiness.

• Collaborating with Product Engineering and R&D teams to create in-house test cases and implement scalable DFT solutions based on customer requirements.

• Performing Quality of Results (QOR) analysis, troubleshooting, and root cause analysis to resolve complex technical issues across multiple aspects of the ASIC flow.

• Focusing on tool features such as DFT compression, ATPG for various fault models (SSAF, Transition Delay Fault, Cell-aware faults), and architecting solutions for Memory and Logic BIST.

• Conducting diagnostics analysis and debugging to enhance tool reliability and performance.

• Working with AI agents to review and create assistive or generative AI documentation for test products.

• Managing performance, installation, and license testing to ensure seamless customer experience.

The Impact You Will Have:

• Elevate the quality and performance of Synopsys’ industry-leading DFT tools, directly contributing to customer success and business growth.

• Enable customers to implement robust test methodologies that improve silicon quality and accelerate time-to-market for advanced chips.

• Drive innovation in DFT automation, making cutting-edge solutions accessible across diverse industry segments, from AI to mobile networking.

• Strengthen Synopsys’ reputation as a trusted partner in delivering scalable, reliable, and high-performance test solutions.

• Facilitate cross-team knowledge sharing by providing actionable feedback and creating comprehensive documentation.

• Advance the adoption of AI-driven testing and automation, keeping Synopsys at the forefront of technological advancement.

• Support the seamless integration of new features and methodologies, ensuring Synopsys products remain competitive and future-ready.

What You’ll Need:

• Bachelor’s, Master’s, or MTech in Electrical/Electronics Engineering, Computer Science, or a related field with 3+ years of relevant experience.

• Hands-on expertise in DFT technologies such as JTAG, MBIST, Scan, and related test architectures.

• Proficiency in RTL coding using Verilog, System Verilog, and/or VHDL.

• Advanced scripting skills in Perl, Tcl/Tk, Python, or similar languages for automation and tool integration.

• Familiarity with change management tools (e.g., Perforce) for collaborative development and version control.

• Solid understanding of ASIC design flow, including design planning, synthesis, physical design, and sign-off verification tools.

Who You Are:

• Analytical thinker with exceptional problem-solving skills and a passion for troubleshooting complex technical challenges.

• Effective communicator who excels in cross-functional team environments and can articulate technical concepts to varied audiences.

• Collaborative team player who values diverse perspectives and actively contributes to group success.

• Proactive and adaptable, with a strong desire to learn and innovate in a fast-paced, evolving technological landscape.

• Detail-oriented and organized, able to manage multiple priorities and deliver high-quality results on schedule.

The Team You’ll Be A Part Of:

You’ll join the Synopsys Test Group, a dynamic team focused on developing cutting-edge Design for Test (DFT) solutions. The team is composed of passionate engineers and innovators who collaborate across product engineering and R&D to create industry-leading methodologies and tools. Together, you will address challenges in diverse domains such as autonomous systems, AI, high-performance computing, and mobile networking, driving the next wave of silicon innovation.

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You are a passionate engineer with a strong foundation in analog and mixed-signal circuit design, eager to make a tangible impact in the world of semiconductor innovation. You thrive in collaborative environments, working alongside diverse teams to solve complex technical challenges. With 1–3 years of experience and a solid academic background in Electronics or Electrical Engineering, you bring a keen understanding of CMOS processes and are adept at navigating deep submicron technologies. Your curiosity drives you to stay current with industry standards, including JEDEC requirements for DDR interfaces, and you are enthusiastic about mastering new methodologies and tools. You value quality and efficiency, consistently delivering robust designs that meet rigorous specifications. Your communication skills enable you to articulate technical concepts clearly and foster productive relationships within cross-functional teams. You are detail-oriented, self-motivated, and embrace opportunities to learn and grow. Whether tackling circuit design tasks or collaborating with system engineers, you demonstrate adaptability, integrity, and a commitment to excellence. Your proactive approach, analytical mindset, and willingness to take initiative make you an invaluable contributor to the team. If you are excited about working on cutting-edge memory interface solutions and contributing to the next generation of high-performance chips, Synopsys is the place for you.

Designing DDR/HBM Memory Interface I/O circuits, including GPIO and Special IOs, ensuring optimal performance and reliability. Collaborating with DDR/HBM PHY teams, package engineers, and system engineers to meet stringent design specifications and project goals. Executing circuit design tasks with a focus on quality, efficiency, and adherence to industry standards. Developing and refining analog/mixed signal circuitry, leveraging advanced CMOS technologies and layout methodologies. Contributing to the ASIC design flow, from concept to implementation, including verification and documentation. Communicating effectively with internal development teams, providing technical insights and feedback throughout the design process. Participating in design reviews, troubleshooting, and optimization activities to ensure robust and scalable solutions.

Accelerate the development of high-performance memory interfaces, integral to next-generation computing platforms. Enhance product quality and reliability by applying best practices in analog circuit design and layout. Drive innovation in deep submicron CMOS technologies, enabling advanced chip functionalities. Contribute to Synopsys’ leadership in DDR/HBM IP solutions, helping customers achieve breakthrough results. Foster a culture of collaboration and technical excellence across multidisciplinary teams. Support the delivery of robust, standards-compliant IP that powers industry-leading silicon solutions. Enable seamless integration and performance optimization for customers worldwide.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology. With 5-8 years of industry experience,primarily in Physical Verification (PV),you thrive on solving complex layout and verification challenges for advanced process nodes. You possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus. Your proficiency in scripting languages like Perl, Tcl, and Python enables you to automate and optimize PV runset development, ensuring high-quality deliverables.

What You'll Be Doing:

Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies. Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes. Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python. Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges. Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions. Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team. Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys' technical edge.

The Impact You Will Have:

Accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses. Ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market. Drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps. Enhance customer satisfaction by providing timely and expert solutions to complex verification challenges. Contribute to the development of next-generation verification methodologies and best practices within Synopsys. Strengthen Synopsys' reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.

What You'll Need:

B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field. 8-10 years of hands-on experience in the Physical Verification (PV) domain. Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS. Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development. Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements. Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks. Exposure to competitive EDA tools and awareness of their strengths and limitations.

Who You Are:

An analytical thinker with strong problem-solving abilities and meticulous attention to detail. A collaborative team player who fosters knowledge sharing and mentorship. Effective communicator, capable of translating technical concepts to diverse audiences. Adaptable and proactive, with a passion for continuous learning and innovation. Customer-focused, with a commitment to delivering high-quality solutions on time. Self-driven, organized, and able to manage multiple priorities in a fast-paced environment.

The Team You'll Be A Part Of:

You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You'll work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You Are: You are a passionate engineer with a strong foundation in analog and mixed-signal circuit design, eager to make a tangible impact in the world of semiconductor innovation. You thrive in collaborative environments, working alongside diverse teams to solve complex technical challenges. With 2+yrs experience and a solid academic background in Electronics or Electrical Engineering, you bring a keen understanding of CMOS processes and are adept at navigating deep submicron technologies.

What You'll Be Doing: Designing DDR/HBM Memory Interface I/O circuits, including GPIO and Special IOs, ensuring optimal performance and reliability. Collaborating with DDR/HBM PHY teams, package engineers, and system engineers to meet stringent design specifications and project goals. Executing circuit design tasks with a focus on quality, efficiency, and adherence to industry standards. Developing and refining analog/mixed signal circuitry, leveraging advanced CMOS technologies and layout methodologies. Contributing to the ASIC design flow, from concept to implementation, including verification and documentation. Communicating effectively with internal development teams, providing technical insights and feedback throughout the design process. Participating in design reviews, troubleshooting, and optimization activities to ensure robust and scalable solutions.

The Impact You Will Have: Accelerate the development of high-performance memory interfaces, integral to next-generation computing platforms. Enhance product quality and reliability by applying best practices in analog circuit design and layout. Drive innovation in deep submicron CMOS technologies, enabling advanced chip functionalities. Contribute to Synopsys' leadership in DDR/HBM IP solutions, helping customers achieve breakthrough results. Foster a culture of collaboration and technical excellence across multidisciplinary teams. Support the delivery of robust, standards-compliant IP that powers industry-leading silicon solutions. Enable seamless integration and performance optimization for customers worldwide.

What You'll Need: B.Tech/M.Tech degree in Electronics or Electrical Engineering. 2+ years of hands-on experience in CMOS circuit design, preferably with exposure to deep submicron process technologies. Proficiency in analog/mixed signal design methodologies and layout flows. Familiarity with JEDEC DDR interface requirements, DDR Timing, ODT, and SDRAM functionality is a strong plus. Basic understanding of ESD concepts and ASIC design flow. Demonstrated ability to execute assigned circuit design tasks with high quality and efficiency. Strong written and verbal communication skills for effective team interactions.

Who You Are: Analytical thinker with strong problem-solving skills. Collaborative and adaptable, thriving in dynamic team settings. Detail-oriented and quality-driven, with a commitment to excellence. Proactive, self-motivated, and eager to learn new technologies. Effective communicator, capable of conveying technical concepts clearly. Resilient and resourceful, able to navigate complex challenges.

The Team You'll Be A Part Of: You will join a highly skilled engineering team specializing in DR I/O circuit design for memory interfaces. The team is focused on developing innovative DDR/HBM solutions, collaborating closely with PHY, package, and system engineers. Together, you will drive advancements in chip performance, reliability, and integration, shaping the future of semiconductor technology.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Our team is focused on developing innovative DDR/HBM solutions, collaborating closely with PHY, package, and system engineers. Together, you will drive advancements in chip performance, reliability, and integration, shaping the future of semiconductor technology.

Key Responsibilities:

• Designing DDR/HBM Memory Interface I/O circuits, including GPIO and Special IOs, ensuring optimal performance and reliability.
• Collaborating with DDR/HBM PHY teams, package engineers, and system engineers to meet stringent design specifications and project goals.
• Executing circuit design tasks with a focus on quality, efficiency, and adherence to industry standards.
• Developing and refining analog/mixed signal circuitry, leveraging advanced CMOS technologies and layout methodologies.
• Contributing to the ASIC design flow, from concept to implementation, including verification and documentation.
• Communicating effectively with internal development teams, providing technical insights and feedback throughout the design process.
• Participating in design reviews, troubleshooting, and optimization activities to ensure robust and scalable solutions.

Requirements:

• B.Tech/M.Tech degree in Electronics or Electrical Engineering.
• 2+ years of hands-on experience in CMOS circuit design, preferably with exposure to deep submicron process technologies.
• Proficiency in analog/mixed signal design methodologies and layout flows.
• Familiarity with JEDEC DDR interface requirements, DDR Timing, ODT, and SDRAM functionality is a strong plus.
• Basic understanding of ESD concepts and ASIC design flow.
• Demonstrated ability to execute assigned circuit design tasks with high quality and efficiency.
• Strong written and verbal communication skills for effective team interactions.

Benefits:

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

Experience Level: Senior Employment Type: Full-time Workplace Type: Onsite Category: Engineering Industry: Technology Salary Range: Not stated Salary Min: Not stated Salary Max: Not stated Salary Currency: USD Salary Period: Year Required Skills: CMOS circuit design, analog/mixed signal design methodologies, layout flows, JEDEC DDR interface requirements, DDR Timing, ODT, SDRAM functionality, ESD concepts, ASIC design flow Preferred Skills: Not stated

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You are a passionate engineer with a strong foundation in analog and mixed-signal circuit design, eager to make a meaningful impact through your expertise. With a BTech or MTech and substantial hands-on experience (BTech+5 years / MTech+3 years), you have mastered the nuances of CMOS processes and deep submicron technologies. You enjoy solving complex challenges in DDR I/O circuit design and thrive in collaborative environments where your technical insights drive innovation.

Designing and developing DDR I/O circuits, ensuring robust performance and compliance with industry standards. Collaborating with cross-functional teams on analog and mixed-signal circuit architecture and implementation. Performing circuit simulations, layout reviews, and post-layout analysis to optimize designs for performance and reliability. Integrating ESD protection and addressing deep submicron process challenges in circuit development. Contributing to ASIC design flows and participating in design reviews to ensure quality and manufacturability. Documenting design methodologies, results, and communicating effectively with internal development teams. Interfacing with verification and validation teams to support the testing and debugging of DDR I/O circuits.

Deliver innovative DDR I/O circuit designs that enable high-speed, reliable data transfer in advanced silicon products. Enhance product quality and efficiency through rigorous design practices and attention to detail. Drive the adoption of best practices in CMOS and mixed-signal design across teams. Support Synopsys' leadership in chip design by contributing to differentiated IP solutions. Facilitate faster time-to-market for cutting-edge semiconductor products by ensuring robust design and integration. Mentor and collaborate with junior engineers, fostering a culture of excellence and continuous improvement. Strengthen Synopsys' reputation for technical innovation and reliability in the semiconductor industry.

BTech+5 years or MTech+3 years in Electrical/Electronics Engineering or related discipline. Expertise in CMOS circuit design and layout methodology, with experience in deep submicron process technologies. Understanding of analog/mixed signal circuitry and basic ESD concepts. Familiarity with ASIC design flow and JEDEC DDR interface standards, including DDR Timing, ODT, and SDRAM functionality. Strong skills in executing assigned circuit design tasks efficiently and to the highest quality standards. Proficiency in circuit simulation tools and layout review processes.

Detail-oriented, methodical, and committed to delivering high-quality results. Collaborative and effective in cross-team communication. Adaptable and able to manage multiple priorities in a fast-paced environment. Curious and eager to learn about new technologies and industry trends. Proactive problem-solver with strong analytical skills. Clear communicator, both verbally and in writing.

You will join a dynamic team of analog and mixed-signal engineers focused on developing industry-leading DDR I/O solutions. The team fosters an inclusive culture, values diverse perspectives, and collaborates closely with digital, verification, and layout experts to deliver world-class products. Together, you'll push the boundaries of semiconductor innovation, leveraging collective expertise to solve complex challenges and achieve technical excellence.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Your primary responsibilities will include:

• Identifying emerging music trends, scenes, and culturally relevant moments, ensuring Spotify's local programming is timely, authoritative, and impactful.
• Curating cohesive, engaging music experiences for Norway & Finland with compelling descriptions and commentary that resonate with audiences.
• Analyzing user behavior and performance data to optimize playlist engagement and make informed editorial decisions.
• Collaborating with global and regional editorial teams on programming initiatives and strategies to enhance Spotify's market position.
• Contributing creative editorial ideas and formats that bring playlists and music stories to life, occasionally participating in written, video or audio content.
• Partnering with Artist & Label Partnerships, Marketing, Comms, Product, and other teams to align editorial priorities with broader initiatives.
• Supporting artist discovery and helping grow fanbases for artists in Norway & Finland through editorial projects and internal workflows.

To succeed in this role, you will need to have:

• 4+ years of experience in the music industry, journalism, or programming/curating music across digital, radio, TV, or similar platforms.
• Deep knowledge of Nordic music and culture, especially Norway and Finland.
• Broad genre expertise,from Hip-Hop to Pop, Indie to Dance or Rock,and the ability to curate across moods, moments, and audiences.
• Comfortable using data and analytics to inform decisions and improve performance.
• Strong cultural awareness and the ability to evaluate trends, emerging movements, and audience behavior beyond just the data.
• Familiarity with Google Suite and comfort using basic design tools to create visual assets such as playlist covers when needed.
• Strong communication skills and the ability to connect with audiences through written, video, or audio formats.
• Organized, detail-oriented, adaptable, and a collaborative, positive approach to teamwork.

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In this role, you will define FPGA architectures, implement high-performance digital logic, and collaborate closely with hardware, firmware, and quantum engineering teams to build scalable, low-latency control systems.

Key responsibilities include: Developing and improving a custom microprocessor responsible for waveform generation and critical logic to operate a quantum computer Working closely with hardware, firmware, and software teams to define architecture, data flow, and interfaces Implementing, simulating, and verifying designs including DSP pipelines, control logic, and high-speed I/O Optimizing designs for latency, resource utilization, and robustness in production environments Developing and maintaining testbenches, verification flows, and CI Supporting bring-up, lab validation, and debugging in collaboration with Quantum Engineering on actual quantum computers Contributing to the long-term roadmap for the architecture of Rigetti’s control systems.

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Your responsibilities will include:

• Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.
• Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.
• Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.
• Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges.
• Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions.
• Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team.
• Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys' technical edge.

You will accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses. You will ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market. You will drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps. You will enhance customer satisfaction by providing timely and expert solutions to complex verification challenges. You will contribute to the development of next-generation verification methodologies and best practices within Synopsys. You will strengthen Synopsys' reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.

To be successful in this role, you will need:

• B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.
• 5-8 years of hands-on experience in the Physical Verification (PV) domain.
• Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.
• Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.
• Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.
• Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.
• Exposure to competitive EDA tools and awareness of their strengths and limitations.

You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

Rewards and benefits include a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Key responsibilities include:

• Design Implementation experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)
• RTL to GDSII full flow experience or knowledge is preferable
• Strong interest and understanding of Advanced Node & Design methodologies are required.
• In-depth Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.
• Knowledge of several Clock Tree Synthesis methodologies like H-Tree, MS-CTS is preferred
• Back end P&R tools (Fusion Compiler, ICC2, Innovus)
• Excellent verbal and written presentation/communication skills are mandatory.

Requirements include:

• BSEE or equivalent, required with 7+ years of experience, or MSEE, or equivalent with 5+ years of experience.
• Tool knowledge: front end Synthesis and back end PnR tools (Fusion Compiler, ICC2, Design Compiler, Genus),
• Tool knowledge: STA (Primetime, Tempus)

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

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As a Sr Engineer, you will collaborate closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes. You will automate qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.

Responsibilities:

• Develop and validate DRC, LVS, and Fill runsets for the Synopsys IC Validator tool
• Collaborate with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes
• Automate qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python
• Troubleshoot and resolve complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges
• Interface directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions
• Mentor junior team members, share best practices, and contribute to a knowledge-sharing culture within the team

Impact:

• Accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses
• Ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market
• Drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps
• Enhance customer satisfaction by providing timely and expert solutions to complex verification challenges
• Contribute to the development of next-generation verification methodologies and best practices within Synopsys
• Strengthen Synopsys' reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support

Requirements:

• B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field
• 5-8 years of hands-on experience in the Physical Verification (PV) domain
• Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS
• Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development
• Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements
• Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks
• Exposure to competitive EDA tools and awareness of their strengths and limitations

Who You Are:

• An analytical thinker with strong problem-solving abilities and meticulous attention to detail
• A collaborative team player who fosters knowledge sharing and mentorship
• Effective communicator, capable of translating technical concepts to diverse audiences
• Adaptable and proactive, with a passion for continuous learning and innovation
• Customer-focused, with a commitment to delivering high-quality solutions on time
• Self-driven, organized, and able to manage multiple priorities in a fast-paced environment

The Team You’ll Be A Part Of:

You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You’ll work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process

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The successful candidate will have a BS/MS/PhD in Electronics Engineering or Telecommunications and 2+ years of experience in RTL design for ASIC or PHY IP. You will have experience with VCS, Verdi, Spyglass, Perl/TCL/Python and knowledge of clock domain crossing, APB, JTAG. Good English communication skills are essential.

As a member of our team, you will advance industry-leading high bandwidth interface IP, ensure robust design and verification processes, drive innovation in RTL design and workflows, and enhance productivity through automation.

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Applications Engineering, Sr Engineer

Hsinchu, Taiwan

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Category: EngineeringHire Type: Employee

Job ID 15949Date posted 03/08/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a proactive, customer-oriented engineer passionate about advancing semiconductor technologies. You thrive in fast-paced environments and are eager to solve complex technical challenges, collaborating with leading foundries and design teams. You possess a strong foundation in ASIC design flow, VLSI, and CAD engineering, and are comfortable navigating the intricacies of EDA tools and physical design. Your communication skills enable you to build trust with customers, translating their needs into actionable solutions and ensuring seamless product implementation. You are resourceful, adaptable, and able to exercise sound judgment while tackling technical issues. Your creative approach to problem-solving and drive for excellence enable you to contribute meaningfully to both individual projects and broader team initiatives. You value diversity and inclusivity, and you are committed to continuous learning, staying current with industry trends and emerging technologies. By joining Synopsys, you seek to make a tangible impact on the future of high-performance silicon, and you are motivated by opportunities to grow, innovate, and collaborate in a global, supportive environment.

What You’ll Be Doing:

• Managing and providing ICV runset support for key foundry customers, ensuring optimal product performance and customer satisfaction.

• Delivering post-sales technical expertise during the runset programming, implementation, and maintenance of Synopsys products.

• Implementing detailed customer installation requirements and customizing solutions to fit unique client environments.

• Ensuring client needs are met and that Synopsys solutions function according to technical specifications and industry standards.

• Collaborating with sales teams to provide pre-sales technical support, contributing to successful business development and customer onboarding.

• Troubleshooting and resolving moderately complex technical issues

• Empowering customers to efficiently deploy and maximize the value of Synopsys EDA solutions in their design workflows.

• Enhancing customer satisfaction and strengthening long-term partnerships with key foundry clients.

• Driving successful product adoptions and implementations, contributing directly to Synopsys’ market leadership.

• Supporting the technical excellence of customer projects, enabling innovative chip design and verification outcomes.

• Facilitating knowledge transfer, helping customers understand and leverage advanced product features.

• Identifying opportunities for product improvements and feeding insights back to development teams for continuous innovation.

What You’ll Need:

• Basic understanding of the design process, with a preference for Design Rule Checking (DRC).

• Solid grasp of ASIC design flow, VLSI concepts, and/or CAD engineering principles.

• Familiarity with competitive EDA tool products and expertise in areas such as Verification, Place and Route, Design Reuse, and/or Physical Design.

• Ability to manage projects from initiation through completion, delivering high-quality technical solutions.

• Creative problem-solving skills and the ability to exercise judgment in selecting methods and techniques to obtain solutions.

Who You Are:

• Collaborative and effective communicator, able to build strong relationships with customers and internal teams.

• Resourceful and adaptable, thriving in dynamic, fast-paced environments.

• Detail-oriented with strong analytical skills and a commitment to delivering exceptional results.

• Open-minded and inclusive, embracing diverse perspectives and fostering an environment of belonging.

• Self-motivated and eager to learn, continuously seeking opportunities for growth and innovation.

The Team You’ll Be A Part Of:

You will join the Customer Application Services team, a group of passionate engineers dedicated to delivering technical excellence and customer success. The team works closely with foundries, design teams, and sales professionals, providing deep expertise and support throughout the product lifecycle. You’ll collaborate in a culture of innovation, knowledge sharing, and mutual respect, where every member’s contribution is valued and celebrated.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As an Analog Design Engineer at Synopsys, you will be designing DDR I/O circuits for high-performance silicon IP, ensuring compliance with industry standards and customer requirements. You will also develop and optimize analog/mixed-signal circuit architectures, focusing on performance, power, and area efficiency.

Key responsibilities include:

• Designing DDR I/O circuits for high-performance silicon IP
• Developing and optimizing analog/mixed-signal circuit architectures
• Executing circuit design tasks using advanced CMOS processes and state-of-the-art layout methodologies
• Collaborating with internal development teams to integrate analog blocks into ASIC and SoC designs
• Assessing and resolving issues related to deep submicron process technologies

The ideal candidate will have a BTech/MTech in Electrical Engineering or related field, with strong knowledge of CMOS processes and deep submicron technology challenges. You should also have hands-on experience with analog/mixed-signal circuit design and layout methodologies, as well as familiarity with ASIC design flow and integration of analog blocks.

At Synopsys, we offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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At Google DeepMind, we've built a unique culture and work environment where long-term ambitious research can flourish. We are a team of scientists, engineers, machine learning experts and more, working together to advance the state of the art in artificial intelligence.

The role requires a blend of deep technical expertise, strategic thinking, and strong leadership. You will lead a multi-disciplinary team to evolve the software side of our hw-sw co-design project.

Responsibilities:

• Closely collaborate with our hardware team to define and drive strategy for next-generation machine learning accelerators.
• Manage relationships and technical execution across a virtual team that spans both Google and outside partners.
• Drive the team to deliver high-quality aligned to tight schedules.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 10+ years of experience in ASIC design and development.
• 3+ years of Management Experience
• Proven track record of technical leadership and successfully delivering complex silicon projects (tape-outs) to production.
• Deep expertise in at least one core silicon discipline (e.g., RTL, PD, DV) and strong familiarity with the entire ASIC flow.
• Experience with managing silicon vendors and other external partners.

Preferred Qualifications:

• Master's or Ph.D. in a related field.
• Experience leading and managing teams across the full silicon development cycle, from RTL to bringup.
• Experience with high-performance compute IPs (e.g., GPUs, ML accelerators).
• Knowledge of high-performance and low-power architectures for ML acceleration.
• Excellent communication, and leadership skills.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

We are seeking an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology.

With 5-8 years of industry experience—primarily in Physical Verification (PV)—you thrive on solving complex layout and verification challenges for advanced process nodes.

You possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus.

Your proficiency in scripting languages like Perl, Tcl, and Python enables you to automate and optimize PV runset development, ensuring high-quality deliverables.

You are committed to continuous learning and improvement, keeping pace with evolving foundry processes and design for manufacturability (DFM) requirements.

As a natural collaborator and mentor, you enjoy guiding junior team members and fostering a supportive team environment.

Your excellent communication skills empower you to engage confidently with customers and field application engineers (FAEs), translating complex requirements into innovative solutions.

You are detail-oriented, resourceful, and dedicated to exceeding customer expectations, making you a valuable asset to any high-performing engineering team.

Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.

Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.

Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.

Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges.

Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions.

Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team.

Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys’ technical edge.

Accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses.

Ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market.

Drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps.

Enhance customer satisfaction by providing timely and expert solutions to complex verification challenges.

Contribute to the development of next-generation verification methodologies and best practices within Synopsys.

Strengthen Synopsys’ reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.

B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.

5-8 years of hands-on experience in the Physical Verification (PV) domain.

Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.

Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.

Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.

Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.

Exposure to competitive EDA tools and awareness of their strengths and limitations.

An analytical thinker with strong problem-solving abilities and meticulous attention to detail.

A collaborative team player who fosters knowledge sharing and mentorship.

Effective communicator, capable of translating technical concepts to diverse audiences.

Adaptable and proactive, with a passion for continuous learning and innovation.

Customer-focused, with a commitment to delivering high-quality solutions on time.

Self-driven, organized, and able to manage multiple priorities in a fast-paced environment.

Join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design.

Work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a skilled and passionate engineer with expertise in system design, embedded firmware, digital design, and verification with over 8+ years of experience. You are a skilled engineer with technical leadership, strategic thinking, and ability to model, architect, and validate mixed-signal SoC development, seeking to make a tangible impact in the semiconductor industry. You value collaboration and mentorship, welcoming opportunities to both learn from and share knowledge with your peers. Your experience with memory interface protocols such as DDR, LPDDR and HBM enables you to quickly contribute to our next-generation solutions.

Technical knowledge in latest DDR, LPDDR, MRDIMM and DFI protocols, with a proven track record in working successfully in IP product developments while focused on verification. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Work hands-on, having a collaborative mindset, thinking clearly and concisely when capturing requirements, and maintaining a proactive attitude to achieve results. You are passionate about right first-time development, ensuring traceability of all verification requirements and covering the whole ecosystem of Controller and PHY.

You bring knowledge of system, digital, firmware design, high-speed memory interface skills. Your experience includes delivering "best-in-class" solutions for protocols like DDR, LPDDR, and HBM. You are highly proficient in creating and using robust verification environments using UVM methodology and System Verilog, and you leverage system level modeling using advanced tools such as MATLAB and scripting languages, Perl, Python, and C++ to automate design and validation flows.

What You’ll Be Doing:

• Developing and optimizing embedded firmware for advanced DDR/LPDDR/HBM memory interface PHYs
• Contributing and collaborating with hardware teams to analyze and debug embedded firmware
• Optimizing and developing new PHY training algorithms using system level modeling tools
• Collaborating closely with analog, digital, and hardware teams to ensure overall system integrity
• Bridging the gap between pre- and post-silicon verification to ensure best-in-class customer support
• Developing and deploying tests on silicon as part of bring up plan with extensive knowledge of the design internals
• Reproducing silicon failures on FPGA/Emulation to identify root causes
• Fostering technical excellence and knowledge sharing across the organization.

The Impact You Will Have:

• Enhancing cross-functional collaboration to improve product quality and end customer satisfaction.
• Evolving/adopting and integrating best-in-class methodologies within the organization for fast silicon bring-up
• Standardizing and optimizing workflows to increase efficiency and compliance.
• Accelerating product innovation and time-to-market by establishing best practices to bridge the gap between architecture and physical implementation using system modeling, functional simulation emulation, and system integration.
• Directly impact customer success by providing guidance, technical support, and innovative solutions.
• Champion diversity and inclusion, ensuring a respectful and opportunity-rich workplace for all team members.

What You’ll Need:

• 8+ years of experience in Firmware, ASIC design, verification, system validation, and technical roles.
• Be results driven
• Proven leadership in developing, optimizing, and verifying SW/HW using UVM-based co-verification environment.
• Advanced scripting proficiency in Shell, Perl, Python, and C++ for workflow automation and process improvement.
• In-depth knowledge of system-level validation for high-speed interface PHY
• Proven track record of working cross-functionally and driving issues to closure
• Knowledge of mixed-signal design
• Experience in working in cross-functional collaborations
• Be an excellent communicator and a beacon for change

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity:

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a skilled and passionate engineer with deep expertise in system design, embedded firmware, digital design, and verification with over 15 years of impactful experience. You are a highly accomplished engineer with technical leadership, strategic thinking, and ability to model, architect, and validate mixed-signal SoC development, seeking to make a tangible impact in the semiconductor industry.

A technical powerhouse as well as subject matter expert in latest DDR, LPDDR, MRDIMM and DFI protocols, with a proven track record in working successfully in IP product developments while focused on verification. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Work hands-on, having a collaborative mindset, thinking clearly and concisely when capturing requirements, and maintaining a proactive attitude to achieve results.

You bring a deep understanding of system, digital, firmware design, high-speed memory interface architectures. Your experience includes leading multi-disciplinary teams, driving technical roadmaps, and mentoring engineers to deliver best-in-class solutions for protocols like DDR, LPDDR, and HBM. You are highly proficient in creating and using robust verification environments using UVM methodology and System Verilog, and you leverage system level modeling using advanced tools such as MATLAB and scripting languages, Perl, Python, and C++ to automate design and validation flows.

What You'll Be Doing:

• Developing and optimizing embedded firmware for advanced DDR/LPDDR/HBM memory interface PHYs
• Contributing and collaborating with hardware teams to analyze and debug embedded firmware
• Optimizing and developing new PHY training algorithms using system level modeling tools
• Collaborating closely with analog, digital, and hardware teams to ensure overall system integrity
• Bridging the gap between pre- and post-silicon verification to ensure best-in-class customer support
• Developing and deploying tests on silicon as part of bring up plan with extensive knowledge of the design internals
• Reproducing silicon failures on FPGA/Emulation to identify root causes
• Mentoring and coaching engineering teams, fostering technical excellence and knowledge sharing across the organization.
• Collaborating with cross-functional groups and customers to resolve challenges, ensure quality design, and meet aggressive project milestones.
• Driving continuous improvement in functional and performance testing on hardware and test-chips, and leading architectural refinements based on analysis.

The Impact You Will Have:

• Enhancing cross-functional collaboration to improve product quality and end customer satisfaction.
• Evolving/adopting and integrating best-in-class methodologies within the organization for fast silicon bring-up
• Standardizing and optimizing workflows to increase efficiency and compliance.
• Accelerating product innovation and time-to-market by establishing best practices to bridge the gap between architecture and physical implementation using system modeling, functional simulation emulation, and system integration.
• Driving cross-team synergy, technical mentorship, and a culture of continuous learning and inclusivity.
• Directly impact customer success by providing expert guidance, technical support, and innovative solutions.
• Champion diversity and inclusion, ensuring a respectful and opportunity-rich workplace for all team members.

What You'll Need:

• 15+ years of experience in Firmware, ASIC design, verification, system validation, and technical leadership roles.

• Be results driven

• Proven leadership in developing, optimizing, and verifying SW/HW using UVM-based co-verification environment.

• Advanced scripting proficiency in Shell, Perl, Python, and C++ for workflow automation and process improvement.

• In-depth knowledge of system-level validation for high-speed interface PHY

• Proven track record of working cross-functionally and driving issues to closure

• Knowledge of mixed-signal design

• Experience in working in cross-functional collaborations

• Be an excellent communicator and a beacon for change

• Excellent debugging, analytical, and problem-solving skills

• Working knowledge of scripting in languages such as Python and/or Perl

• Good understanding of DFT, ATPG, and design for debug techniques and their application in testing of silicon

• Good interpersonal skills, ability & desire to work as a standout colleague

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity:

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

#LI-DP1

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• Health & Wellness
• Time Away
• Family Support
• ESPP
• Retirement Plans
• Compensation

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What you'll do

• Providing technical guidance and hands-on support to customers integrating Synopsys Interface IP (PCI Express and High Speed SerDes design) into their ASIC SoC/systems
• Conducting detailed integration reviews at key customer milestones and troubleshooting complex integration challenges throughout the SoC design flow.

What you need

• Bachelor's and/or masters with a minimum 10+yrs of Industry experience or equivalent
• At least 5+ years of experience in IP design, ASIC/SoC integration, or related customer-facing engineering roles (exceptional candidates with strong silicon debug and academic background considered)
• Solid understanding of ASIC design flows, including simulation/verification, RTL synthesis, floorplanning, physical design, and timing closure
• Hands-on expertise in integration and validation of High Speed SerDes IPs for PCIe, ETH, USB

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What you'll do

• Reviewing and analyzing customer and partner feedback to enhance product and solution performance.
• Collaborating with R&D to shape technical roadmaps, specifications, and validation processes for product improvements.
• Diagnosing, troubleshooting, and resolving complex technical issues on-site and remotely for customer installations.

What you need

• BS or MS in Electrical or Computer Engineering.
• 6-8 years of relevant experience in the semiconductor industry.
• Hands-on expertise with Place & Route (P&R), extraction, Static Timing Analysis (STA), and Engineering Change Order (ECO) tools.

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What you'll do

• Supporting post-sales integration and silicon bring-up of Memory Interface PHY IPs and Controller IPs.
• Delivering insightful technical presentations and hands-on training sessions to both internal teams and external customers.
• Creating clear, detailed documentation and user collateral to facilitate customer understanding and product usability.

What you need

• Direct experience with Memory Interface PHY IPs and Controller IPs integration and bring-up.
• Solid knowledge of AMBA/AXI bus interfaces, floor-planning, and backend engineering for ASIC design.
• Proficiency with Linux, Verilog/VHDL, and modern ASIC design flows.

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What you'll do

• Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.
• Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.

What you need

• B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.
• 5-8 years of hands-on experience in the Physical Verification (PV) domain.
• Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.
• Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.
• Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.
• Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.
• Exposure to competitive EDA tools and awareness of their strengths and limitations.

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What you'll do

You will be responsible for delivering post-sales technical expertise throughout the runset programming, implementation, and ongoing maintenance cycles.

• Managing and providing ICV runset support for key foundry partners, ensuring seamless integration and optimal performance of Synopsys products.
• Delivering post-sales technical expertise throughout the runset programming, implementation, and ongoing maintenance cycles.
• Translating detailed customer installation requirements into actionable solutions, customizing product configurations as needed.
• Collaborating with clients to ensure their needs are fully met and Synopsys solutions function according to specifications.
• Offering pre-sales technical support, contributing to sales efforts by addressing technical queries and demonstrating product capabilities.
• Serving as a subject matter expert in EDA tool products, guiding customers through verification, place and route, design reuse, and physical design challenges.

What you need

• Basic understanding of the design process; familiarity with Design Rule Manuals (DRM) is preferred.
• Strong communication skills, capable of conveying technical concepts clearly to diverse audiences.
• Solid grasp of ASIC design flows, VLSI, and/or CAD engineering principles.
• Experience or knowledge of competitive EDA tool products, with expertise in verification, place and route, design reuse, and/or physical design.

What you'll be doing

You will be working as a Sr Staff Engineer in the R&D Engineering team, responsible for delivering post-sales technical expertise and managing ICV runset support for key foundry partners.

Why this matters

This role is critical in ensuring the successful implementation of Synopsys solutions and meeting customer needs.

Why you'll love it

You will have the opportunity to work with a talented team of engineers and contribute to the development of cutting-edge EDA tools.

What you'll need

• 5+ years of experience in EDA tool development, with a focus on ASIC design flows, VLSI, and/or CAD engineering principles.
• Strong understanding of competitive EDA tool products, with expertise in verification, place and route, design reuse, and/or physical design.
• Excellent communication and problem-solving skills, with the ability to convey technical concepts clearly to diverse audiences.
• Experience working with foundry partners and delivering post-sales technical expertise.

What you'll get

• Competitive salary and benefits package.
• Opportunity to work with a talented team of engineers and contribute to the development of cutting-edge EDA tools.
• Professional development opportunities, including training and mentorship.

How to apply

If you are a motivated and experienced engineer looking for a new challenge, please submit your application, including your resume and a cover letter, to [insert contact information].

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What you'll do

• Understanding and documenting project scope, requirements, and deliverable dependencies across multiple cross-functional teams.
• Leading regular and ad hoc sync-up meetings with internal teams and customers to align goals, clarify requirements, and drive progress.

What you need

• MSEE/BSEE or MSCE/BSCE with 15+ years' experience in ASIC design and project management.
• Deep understanding of ASIC design flow (RTL to physical implementation) and familiarity with advanced EDA tools (e.g., Synopsys EDA tools).

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What you'll do

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

• Designing and verifying complex ASIC digital and mixed-signal systems using Verilog or VHDL.
• Analyzing digital and analog specifications to develop robust system-level designs.

What you need

• Master’s degree in Electrical Engineering or related field, with at least 5 years of relevant industry experience.
• Proficient in Verilog or VHDL for digital design and verification.

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What you'll do

• Engaging in business development and customer meetings to identify and drive business opportunities.
• Defining and promoting products to achieve sustainable growth within the USB Solution IP product lines.

What you need

• BS EE with 10+ years of relevant experience, or MS EE with 8+ years of relevant experience (MBA preferred).
• Experience in product marketing or technical marketing, preferably in system-level, ASIC, or system-on-chip design.
• Knowledge of USB protocol, mixed signal, and semiconductor chip design.
• Ability to analyze market segments and applications.

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