This role involves defining, implementing, and tracking comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.

Key responsibilities include building, enhancing, and maintaining top-level UVM-based System Verilog testbenches and AMS co-simulation environments, integrating RTL, behavioral models, and transistor-level netlists.

The ideal candidate will have a strong foundational understanding of analog circuits, expertise with AMS tools such as HSPICE, XA, Custom Sim, VCS, and proficiency with System Verilog/UVM.

As a member of the Synopsys IPG Co-Simulation (COSIM) team, you will collaborate closely with mixed-signal designers, modeling engineers, and system architects across global Synopsys teams to deliver best-in-class IP.

In this role, you will enable the successful verification and deployment of high-performance SERDES and mixed-signal IP in leading-edge SoCs worldwide.

Synopsys is a comprehensive range of health, wellness, and financial benefits to cater to your needs.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

We consider all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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What you'll do

• Define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.
• Build, enhance, and maintain top-level UVM-based System Verilog testbenches and AMS co-simulation environments, integrating RTL, behavioral models, and transistor-level netlists.

What you need

• Bachelor's or master's degree in electrical engineering or a related field.
• Strong foundational understanding of analog circuits (op-amps, bandgaps, PLLs, ADCs, TX/RX components, etc.).
• Experience with AMS tools such as HSPICE, XA, Custom Sim, VCS, and scripting languages like Python, Perl, and UNIX shell.

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