Introduction: We drive technology innovations that shape the way we live and connect. Catalyzing the era of pervasive intelligence, we deliver design solutions, from electronic design automation to silicon IP, to system design and multiphysics simulation and analysis. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

Internship Experience: At Synopsys, interns dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide,and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today!

Mission Statement: Our mission is to fuel today’s innovations and spark tomorrow’s creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive,both at work and beyond.

Responsibilities:

• Develop and support microprojects related to 5G–6G and next-generation communication systems.
• Perform high-frequency electromagnetic simulations (microwave, mmWave, sub-THz) using Ansys HFSS and related tools.
• Investigate electromagnetic challenges in miniaturization, high-speed interconnects, antenna design, and packaging.
• Translate academic research topics into reproducible simulation examples and demonstrators for universities.
• Generate educational content and learning materials based on developed microprojects to support teaching and academic engagement.
• Support internal strategic initiatives in high-frequency and RF simulation domains, strengthening Synopsys’ academic presence through technical collaboration, workshops, and research-oriented deliverables.

Requirements:

• Graduating this year from a master's degree in telecommunications/electrical engineering
• Solid knowledge of electromagnetic theory and high-frequency systems.
• Experience with electromagnetic (EM) simulation tools (especially Ansys HFSS).
• Programming skills in Python or MATLAB, with an interest in automation and AI/ML.
• Familiarity with RF, antennas, IC/PCB modeling, and advanced packaging topics (preferred).
• Strong analytical and problem-solving abilities (preferred).
• Technical curiosity and motivation to explore emerging technologies.
• Clear and structured communication skills in academic, collaborative, and multicultural contexts.
• Proactive attitude, sense of ownership, and collaborative mindset.
• Adaptability and willingness to learn new tools, domains, and methodologies.
• Detail-oriented approach with a solid system-level perspective.
• Creativity in developing demonstrators or translating research into practical simulations.
• Strong organizational skills to manage and prioritize multiple projects.

Key Program Facts:

• Program Length: 12 months
• Location: Madrid office, Spain
• Working Model: In-office, Flex. Remote work can be discussed.
• Full-Time/Part-Time: Full time
• Start Date: Summer 2026 or September 2026

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About the Team:

OpenAI's Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI's supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

Role Overview

We are seeking an experienced engineer to lead the development of advanced packaging technologies that enable next-generation, high-performance compute systems. This role sits at the intersection of chip architecture, package integration, and manufacturing scale-up, driving breakthroughs in performance, power, thermal, and reliability. The ideal candidate brings deep expertise in 2.5D and 3.5D large-reticle integration and Co-Packaged Optics (CPO) packaging, with a proven ability to translate advanced concepts into qualified, high-volume production solutions.

In this role you will:

• Architect, develop, and prototype advanced packaging solutions (2.5D/3D integration, large-format interposers/bridges, high-density substrates, advanced assembly flows), and drive end-to-end qualification for high-volume production.

• Develop packaging concepts and requirements to support CPO packaging, including optical/electrical co-integration considerations, thermal/mechanical constraints, and high-volume manufacturability.

• Lead large-reticle and multi-die integration strategies, including mechanical/thermal co-design, warpage control, and yield/reliability risk mitigation across package scale-up.

• Identify and solve fundamental technical challenges in package architecture, integration, and manufacturability for high-performance compute chips.

• Collaborate closely with cross-functional teams (silicon architecture, SI/PI, thermal, mechanical, system, test, and manufacturing) to align package development with product requirements and program milestones.

• Drive vendor engagement and technical alignment with external partners (foundry/OSAT/material/tool vendors), including technology selection, DOE planning, and qualification readiness.

You might thrive in this role if you have:

• Large-reticle / large-body-size integration, including interposer/bridge-based architectures, package-scale mechanical/thermal risk management, and manufacturability at scale.

• Hands-on experience with CPO packaging, including package-level optical integration constraints and cross-domain trade-offs (electrical/optical/thermal/mechanical).

• Proven track record developing and productizing large-format, high-power, high-speed advanced packaging technologies for high-performance compute products.

• In-depth expertise across advanced packaging techniques and platforms used in the semiconductor industry (2.5D, 3D stacking, interposers/bridges, high-density substrates, advanced materials and assembly).

• Strong understanding of chip–package co-design: how chip architecture, I/O, power delivery, and floorplan decisions interact with packaging architecture and constraints.

Preferred Qualifications

• Solid understanding of thermal and mechanical interactions in large-format packages (warpage, stress, lid/heat-spreader/cold-plate interfaces, material interactions).

• Working knowledge of reliability requirements and qualification methodologies for advanced packages (JEDEC/industry practices, failure analysis, DOE-driven learning cycles).

• Familiarity with system-level considerations and chip architecture fundamentals (I/O topology, HBM/advanced memory integration, SI/PI constraints, module-to-system integration).

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