Design on-chip Process, Voltage, Temperature, glitch, and Droop monitors for silicon biometrics and reliability.

Execute digital backend activities, including synthesis, pre-layout STA, SDC constraints development, floor planning, bump placement, power planning, MV design techniques, VCLP, UPF understanding, placement, CTS, and routing.

Drive post-layout STA, timing and functional ECO development, and timing signoff methodology for high-frequency IP design closure.

Perform physical verification tasks such as DRC, LVS, PERC, ERC, Antenna, EMIR, and Power signoff.

Collaborate with architects and circuit design engineering teams to create and refine new flows and methodologies.

Ensure pre-layout and post-layout timing closure and timing model characterizations across various design corners, meeting reliability and aging requirements for automotive and consumer products.

Accelerating the integration of next-generation intelligent in-chip sensors and analytics into Synopsys technology products.

Optimizing performance, power, area, schedule, and yield at every stage of the semiconductor lifecycle.

Enhancing product reliability and differentiation in the market, reducing risk for customers and partners.

Driving innovation in physical design, verification, STA, and signoff methodologies and tools.

Contributing to industry-leading SLM monitors and silicon biometrics solutions that set new standards.

Collaborating with cross-functional teams to ensure successful deployment and adoption of advanced technologies.

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Responsibilities:

• Design top-level layout with advanced process nodes.
• Provide solutions for difficult ESD/latch-up/ANT issues in layout.
• Stick to workflow and deliver database with high quality.
• Take part in analog layout and design communication, detecting problems.
• Discuss and exchange skill sets with global designers.

Requirements:

• Bachelor's degree or above.
• Major in Microelectronics, Electronic Engineering, or Electronic-related fields.
• Mastering in using EDA tool for layout drawing.
• Proficient in top-level floorplan and connection.
• Adept at ESD/latch-up and solve related problems.
• Use English to communicate with layout designers from global sites.

Preferred experience:

• 3+ years of experience in layout design.
• Knowledge of advanced nodes.
• SoC level experience is prior.

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You will operate across architecture, circuits, memory, RTL, physical implementation, and integration technologies to turn ambitious product goals into manufacturable silicon. This role is not limited to analysis or pathfinding,you will be expected to develop solutions, prototype ideas, drive execution, and close critical gaps.

The ideal candidate is a hands-on generalist with strong engineering judgment, deep circuit intuition, broad semiconductor knowledge, and a habit of using AI tools to move faster and make better decisions.

Key responsibilities include: Partner with architecture and system teams to translate product goals into executable silicon construction strategies. Drive hands-on optimization of power, performance, area, cost, and reliability across the silicon stack. Develop and implement solutions spanning circuits, memory, RTL, physical design, and integration. Use and build AI-driven tools, flows, and methodologies to accelerate silicon implementation. Evaluate new technologies and convert them into reliable product constructions optimized for performance, performance/TCO, and performance/W.

Requirements include: BS with 12+ years, MS with 10+ years, or PhD with 6+ years of relevant industry experience in chip design or implementation. Strong hands-on expertise in circuits and implementation-driven PPA optimization. Deep knowledge of semiconductor technologies including memory, advanced nodes, packaging, and 3D integration. Hands-on experience with RTL design and physical implementation through tapeout. Proven ability to work across disciplines and solve complex technical problems end-to-end. Strong use of AI tools for engineering productivity, analysis, coding, or design optimization. Excellent technical communication and collaboration skills.

Preferred qualifications include: Strong first-principles understanding of AI chip architectures and training/inference workloads. Experience improving silicon products through innovations in performance, power, cost, yield, or reliability. Experience with HBM, SRAM, memory hierarchy design, or memory-centric optimization. Experience building internal tools, models, or automation used by engineering teams. Research lab experience and/or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.

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What you'll do

Responsible for the development and implementation of System Design Solutions using Synopsys EDA tools and IP to solve customer problems as part of a service project team. Contributes to both turnkey projects and as a trusted advisor to customer design. Develop innovative solutions to problems with little guidance and implement them independently. Set task-level goals and consistently meet schedules. Works with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tool and IP solutions.

• Synthesis
• LEC
• LDRC
• GCA
• STA
• PTPX

What you need

• 2 - 4 years of related experience.
• Good of ASIC/SOC design, synthesis, timing closure.
• Familiar with Synthesis, LEC, STA flow.
• It’s a plus if you have experience in low-power, high-performance design, advanced nodes under 12nm.
• Knowledge of RTL, DFT, LDRC, GCA, VCLP, PTPX, IREM is advantageous.
• Familiar with scripting languages, such as TCL, Perl, Python.
• Good English/communication skills and willingness to work with customer.
• BS or MS with an EE or related major

XML job scraping automation by YubHub

What you'll do

Responsible for the development and implementation of System Design Solutions using Synopsys EDA tools and IP to solve customer problems as part of a service project team. Contributes to both turnkey projects and as a trusted advisor to customer design. Develop innovative solutions to problems with little guidance and implement them independently. Set task-level goals and consistently meet schedules. Works with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tool and IP solutions.

• Synthesis
• LEC
• LDRC
• GCA
• STA
• PTPX

What you need

• 6-12 years of related experience.
• Good of ASIC/SOC design, synthesis, timing closure.
• Familiar with Synthesis, LEC, STA flow.
• It’s a plus if you have experience in low-power, high-performance design, advanced nodes under 12nm.
• Knowledge of RTL, DFT, LDRC, GCA, VCLP, PTPX, IREM is advantageous.
• Familiar with scripting languages, such as TCL, Perl, Python.
• Good English/communication skills and willingness to work with customer.
• BS or MS with an EE or related major

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