{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/adaptation"},"x-facet":{"type":"skill","slug":"adaptation","display":"Adaptation","count":4},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_32c9fdc1-fd4"},"title":"Analog Design, Sr Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>We are seeking an expert analog design engineer with a passion for high-speed integrated circuits and a drive to push the boundaries of SERDES technology. As a Sr Staff Engineer, you will lead the design and development of high-performance analog and mixed-signal solutions in advanced process nodes.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Reviewing SERDES standards to develop innovative transceiver architectures and sub-block specifications for Multi-Gbps NRZ &amp; PAM4 SERDES IP.</li>\n<li>Investigating and architecting advanced circuit solutions to overcome bottlenecks, achieving breakthroughs in power efficiency, area reduction, and performance.</li>\n<li>Collaborating with cross-functional teams, including analog, digital, and layout engineers,to optimize design and verification strategies for superior quality and project efficiency.</li>\n<li>Presenting and critically reviewing simulation data within project teams and at external industry panels or customer meetings.</li>\n<li>Overseeing physical layout to minimize parasitics, device stress, and process variations, ensuring robust manufacturability and reliability.</li>\n<li>Documenting design features, creating comprehensive test plans, and ensuring traceability throughout the development lifecycle.</li>\n<li>Consulting on electrical characterization of SERDES IP, analyzing customer silicon data, and proposing enhancements or post-silicon updates as needed.</li>\n</ul>\n<p>Impact:</p>\n<ul>\n<li>Driving the next generation of high-speed data communication through pioneering SERDES architectures.</li>\n<li>Enabling Synopsys customers to achieve industry-leading performance, power efficiency, and reliability in their products.</li>\n<li>Fostering a culture of technical excellence and innovation within a diverse, high-caliber design team.</li>\n<li>Accelerating project timelines by streamlining design and verification methodologies.</li>\n<li>Enhancing the overall quality and competitiveness of Synopsys IP offerings through expert problem-solving and continuous improvement.</li>\n<li>Mentoring and developing junior engineers, strengthening the team&#39;s collective expertise and future leadership pipeline.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Ph.D. with 6+ years, or M.Sc. with 8+ years of practical analog IC design experience, preferably in Electrical Engineering, Computer Engineering, or a related field.</li>\n<li>Deep expertise in transistor-level circuit design and sound CMOS fundamentals.</li>\n<li>Hands-on design experience with one or more SERDES sub-circuits (e.g., receive equalizers, samplers, drivers, serializers/deserializers, voltage-controlled oscillators, PLLs, bandgap references, ADCs, DACs).</li>\n<li>Proficiency with schematic entry, physical layout, and design verification tools; familiarity with SPICE simulators and simulation methodologies.</li>\n<li>Experience with analog/digital co-design for performance optimization, including calibration, adaptation, and timing handoff.</li>\n<li>Knowledge of reliability and layout effects (EM, IR, aging, matching, proximity, ESD, etc.).</li>\n<li>Proficiency in Verilog-A for analog behavioral modeling, and experience with scripting languages such as TCL, Perl, C, Python, or MATLAB.</li>\n<li>Excellent communication, presentation, and documentation skills.</li>\n</ul>\n<p>Team:</p>\n<ul>\n<li>You will join a dynamic, growing analog and mixed-signal design team focused on developing cutting-edge Multi-Gbps SERDES IP.</li>\n<li>The team is composed of passionate engineers from diverse backgrounds, collaborating closely with digital designers, layout specialists, and software/CAD experts.</li>\n<li>Our culture emphasizes technical excellence, innovation, and continuous learning.</li>\n<li>With access to best-in-class design tools and in-house support, this team thrives on solving industry-defining challenges and delivering world-class IP to Synopsys&#39; global customers.</li>\n</ul>\n<p>Rewards and Benefits:</p>\n<ul>\n<li>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</li>\n<li>Our total rewards include both monetary and non-monetary offerings.</li>\n<li>Your recruiter will provide more details about the salary range and benefits during the hiring process.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_32c9fdc1-fd4","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ottawa/analog-design-sr-staff-engineer/44408/94257665728?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"Competitive salary and benefits package","x-skills-required":["Analog IC design","CMOS fundamentals","SERDES technology","Transistor-level circuit design","Schematic entry","Physical layout","Design verification tools","SPICE simulators","Simulation methodologies","Analog/digital co-design","Calibration","Adaptation","Timing handoff","Reliability and layout effects","Verilog-A","Scripting languages","Communication","Presentation","Documentation"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:16:08.755Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ottawa"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Analog IC design, CMOS fundamentals, SERDES technology, Transistor-level circuit design, Schematic entry, Physical layout, Design verification tools, SPICE simulators, Simulation methodologies, Analog/digital co-design, Calibration, Adaptation, Timing handoff, Reliability and layout effects, Verilog-A, Scripting languages, Communication, Presentation, Documentation"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5f4e85a9-296"},"title":"Staff Analog Design Engineer","description":"<p><strong>Overview</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>15391</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>02/23/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a seasoned analog design professional with a passion for pushing technology boundaries. With over a decade of hands-on experience in analog IC design, you thrive in fast-paced, collaborative environments and are motivated by technical challenges. Your expertise in Multi-Gbps NRZ &amp; PAM4 SERDES IP and familiarity with the latest FinFET and gate-all-around process nodes set you apart as a leader in the field. You are adept at translating complex SerDes standards into innovative, high-performance circuit architectures and are comfortable navigating the intricacies of transistor-level design, system-level budgeting, and analog/digital co-design.</p>\n<p>You excel at mentoring peers, sharing knowledge, and advocating for design excellence. Your strong analytical skills allow you to quickly identify architectural bottlenecks and propose effective solutions. You are detail-oriented, balancing deep technical focus with a strategic view of project goals and timelines. Communication is one of your strengths—whether presenting simulation data, documenting design features, or collaborating across multidisciplinary teams, you articulate complex ideas clearly to both technical and non-technical audiences.</p>\n<p>Beyond your technical expertise, you are committed to continuous learning and growth, staying abreast of industry trends and emerging technologies. You value diversity and inclusion, recognizing that great ideas come from a variety of perspectives. Your proactive and adaptable approach ensures you thrive in dynamic, innovative environments where your contributions drive meaningful impact.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Reviewing SerDes standards to develop novel transceiver architectures and detailed sub-block specifications.</li>\n</ul>\n<ul>\n<li>Investigating and architecting circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed.</li>\n</ul>\n<ul>\n<li>Collaborating with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality.</li>\n</ul>\n<ul>\n<li>Overseeing and guiding the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance.</li>\n</ul>\n<ul>\n<li>Presenting and reviewing simulation data with internal teams and external stakeholders, including industry panels and customer reviews.</li>\n</ul>\n<ul>\n<li>Documenting design features, test plans, and results, and consulting on electrical characterization and post-silicon analysis for product enhancements.</li>\n</ul>\n<ul>\n<li>Analyzing customer silicon data to identify design improvement opportunities and proposing solutions for post-silicon updates.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Drive innovation in high-speed analog/mixed-signal design, enabling next-generation connectivity solutions.</li>\n</ul>\n<ul>\n<li>Shape the architectural direction of SERDES IP, influencing industry standards and future product offerings.</li>\n</ul>\n<ul>\n<li>Enhance the performance, power efficiency, and reliability of Synopsys’ silicon IP portfolio.</li>\n</ul>\n<ul>\n<li>Mentor and elevate the technical capabilities of team members, fostering a culture of excellence and continuous learning.</li>\n</ul>\n<ul>\n<li>Directly contribute to successful customer deployments by addressing post-silicon challenges and ensuring robust field performance.</li>\n</ul>\n<ul>\n<li>Strengthen Synopsys’ market leadership in advanced process nodes and high-speed communication technologies.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>MTech/MS with 4+ years or BTech/BS with 5+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field).</li>\n</ul>\n<ul>\n<li>Proven expertise with FinFET technologies and CMOS tape-outs.</li>\n</ul>\n<ul>\n<li>Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures.</li>\n</ul>\n<ul>\n<li>Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC).</li>\n</ul>\n<ul>\n<li>Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance.</li>\n</ul>\n<ul>\n<li>Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating).</li>\n</ul>\n<ul>\n<li>Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators.</li>\n</ul>\n<ul>\n<li>Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results.</li>\n</ul>\n<ul>\n<li>Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk).</li>\n</ul>\n<ul>\n<li>Excellent communication and documentation skills.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Collaborative and open-minded, eager to share knowledge and learn from others.</li>\n</ul>\n<ul>\n<li>Detail-oriented and thorough, with a commitment to delivering high-quality results.</li>\n</ul>\n<ul>\n<li>Analytical thinker with strong problem-solving abilities and a proactive approach.</li>\n</ul>\n<ul>\n<li>Excellent communicator, able to convey complex technical concepts clearly.</li>\n</ul>\n<ul>\n<li>Adaptable and resilient in fast-paced, dynamic environments.</li>\n</ul>\n<ul>\n<li>Committed to fostering an inclusive, innovative, and supportive workplace.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You’ll join a world-class analog and mixed-signal R&amp;D team at Synopsys, working alongside experts in high-speed IC design, verification, and CAD tool development. The team is collaborative, diverse, and passionate about innovation, with a focus on developing cutting-edge SERDES IP for advanced process nodes. You’ll have access to best-in-class design tools, mentorship, and opportunities for professional growth as you help shape the future of connectivity technology.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>What is it like to be an Analog Design Engineer at Synopsys?</p>\n<p>Arman Shahmuradyan</p>\n<p>Analog Design, Manager</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and patern</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_5f4e85a9-296","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/staff-analog-design-engineer/44408/92076328848?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["analog IC design","FinFET technologies","CMOS tape-outs","Multi-Gbps high-speed designs","SERDES architectures","analog/digital co-design","calibration","adaptation","timing handoff","ESD protection","custom digital design","design for reliability","schematic entry","physical layout","design verification tools","SPICE simulators","scripting languages","system-level budgeting","signal integrity"],"x-skills-preferred":[],"datePosted":"2026-03-09T11:05:32.632Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad, Telangana, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"analog IC design, FinFET technologies, CMOS tape-outs, Multi-Gbps high-speed designs, SERDES architectures, analog/digital co-design, calibration, adaptation, timing handoff, ESD protection, custom digital design, design for reliability, schematic entry, physical layout, design verification tools, SPICE simulators, scripting languages, system-level budgeting, signal integrity"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_8ae6102f-700"},"title":"GRC Automation Engineering Lead","description":"<p><strong>About the Role</strong></p>\n<p>We are seeking a GRC Automation Lead to join our GRC organisation and build the technical foundation for how we scale our risk and compliance programs. In this role, you will lead the team that designs and implements automated workflows, data pipelines, and integrations that transform manual compliance processes into scalable engineering systems.</p>\n<p>This is a greenfield opportunity to establish the team, architecture, and integrations that will define how we approach governance, risk, and compliance at Anthropic. The core challenge is a data problem: compliance information lives across dozens of systems—cloud infrastructure, identity providers, HR platforms, ticketing tools, code repositories—and your job is to design systems that bring it together, normalise it, and make it actionable.</p>\n<p>At Anthropic, you&#39;ll also have a unique advantage: the ability to design AI-powered workflows where Claude acts as an extension of your team, handling tasks that would traditionally require additional headcount or manual effort. You&#39;ll need ingenuity to identify where agentic AI can accelerate evidence collection, interpret unstructured data, triage compliance gaps, and augment human judgment in risk assessments.</p>\n<p>Working closely with Security, IT, and Engineering teams, you&#39;ll translate compliance and regulatory requirements into solutions that support audit programs including SOC 2, ISO, HIPAA, and FedRAMP, building systems that combine traditional automation with AI capabilities to achieve scale that wouldn&#39;t otherwise be possible.</p>\n<p><strong>Responsibilities:</strong></p>\n<ul>\n<li>Lead the team that establishes foundational GRC processes and architecture. Design and build automated workflows for risk management and compliance, creating scalable systems that enable continuous monitoring as Anthropic grows.</li>\n</ul>\n<ul>\n<li>Build data pipelines that aggregate risk, control, and asset information from across our technology stack. This means solving hard data integration problems: mapping disparate schemas, handling inconsistent data quality, and creating unified views of compliance posture through dashboards and reporting tools.</li>\n</ul>\n<ul>\n<li>Inform GRC platform strategy and implementation: in partnership with other programs, evaluate, select, and deploy tooling that meets our compliance requirements.</li>\n</ul>\n<ul>\n<li>Translate written policies and compliance requirements into policy-as-code—working with Engineering and Security teams to express requirements as enforceable rules, automated checks, and continuous validation rather than static documents.</li>\n</ul>\n<ul>\n<li>Establish feedback loops between policy and implementation: surface where technical controls diverge from written requirements, identify where policies need to evolve based on infrastructure realities, and ensure that compliance requirements are expressed in terms engineers can act on.</li>\n</ul>\n<ul>\n<li>Design and deploy agentic AI workflows that extend team capacity, using Claude to automate evidence analysis, monitor control effectiveness, draft audit responses, interpret policy documents, and handle other tasks that require reasoning over unstructured information.</li>\n</ul>\n<ul>\n<li>Design and maintain integrations connecting GRC tooling with cloud infrastructure, identity management systems, HRIS platforms, ticketing systems, version control, and CI/CD pipelines—working with engineers to implement integrations that enable automated evidence collection and continuous compliance validation.</li>\n</ul>\n<ul>\n<li>Build and lead the GRC Automation function as we scale: hiring team members, establishing practices, and defining the technical roadmap for governance and compliance automation at Anthropic.</li>\n</ul>\n<p><strong>You may be a good fit if you:</strong></p>\n<ul>\n<li>Have 3-4+ years of experience managing technical individual contributors or systems-focused teams, with a proven track record of building or scaling small teams (2-5 people) in security, compliance, automation, or operations functions.</li>\n</ul>\n<ul>\n<li>Are a systems thinker first. You understand how complex environments work: how data flows between systems, where integration points exist, what breaks when systems don&#39;t talk to each other. Your strength is designing the right architecture and environment for security monitoring, not necessarily implementing it yourself.</li>\n</ul>\n<ul>\n<li>Have 5+ years of experience designing automated workflows, data pipelines, or system integrations, whether through traditional development, low-code platforms, GRC tools, or process automation. We care about your ability to solve integration problems, not your programming language proficiency.</li>\n</ul>\n<ul>\n<li>Proficiency to write production level code in at least one programming language (e.g., Python, Rust, Go)</li>\n</ul>\n<ul>\n<li>Have a relentless focus on data integration: you understand how to pull data from multiple sources, normalise it, join it meaningfully, and surface insights. You&#39;re comfortable reasoning about messy, inconsistent data and designing systems that handle edge cases gracefully.</li>\n</ul>\n<ul>\n<li>Understand APIs and integration patterns conceptually: REST APIs, webhooks, authentication flows, polling vs. push architectures, and can evaluate systems based on how well they expose data and support automation, even if you&#39;re not writing the integration code yourself.</li>\n</ul>\n<ul>\n<li>Can work independently with minimal guidance, taking ownership of complex problems from design through implementation while managing ambiguity inherent in early-stage programs.</li>\n</ul>\n<ul>\n<li>Have strong analytical and problem-solving skills, with the ability to break down complex problems into manageable parts and develop creative solutions.</li>\n</ul>\n<ul>\n<li>Are able to communicate complex technical ideas to both technical and non-technical stakeholders, with a strong focus on collaboration and teamwork.</li>\n</ul>\n<ul>\n<li>Are passionate about staying up-to-date with industry trends and emerging technologies, with a willingness to learn and adapt to new tools and techniques.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_8ae6102f-700","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Anthropic","sameAs":"https://job-boards.greenhouse.io","logo":"https://logos.yubhub.co/anthropic.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/anthropic/jobs/4980335008?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["GRC","Automation","Data Pipelines","System Integrations","APIs","Integration Patterns","REST APIs","Webhooks","Authentication Flows","Polling vs. Push Architectures","Data Integration","Data Normalisation","Data Joining","Data Modelling","Data Analysis","Data Visualisation","Agile Methodologies","Scrum","Kanban","Continuous Integration","Continuous Deployment","Continuous Monitoring","Cloud Infrastructure","Identity Providers","HR Platforms","Ticketing Tools","Code Repositories","Version Control","CI/CD Pipelines","GRC Tools","Policy-as-Code","Automated Checks","Continuous Validation","Feedback Loops","Policy Implementation","Technical Controls","Policy Evolution","Infrastructure Realities","Compliance Requirements","Engineer Communication","Technical Ideas","Collaboration","Teamwork","Industry Trends","Emerging Technologies","Learning","Adaptation","New Tools","New Techniques"],"x-skills-preferred":["Python","Rust","Go","Java","C++","JavaScript","TypeScript","SQL","NoSQL","Cloud Computing","DevOps","Security","Compliance","Risk Management","Audit Programs","SOC 2","ISO","HIPAA","FedRAMP","GRC Platforms","GRC Tools","Policy Management","Compliance Management","Risk Management","Audit Management","Compliance Automation","GRC Automation","Policy Automation","Compliance Orchestration","Risk Orchestration","Audit Orchestration","Compliance Intelligence","Risk Intelligence","Audit Intelligence","Compliance Analytics","Risk Analytics","Audit Analytics","Compliance Reporting","Risk Reporting","Audit Reporting","Compliance Dashboarding","Risk Dashboarding","Audit Dashboarding"],"datePosted":"2026-03-08T13:43:53.373Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco, CA | New York City, NY | Seattle, WA"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"GRC, Automation, Data Pipelines, System Integrations, APIs, Integration Patterns, REST APIs, Webhooks, Authentication Flows, Polling vs. Push Architectures, Data Integration, Data Normalisation, Data Joining, Data Modelling, Data Analysis, Data Visualisation, Agile Methodologies, Scrum, Kanban, Continuous Integration, Continuous Deployment, Continuous Monitoring, Cloud Infrastructure, Identity Providers, HR Platforms, Ticketing Tools, Code Repositories, Version Control, CI/CD Pipelines, GRC Tools, Policy-as-Code, Automated Checks, Continuous Validation, Feedback Loops, Policy Implementation, Technical Controls, Policy Evolution, Infrastructure Realities, Compliance Requirements, Engineer Communication, Technical Ideas, Collaboration, Teamwork, Industry Trends, Emerging Technologies, Learning, Adaptation, New Tools, New Techniques, Python, Rust, Go, Java, C++, JavaScript, TypeScript, SQL, NoSQL, Cloud Computing, DevOps, Security, Compliance, Risk Management, Audit Programs, SOC 2, ISO, HIPAA, FedRAMP, GRC Platforms, GRC Tools, Policy Management, Compliance Management, Risk Management, Audit Management, Compliance Automation, GRC Automation, Policy Automation, Compliance Orchestration, Risk Orchestration, Audit Orchestration, Compliance Intelligence, Risk Intelligence, Audit Intelligence, Compliance Analytics, Risk Analytics, Audit Analytics, Compliance Reporting, Risk Reporting, Audit Reporting, Compliance Dashboarding, Risk Dashboarding, Audit Dashboarding"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_83f45538-d2c"},"title":"Analog Design, Sr Staff Engineer","description":"<p>Opening. This role is responsible for driving innovation in high-speed analog/mixed-signal design, enabling next-generation connectivity solutions. The successful candidate will be a seasoned analog design professional with a passion for pushing technology boundaries.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Review SerDes standards to develop novel transceiver architectures and detailed sub-block specifications.</p>\n<p>Investigate and architect circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed.</p>\n<p>Collaborate with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality.</p>\n<p>Oversee and guide the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance.</p>\n<p>Present and review simulation data with internal teams and external stakeholders, including industry panels and customer reviews.</p>\n<p>Document design features, test plans, and results, and consult on electrical characterization and post-silicon analysis for product enhancements.</p>\n<p>Analyze customer silicon data to identify design improvement opportunities and propose solutions for post-silicon updates.</p>\n<p><strong>What you need</strong></p>\n<p>MTech/MS with 7+ years or BTech/BS with 8+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field).</p>\n<p>Proven expertise with FinFET technologies and CMOS tape-outs.</p>\n<p>Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures.</p>\n<p>Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC).</p>\n<p>Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance.</p>\n<p>Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating).</p>\n<p>Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators.</p>\n<p>Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results.</p>\n<p>Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk).</p>\n<p>Excellent communication and documentation skills.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_83f45538-d2c","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/analog-design-sr-staff-engineer/44408/91089467936?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["analog IC design","FinFET technologies","CMOS tape-outs","Multi-Gbps high-speed designs","SERDES architectures","SERDES sub-circuits","analog/digital co-design","calibration","adaptation","timing handoff","ESD protection","custom digital design","design for reliability"],"x-skills-preferred":["scripting languages","schematic entry","physical layout","design verification tools","SPICE simulators"],"datePosted":"2026-01-28T15:10:19.833Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"analog IC design, FinFET technologies, CMOS tape-outs, Multi-Gbps high-speed designs, SERDES architectures, SERDES sub-circuits, analog/digital co-design, calibration, adaptation, timing handoff, ESD protection, custom digital design, design for reliability, scripting languages, schematic entry, physical layout, design verification tools, SPICE simulators"}]}