These engineers play a crucial role in advancing technology and enabling innovations in various industries.

We are hiring a Staff Engineer to lead the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.

As a Staff Engineer, you will be responsible for leading the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies. You will work on hands-on execution of layout development, ensuring precision and adherence to industry standards.

You will also mentor and support junior engineers, fostering technical growth and knowledge sharing within the team.

Estimating project efforts, planning schedules, and executing projects in cross-functional settings will be another key responsibility.

Collaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks will also be a part of your role.

Managing the release process, ensuring timely delivery and consistent quality of layout deliverables will be your additional responsibility.

Key Responsibilities:

• Lead the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.

• Hands-on execution of layout development, ensuring precision and adherence to industry standards.

• Mentor and support junior engineers, fostering technical growth and knowledge sharing within the team.

• Estimating project efforts, planning schedules, and executing projects in cross-functional settings.

• Collaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks.

• Managing the release process, ensuring timely delivery and consistent quality of layout deliverables.

Requirements:

• BTech/MTech degree in Electrical Engineering, Electronics, or related field.

• 5+ years of relevant experience in layout design for CMOS, FinFET, GAA process technologies (7nm and below).

• Expertise in layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements.

• Strong understanding of floorplan techniques and deep submicron effects.

• Proven ability to lead projects and deliver best product quality within tight timelines.

Preferred Qualifications:

• Collaborative and team-oriented, with a commitment to inclusion and diversity.

• Detail-oriented, with strong problem-solving and analytical skills.

• Effective communicator, both written and verbal, with excellent interpersonal abilities.

• Adaptable and eager to learn, embracing new technologies and methodologies.

• Empathetic mentor, fostering accountability, ownership, and technical growth in others.

Benefits:

• Comprehensive medical and healthcare plans that work for you and your family.

• In addition to company holidays, we have ETO and FTO Programs.

• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• Save for your future with our retirement plans that vary by region and country.

• Competitive salaries.

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What you'll do

• Developing and maintaining SerDes system models for NRZ and PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.
• Running comprehensive system simulations to verify and sign-off design performance across multiple protocols and channels.

What you need

• M.Sc. or Ph.D. in Electrical or Computer Engineering.
• Strong experience modeling circuits and systems in MATLAB/Simulink.
• Expertise in designing high-speed analog CMOS circuits.
• Solid understanding of DSP and communications theory, including equalization, coding, and noise/crosstalk filtering.
• Proficiency in analyzing link budgets for NRZ and/or PAM4 high-speed serial links.
• Familiarity with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).
• Experience with circuit topologies used in high-speed SerDes Tx/Rx and Tx/Rx equalization techniques.
• Hands-on lab testing for high-speed serial links and proficiency in C/Verilog-A/systemVerilog.

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