Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
\nThese engineers play a crucial role in advancing technology and enabling innovations in various industries.
\nWe are hiring a Staff Engineer to lead the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.
\nAs a Staff Engineer, you will be responsible for leading the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies. You will work on hands-on execution of layout development, ensuring precision and adherence to industry standards.
\nYou will also mentor and support junior engineers, fostering technical growth and knowledge sharing within the team.
\nEstimating project efforts, planning schedules, and executing projects in cross-functional settings will be another key responsibility.
\nCollaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks will also be a part of your role.
\nManaging the release process, ensuring timely delivery and consistent quality of layout deliverables will be your additional responsibility.
\nKey Responsibilities:
\nLead the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.
\nHands-on execution of layout development, ensuring precision and adherence to industry standards.
\nMentor and support junior engineers, fostering technical growth and knowledge sharing within the team.
\nEstimating project efforts, planning schedules, and executing projects in cross-functional settings.
\nCollaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks.
\nManaging the release process, ensuring timely delivery and consistent quality of layout deliverables.
\nRequirements:
\nBTech/MTech degree in Electrical Engineering, Electronics, or related field.
\n5+ years of relevant experience in layout design for CMOS, FinFET, GAA process technologies (7nm and below).
\nExpertise in layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements.
\nStrong understanding of floorplan techniques and deep submicron effects.
\nProven ability to lead projects and deliver best product quality within tight timelines.
\nPreferred Qualifications:
\nCollaborative and team-oriented, with a commitment to inclusion and diversity.
\nDetail-oriented, with strong problem-solving and analytical skills.
\nEffective communicator, both written and verbal, with excellent interpersonal abilities.
\nAdaptable and eager to learn, embracing new technologies and methodologies.
\nEmpathetic mentor, fostering accountability, ownership, and technical growth in others.
\nBenefits:
\nComprehensive medical and healthcare plans that work for you and your family.
\nIn addition to company holidays, we have ETO and FTO Programs.
\nMaternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
\nPurchase Synopsys common stock at a 15% discount, with a 24 month look-back.
\nSave for your future with our retirement plans that vary by region and country.
\nCompetitive salaries.
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