Senior FPGA Engineer, Space · Anduril

Sat, 25 Apr 2026 15:07:03 GMT
Engineering

Anduril · Costa Mesa, California, United States · $191,000-$253,000 USD · onsite

We are looking for a Sr. FPGA/SoC Engineer to join our rapidly growing team in Costa Mesa, CA. In this role, you will be responsible for developing FPGA/SoC firmware and overseeing 3rd party development. You will work with internal and external design teams to develop products for use in orbit. This will require architecture, RTL generation and debug.

Your responsibilities will include:

Rapidly develop, test, and implement FPGA designs using Xilinx SoC/FPGA.

Integrate third-party vendors IP, as necessary.

Work with third-party developers to ensure timely product success

Perform digital circuit design, VHDL/Verilog coding, synthesis, place and route, timing closure, simulation, and verification.

Participate in entire design life cycle: from requirements and concept, through design and hand on testing/board bring up.

Implement a variety of signal types such as high speed comms (ethernet, serial), signal processing (analog, digital).

Ensure designs meet all relevant safety and performance standards, with traceability back to top-level system requirements, as necessary.

Investigate and resolve bugs found during hand on testing (at HDL level and system level).

Required qualifications include:

5 years of experience preferred in FPGA/HDL hardware design. Experience with Xilinx SoC (Versal) is highly preferred.

Familiarity with design software like Vivado (preferred), ModelSim, or Quartus.

Proficient in VHDL and/or Verilog.

Ability to work in a fast-paced, challenging environment.

Excellent problem-solving and organizational skills.

Strong communication and teamwork skills.

Experience in SoC hardware bring-up, preferably on ARM-based systems.

Eligible to obtain and maintain an active U.S. Secret security clearance.

Preferred qualifications include:

Working knowledge of designing for safety-critical functions.

FPGA interfaces and high speed busses.

Experience with systems on a Chip (SoC).

Low-level firmware (C/C++) development for bring-up and test.

Experience writing HDL for Space applications.