{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/city/yerevan"},"x-facet":{"type":"city","slug":"yerevan","display":"Yerevan","count":14},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. 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We push technological boundaries and ensure high standards of quality and performance, fostering an inclusive and supportive work environment.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Work on the backend ASIC design flow, from netlist to GDSII, as well as the physical verification of standard cell libraries.</li>\n<li>Analyze and debug physical verification results.</li>\n<li>Collaborate with cross-functional teams to support design and verification activities.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>Currently studying in the 3rd or final year of Electronics Engineering, Telecommunications, Automation &amp; Control, Computer Science, or a related field.</li>\n<li>Good knowledge of UNIX/Linux operating systems.</li>\n<li>Basic understanding of Shell and TCL scripting for process automation and day-to-day tasks.</li>\n<li>Basic knowledge of VLSI technology; familiarity with standard cell libraries and PDKs would be a plus.</li>\n<li>Good English communication skills.</li>\n<li>Strong self-learning, research, and presentation skills.</li>\n<li>Accountable, patient, and motivated, with a strong work ethic.</li>\n<li>Ability to learn quickly and work effectively both independently and as part of a team.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Contribute to the successful validation of standard cell libraries.</li>\n<li>Support high-quality ASIC physical design and verification activities.</li>\n<li>Explore and apply AI-enabled tools to support engineering workflows and continuous improvement.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2589a951-f3d","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/yerevan/asic-physical-design-intern/44408/102166693184?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":null,"x-job-type":"internship","x-salary-range":null,"x-skills-required":["UNIX/Linux","Shell scripting","TCL scripting","VLSI technology","English communication"],"x-skills-preferred":["standard cell libraries","PDKs"],"datePosted":"2026-10-20T10:05:20.999Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Yerevan"}},"employmentType":"INTERN","occupationalCategory":"Engineering","industry":"Technology","skills":"UNIX/Linux, Shell scripting, TCL scripting, VLSI technology, English communication, standard cell libraries, PDKs"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c24dc7f8-907"},"title":"Analog Design, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. 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You spot design risks early and know how to weigh the tradeoffs between area, power, and cost without losing sight of what makes a design robust in production.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Leading the design and development of advanced analog and mixed-signal circuits, blocks, and subsystems from concept to production</li>\n<li>Developing architecture proposals and evaluating tradeoffs for performance, power, area, and cost using real project constraints</li>\n<li>Running circuit simulation, verification, and optimization with industry-standard tools like SPICE and Spectre</li>\n<li>Owning tape-out activities, silicon bring-up, debug, and hands-on characterization in the lab</li>\n<li>Partnering with layout engineers to ensure your design intent carries through to silicon, with an eye on manufacturability and robustness</li>\n<li>Defining and executing validation plans that actually catch what matters,meeting product requirements, not just checklists</li>\n<li>Reviewing specs, schematics, and lab results, and driving design reviews that raise the technical bar</li>\n<li>Mentoring junior engineers and providing technical leadership across projects and teams</li>\n<li>Working cross-functionally with system, digital, validation, and product teams to resolve issues and keep projects moving</li>\n<li>Driving improvements in design methodologies and best practices so the next project runs smoother than the last</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>Bachelor’s degree in electrical engineering, microelectronics, Computer Engineering, or related field</li>\n<li>Minimum 2-3 years of hands-on experience in analog and/or mixed-signal IC design</li>\n<li>Deep understanding of transistor-level circuit design and analysis,you know your way around a schematic and simulation results</li>\n<li>Proficiency with simulation tools such as SPICE, Spectre, or equivalent for real-world design and debug</li>\n<li>Practical experience with silicon debug, characterization, and using lab equipment to close the loop between simulation and silicon</li>\n<li>Experience with high-speed interfaces, data converters, regulators, bandgap reference, power management, sensors, or similar analog/mixed-signal blocks is a plus</li>\n<li>Familiarity with deep submicron CMOS processes is helpful</li>\n<li>Using AI tools during circuit design and verification processes</li>\n<li>Experience with MIPI cphy/dphy (Mobile Industry Processor Interface), USB (Universal Serial Bus) and other high speed serial links are plus</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family</li>\n<li>Time away: In addition to company holidays, we have ETO and FTO Programs</li>\n<li>Family support: Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>ESPP: Purchase Synopsys common stock at a 15% discount, with a 24-month look-back</li>\n<li>Retirement plans: Save for your future with our retirement plans that vary by region and country</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c24dc7f8-907","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/yerevan/analog-design-sr-engineer/44408/101703888448?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["SPICE","Spectre","analog and mixed-signal IC design","transistor-level circuit design","silicon debug","characterization"],"x-skills-preferred":["high-speed interfaces","data converters","regulators","bandgap reference","power management","sensors","MIPI cphy/dphy","USB"],"datePosted":"2026-10-09T06:37:31.193Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Yerevan"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"SPICE, Spectre, analog and mixed-signal IC design, transistor-level circuit design, silicon debug, characterization, high-speed interfaces, data converters, regulators, bandgap reference, power management, sensors, MIPI cphy/dphy, USB"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_538d0b83-7e7"},"title":"Layout Design, Manager","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You have spent years in the physical layout trenches of SRAM development, and you know that the difference between a memory that meets PPA targets and one that requires three more spins is usually a layout decision made during floorplanning. You understand how bitcell density, array routing, and peripheral placement affect yield, performance, and power in ways that do not show up in early simulations. You have debugged enough DRC violations, LVS mismatches, and EM/IR failures to recognize patterns before they become blockers.</p>\n<p>Managing people energizes you because you want your team to have the support, clarity, and technical direction you wish you had earlier in your career. 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solutions</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>Bachelor&#39;s or master&#39;s degree in electrical engineering, Electronics, Microelectronics, or a related field</li>\n<li>7+ years of hands-on experience in SRAM memory layout development, including work on bitcells, arrays, peripheral circuits, and full memory integration</li>\n<li>Deep understanding of SRAM architecture, memory compilers, and how layout decisions affect performance, power, area, yield, and reliability</li>\n<li>Strong working knowledge of DRC, LVS, ERC, antenna checks, EM/IR analysis, parasitic extraction, and advanced-node layout constraints</li>\n<li>Demonstrated experience leading engineering teams or managing complex technical projects with multiple stakeholders and dependencies</li>\n<li>Proficiency with industry-standard custom layout tools and physical verification flows, experience with layout automation and scripting is a plus</li>\n<li>Experience with SRAM memory compiler development across multiple process technologies and advanced FinFET or GAA nodes is a plus</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_538d0b83-7e7","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/yerevan/layout-design-manager/44408/101580799488?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["SRAM memory layout development","physical design","DRC","LVS","ERC","EM/IR analysis","parasitic extraction","layout automation","scripting"],"x-skills-preferred":["SRAM memory compiler development","FinFET","GAA nodes"],"datePosted":"2026-10-07T04:19:50.150Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Yerevan"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"SRAM memory layout development, physical design, DRC, LVS, ERC, EM/IR analysis, parasitic extraction, layout automation, scripting, SRAM memory compiler development, FinFET, GAA nodes"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_f74a347a-01a"},"title":"Layout Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You have built a career in SRAM layout design, developing expertise in solving complex technical challenges at advanced process nodes where parasitic effects, density constraints, and matching requirements create significant design complexity. You understand that layout decisions made early in the design cycle have direct consequences for circuit performance, yield, and manufacturability, and you have developed the technical judgment to anticipate and address these issues systematically.</p>\n<p>You will apply this expertise to memory compiler development that serves customers across the semiconductor industry, working within a team that values technical rigor and collaborative problem-solving.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Lead physical layout development for embedded SRAM memory compiler peripheral circuits, including sense amplifiers, decoders, write drivers, and control logic across advanced technology nodes</li>\n<li>Optimize SRAM layouts to meet specifications for performance, power consumption, area efficiency, reliability, manufacturability, and yield</li>\n<li>Drive physical verification closure including DRC, LVS, ERC, antenna checks, and parasitic extraction, coordinating with CAD and verification teams to resolve technical issues</li>\n<li>Collaborate with circuit design teams to ensure layout implementations satisfy timing, matching, and electrical requirements</li>\n<li>Address advanced-node layout challenges including device matching, parasitic management, high-density routing, and reliability constraints</li>\n<li>Develop and implement layout methodology improvements and automation capabilities to enhance team productivity</li>\n<li>Provide technical guidance and mentorship to layout engineers, conducting design reviews and supporting skill development</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Your layout implementations will directly influence the performance, power, and area characteristics of SRAM compilers integrated into customer system-on-chip designs</li>\n<li>The methodologies and automation capabilities you develop will improve development efficiency and reduce time-to-market for future memory compiler releases</li>\n<li>Your technical contributions to verification closure and yield optimization will reduce risk and support program schedule adherence</li>\n<li>The technical leadership you provide will strengthen the capabilities of the layout engineering team and improve overall deliverable quality</li>\n<li>Your collaboration with circuit design and technology teams will support the successful adaptation of Synopsys memory IP to emerging process technologies</li>\n<li>Your design decisions will contribute to the competitive positioning of Synopsys memory solutions across key market segments</li>\n<li>Your work will enable reliable, high-performance embedded memory integration in applications spanning AI, automotive, mobile, and data center markets</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering, Microelectronics, or related technical discipline</li>\n<li>6+ years of professional experience in SRAM or embedded memory layout design, including bitcells, arrays, and peripheral circuits</li>\n<li>Comprehensive understanding of SRAM architecture, including bitcell operation, array organization, sense amplifier design, and decoder/driver circuits</li>\n<li>Demonstrated ability to optimize layouts across multiple design objectives including performance, power, area, reliability, and manufacturability</li>\n<li>Strong analytical and problem-solving capabilities for complex layout challenges involving device matching, parasitic extraction, and advanced-node design rules</li>\n<li>Proven experience driving physical verification closure including DRC, LVS, ERC, and antenna checks</li>\n<li>Experience with scripting or layout automation is highly valued, as is experience with technology bring-up or foundry collaboration</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family</li>\n<li>Time away: company holidays, ETO and FTO Programs</li>\n<li>Family support: maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back</li>\n<li>Retirement plans: save for your future with our retirement plans that vary by region and country</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_f74a347a-01a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/yerevan/layout-design-staff-engineer/44408/101601440480?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["SRAM layout design","circuit design","verification","physical implementation","layout automation"],"x-skills-preferred":["scripting","technology bring-up","foundry collaboration"],"datePosted":"2026-10-07T04:07:04.039Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Yerevan"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"SRAM layout design, circuit design, verification, physical implementation, layout automation, scripting, technology bring-up, foundry collaboration"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_2c72da87-eb0"},"title":"Layout Design Manager","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You have built your career in custom analog and mixed-signal layout, developing a deep understanding that successful tapeouts depend on decisions made during floorplanning, rigorous verification processes, and proactive risk management. Your expertise extends beyond technical execution to include the strategic thinking required to prevent issues before they reach critical stages in the development cycle.</p>\n<p>You have progressed from individual contributor to technical leader, establishing methodologies that ensure consistency and quality across complex projects. When your team encounters challenges with EMIR analysis or LVS verification, you provide the technical guidance necessary to resolve issues while developing their problem-solving capabilities. Your approach to execution is disciplined and data-driven. You have successfully managed multiple tapeouts, balanced competing project demands, and maintained schedule integrity through careful planning and clear communication with stakeholders at all levels. At Synopsys, you will lead the layout organization responsible for advanced SerDes and high-speed connectivity IP that defines industry standards.</p>\n<p><strong>What You&#39;ll Be Doing</strong></p>\n<ul>\n<li>Lead and manage a layout engineering team delivering custom analog/mixed-signal IC layout for PCIe Gen7/Gen8, UCIe, SerDes, PLLs, PHYs, and power management IP</li>\n<li>Direct layout execution from initial floorplanning through tapeout, including resource planning, schedule management, and risk mitigation across concurrent development programs</li>\n<li>Establish and implement advanced layout methodologies, automation frameworks, and AI-assisted design tools to enhance quality and efficiency</li>\n<li>Collaborate with analog design, digital implementation, verification, CAD, and product engineering organizations to resolve technical challenges and ensure alignment with project objectives</li>\n<li>Define and enforce layout standards for DRC, LVS, EMIR, reliability, ESD, and manufacturing compliance across advanced CMOS process technologies</li>\n<li>Build organizational capability through recruiting, mentoring, and developing layout engineers and technical leads</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Your team will deliver the physical implementation for industry-leading high-speed connectivity IP deployed in data center, AI infrastructure, and networking applications globally</li>\n<li>The methodologies and quality standards you establish will improve first-pass silicon success rates and reduce development cycle times across multiple product portfolios</li>\n<li>Your investment in team development will build technical depth and leadership capability within the organization</li>\n<li>Your execution discipline will ensure critical programs meet schedule commitments while maintaining the quality standards required for production silicon</li>\n<li>The cross-functional collaboration frameworks you implement will strengthen alignment between design, layout, CAD, and process technology teams across global development sites</li>\n</ul>\n<p><strong>What You&#39;ll Need</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering, Electronics Engineering, or equivalent professional experience</li>\n<li>10+ years of professional experience in custom analog/mixed-signal IC layout design with demonstrated expertise in advanced CMOS process technologies</li>\n<li>3+ years of experience managing and developing layout engineering teams</li>\n<li>Proven track record delivering high-speed SerDes, PLLs, PHYs, ADC/DACs, or power management circuits through multiple production tapeouts</li>\n<li>Comprehensive knowledge of DRC, LVS, EMIR, reliability, ESD, and design-for-manufacturing requirements</li>\n<li>Experience with PCIe, UCIe, or other high-speed interface standards is highly valued</li>\n</ul>\n<p><strong>Who You Are</strong></p>\n<ul>\n<li>You identify potential design-for-manufacturing issues during technical reviews and communicate the implications and mitigation strategies clearly to design teams and management</li>\n<li>You assess when direct technical intervention is required versus when coaching and resource connection will better serve both the immediate need and long-term team development</li>\n<li>You maintain sufficient technical engagement with ongoing work to accurately assess project health and risk beyond what is reflected in status reports</li>\n<li>You have established team environments where engineers proactively communicate challenges, share lessons learned, and collaborate effectively</li>\n<li>You provide data-supported recommendations when project timelines or scope changes introduce technical or schedule risk</li>\n</ul>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</li>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n<li>Competitive salaries.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2c72da87-eb0","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/yerevan/layout-design-manager/44408/101448372448?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["analog/mixed-signal IC layout design","CMOS process technologies","layout engineering team management","DRC","LVS","EMIR","reliability","ESD","design-for-manufacturing"],"x-skills-preferred":["PCIe","UCIe","high-speed interface standards"],"datePosted":"2026-10-03T03:04:58.424Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Yerevan"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"analog/mixed-signal IC layout design, CMOS process technologies, layout engineering team management, DRC, LVS, EMIR, reliability, ESD, design-for-manufacturing, PCIe, UCIe, high-speed interface standards"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_cf69b1c9-ecb"},"title":"Analog Design, Sr Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You bring extensive experience in analog and mixed-signal design, with a proven ability to deliver circuits that perform reliably across process corners, temperature variations, and real-world operating conditions. Your work extends beyond meeting specifications to ensuring robust performance in demanding applications including data centers, AI accelerators, and networking platforms.</p>\n<p>You approach design through systematic tradeoff analysis, balancing power, performance, area, yield, and time-to-market considerations. Your technical decisions are grounded in data and validated through silicon results. In design reviews, you contribute clarity and insight that advances technical discussions and resolves complex challenges.</p>\n<p>Technical mentorship is central to your professional practice. You guide engineers through circuit analysis, layout considerations, and jitter budgeting with a focus on building their independent problem-solving capabilities. Your leadership is exercised through technical expertise and collaborative influence rather than formal authority.</p>\n<p>At Synopsys, you will contribute to the development of PCIe Gen7/Gen8 and advanced SerDes architectures that enable AI and cloud computing infrastructure. You will work within a global engineering organization on high-speed connectivity solutions with direct impact on next-generation systems.</p>\n<p><strong>What You&#39;ll Be Doing</strong></p>\n<ul>\n<li>Design and deliver critical analog and mixed-signal circuit blocks including PLLs, CDRs, equalization circuits, ADCs, DACs, and clocking systems for high-speed SerDes and PHY products</li>\n<li>Conduct architecture exploration and tradeoff analysis for next-generation connectivity IP supporting PCIe Gen7/Gen8, AI, and networking applications</li>\n<li>Execute transistor-level design, simulation, and optimization with focus on performance, power consumption, jitter, and signal integrity</li>\n<li>Provide technical mentorship to engineering staff on circuit design techniques, debugging methodologies, and industry best practices</li>\n<li>Collaborate with layout, verification, digital design, and system engineering teams to ensure successful integration of mixed-signal subsystems</li>\n<li>Support silicon bring-up, characterization, and root-cause analysis in coordination with laboratory and customer engineering teams</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Your circuit innovations will enable improved data rates and power efficiency in products deployed across AI and data center applications</li>\n<li>The architectures you develop will inform Synopsys IP roadmaps and influence strategic technology decisions</li>\n<li>Your mentorship will elevate engineering capabilities and establish higher standards of technical excellence across project teams</li>\n<li>Your methodology contributions will improve simulation efficiency and increase first-pass silicon success rates</li>\n<li>The SerDes and PHY intellectual property you deliver will serve as foundational building blocks across multiple product generations</li>\n<li>Your participation in design reviews will identify critical issues early in the development cycle and reduce risk of costly design iterations</li>\n</ul>\n<p><strong>What You&#39;ll Need</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering, Electronics Engineering, or related technical discipline</li>\n<li>Minimum 10 years of professional experience in analog and mixed-signal integrated circuit design with demonstrated success delivering complex products through silicon validation</li>\n<li>Extensive expertise in the design of high-performance SerDes, PLLs, CDRs, PHYs, ADCs, DACs, equalization circuits, or clocking systems</li>\n<li>Strong technical foundation in transistor-level design, noise analysis, jitter budgeting, signal integrity, and power optimization</li>\n<li>Demonstrated capability to resolve complex circuit and system-level challenges independently and influence technical direction across organizational boundaries</li>\n<li>Experience with silicon bring-up, characterization, and debug activities is highly valued</li>\n</ul>\n<p><strong>Who You Are</strong></p>\n<ul>\n<li>You identify critical technical risks in design reviews and articulate solutions that enable team consensus and forward progress</li>\n<li>You develop engineering talent by guiding colleagues through systematic problem-solving approaches rather than providing direct solutions</li>\n<li>You exercise sound judgment regarding design iteration cycles, balancing technical optimization with program schedules and risk management</li>\n<li>You communicate technical concepts effectively to executive leadership, supported by data and clear articulation of design tradeoffs</li>\n<li>You collaborate productively across geographically distributed teams and maintain project momentum across time zones</li>\n<li>You maintain current knowledge of circuit techniques, process technologies, and industry developments in high-speed analog design</li>\n</ul>\n<p><strong>The Team You&#39;ll Be Part Of</strong></p>\n<p>You will join the engineering team responsible for developing next-generation PCIe Gen7/Gen8 and advanced connectivity solutions that enable AI, cloud, networking, and high-performance computing platforms. This global team delivers SerDes and PHY intellectual property to customers building critical infrastructure for AI training, inference, and data center operations. Your contributions will directly influence product architecture and advance the technologies that define high-speed communications.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</li>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n<li>Competitive salaries.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cf69b1c9-ecb","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/yerevan/analog-design-sr-staff-engineer/44408/101448372464?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["analog and mixed-signal design","SerDes","PLL","CDR","PHY","ADC","DAC","clocking systems","transistor-level design","noise analysis","jitter budgeting","signal integrity","power optimization"],"x-skills-preferred":["silicon bring-up","characterization","debug activities"],"datePosted":"2026-10-03T03:03:28.980Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Yerevan"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"analog and mixed-signal design, SerDes, PLL, CDR, PHY, ADC, DAC, clocking systems, transistor-level design, noise analysis, jitter budgeting, signal integrity, power optimization, silicon bring-up, characterization, debug activities"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_40e2fb67-736"},"title":"ASIC Digital Design, Sr Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You bring extensive ASIC digital design experience with a track record of delivering production RTL for complex semiconductor IP. Your expertise encompasses timing closure, power optimization, and design quality across advanced process nodes.</p>\n<p>You will:</p>\n<ul>\n<li>Design RTL modules for UCIe Controller IP from microarchitecture through synthesis-ready implementation</li>\n<li>Optimize designs to meet timing, power, and area targets across multiple process nodes</li>\n<li>Develop Python/tcl/perl automation for design generation and flow integration</li>\n<li>Collaborate with cross-functional teams to resolve timing and power challenges</li>\n<li>Contribute to design reviews and methodology development</li>\n</ul>\n<p>Your designs will enable UCIe IP deployed in high-volume HPC, automotive, and AI products. You will contribute to a solid revenue-generating product line for Synopsys. Your work will define performance characteristics for customer systems-on-chip. Your automation will improve design efficiency across the engineering team. Your expertise will influence architectural decisions for future products.</p>\n<p>Requirements:</p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering, Computer Engineering, or related field</li>\n<li>8+ years of ASIC digital design experience with RTL ownership in production silicon</li>\n<li>Expert Verilog proficiency for timing-critical designs</li>\n<li>Strong Python/Tcl/Perl scripting skills for design automation</li>\n<li>Deep knowledge of synthesis, timing analysis, and power optimization</li>\n<li>Experience with Controller IP or high-speed interfaces is preferred</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family</li>\n<li>In addition to company holidays, we have ETO and FTO Programs</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back</li>\n<li>Save for your future with our retirement plans that vary by region and country</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_40e2fb67-736","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/yerevan/asic-digital-design-sr-staff-engineer/44408/100721402192?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC digital design","RTL ownership","Verilog","Python","Tcl","Perl","synthesis","timing analysis","power optimization"],"x-skills-preferred":["Controller IP","high-speed interfaces"],"datePosted":"2026-09-16T19:04:04.913Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Yerevan"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC digital design, RTL ownership, Verilog, Python, Tcl, Perl, synthesis, timing analysis, power optimization, Controller IP, high-speed interfaces"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_87136be9-cad"},"title":"Analog Design, Staff Engineer (SerDes)","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You are the kind of engineer who can walk into a room with a whiteboard and leave with a block diagram everyone trusts to become silicon. Years spent translating performance specs into transistor-level reality have made you as comfortable with SPICE. You spot design risks early and know how to weigh the tradeoffs between area, power, and cost without losing sight of what makes a design robust in production. You thrive on technical depth and know the satisfaction of seeing your blocks come up on first silicon. You mentor because you want the team to win, not just your project. You do not wait for someone to define the validation plan,you write it, run it, and fix what you find. Collaboration with layout, digital, validation, and product teams is where you turn good design into great silicon. At Synopsys, you will find the scale, the tools, and the technical challenge to keep growing while knowing your work ships in real products.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Leading the design and development of advanced analog and mixed-signal circuits, blocks, and subsystems from concept to production</li>\n<li>Developing architecture proposals and evaluating tradeoffs for performance, power, area, and cost using real project constraints</li>\n<li>Running circuit simulation, verification, and optimization with industry-standard tools like SPICE and Spectre.</li>\n<li>Owning tape-out activities, silicon bring-up, debug, and hands-on characterization in the lab</li>\n<li>Partnering with layout engineers to ensure your design intent carries through to silicon, with an eye on manufacturability and robustness</li>\n<li>Defining and executing validation plans that actually catch what matters,meeting product requirements, not just checklists</li>\n<li>Reviewing specs, schematics, and lab results, and driving design reviews that raise the technical bar</li>\n<li>Mentoring junior engineers and providing technical leadership across projects and teams</li>\n<li>Working cross-functionally with system, digital, validation, and product teams to resolve issues and keep projects moving</li>\n<li>Driving improvements in design methodologies and best practices so the next project runs smoother than the last</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>Bachelor’s degree in electrical engineering, microelectronics, Computer Engineering, or related field (master’s or PhD preferred)</li>\n<li>Minimum 5 years of hands-on experience in analog and/or mixed-signal IC design</li>\n<li>Deep understanding of transistor-level circuit design and analysis,you know your way around a schematic and simulation results</li>\n<li>Proficiency with simulation tools such as SPICE, Spectre, or equivalent for real-world design and debug</li>\n<li>Practical experience with silicon debug, characterization, and using lab equipment to close the loop between simulation and silicon</li>\n<li>Knowledge of design methodologies for robustness, reliability, and testability,you build designs that survive manufacturing and field stress</li>\n<li>Experience with high-speed interfaces, data converters, regulators, bandgap reference, power management, sensors, or similar analog/mixed-signal blocks is a plus</li>\n<li>Familiarity with deep submicron CMOS processes is helpful</li>\n<li>Experience mentoring engineers or leading technical discussions is valued</li>\n<li>Using AI tools during circuit design and verification processes</li>\n<li>Experience with MIPI cphy/dphy (Mobile Industry Processor Interface), USB (Universal Serial Bus) and other high speed serial links are plus</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>In addition to company holidays, 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and drive execution.</li>\n<li>Lead customer engagements, technical reviews, and escalations with strategic customers, translating their needs into actionable engineering solutions.</li>\n<li>Own strategic programs from concept through deployment, including resource planning, risk management, and delivery across the organization.</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Define the technical roadmap for next-generation PCIe and SerDes technologies powering AI, data center, networking, and high-performance computing platforms.</li>\n<li>Accelerate time to market and improve product quality by championing AI-assisted design workflows and engineering automation across the organization.</li>\n<li>Build and retain top engineering talent, creating an environment where engineers work on industry-leading connectivity solutions that shape the future.</li>\n<li>Influence investment priorities and strategic decisions that position Synopsys as a leader in high-speed interface IP.</li>\n<li>Drive measurable improvements in design efficiency, silicon success rates, and customer satisfaction across multiple product lines.</li>\n<li>Establish best practices and common methodologies that scale across global teams and improve collaboration.</li>\n<li>Deliver innovations that directly improve the competitiveness and profitability of Synopsys IP offerings.</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s in Electrical Engineering, Electronics Engineering, or related field with 12+ years of analog/mixed-signal IC design experience.</li>\n<li>Proven track record managing engineering teams and delivering complex analog IP products to production, including SerDes, high-speed interfaces, or related technologies.</li>\n<li>Deep technical expertise in analog design fundamentals, high-speed signaling, PLL/CDR architectures, or power management circuits.</li>\n<li>Experience driving cross-functional initiatives across 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country.</li>\n<li>Competitive salaries.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_45af307c-9d3","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/yerevan/director-advanced-interface-technologies/44408/100672041296?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["analog and mixed-signal design","high-speed interfaces","PCIe Gen7","Gen8","SerDes","PLLs","CDRs","ADC/DAC","power management IP","AI-driven design methodologies"],"x-skills-preferred":["automation","engineering productivity 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