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skills for interacting between different design groups and customer support teams</li>\n</ul>\n<p>Preferred experience:</p>\n<ul>\n<li>RTL coding, modeling of analog blocks, and writing complex system-level test-benches in Verilog</li>\n<li>Defining synthesis design constraints and resolving STA issues as well as gate-level simulation failures</li>\n<li>Defining Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC tools</li>\n<li>Enhancing and maintaining existing SERDES PHY IPs supporting multiple protocols</li>\n<li>Interacting with Application Engineers for customer support and resolving technical issues with Analog and P&amp;R teams.</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans</li>\n<li>Time away programs, including ETO and FTO</li>\n<li>Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance</li>\n<li>ESPP, allowing purchase of Synopsys common stock at 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In this role, you will be responsible for developing test benches and verifying integrated IP Subsystems for our global customers.</p>\n<p><strong>Key Qualifications</strong></p>\n<ul>\n<li>BSEE in EE with 6+ years of relevant experience or MSEE with 3+ years of relevant experience</li>\n<li>Experience in ASIC RTL design and verification at the chip level and block level</li>\n<li>Strong Verilog, system Verilog, UVM, PERL, and TCL skills</li>\n<li>Knowledge in silicon debugging</li>\n<li>Demonstrates good communication skills in both Mandarin and English</li>\n<li>Demonstrates good analysis and problem-solving skills</li>\n<li>Knowledge of high speed interface protocols is a plus</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family</li>\n<li>In addition to company holidays, we have ETO and FTO Programs</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back</li>\n<li>Save for your future with our retirement plans that vary by region and country</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c3439b4a-78f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/wuhan/lpddr-phy-ip-verification-engineer/44408/101071131504?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC RTL design","verification","Verilog","system Verilog","UVM","PERL","TCL","silicon debugging"],"x-skills-preferred":["high speed interface protocols"],"datePosted":"2026-09-24T23:44:36.063Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Wuhan, Hubei"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC RTL design, verification, Verilog, system Verilog, UVM, PERL, TCL, silicon debugging, high speed interface protocols"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_d8aebec8-f44"},"title":"DDR/LPDDR IP Design Sr Staff Engineer","description":"<p>We are seeking a highly motivated and innovative senior engineer with wide-spectrum knowledge of generic ASIC design methodology, and simulation/silicon debug skills.</p>\n<p>The successful candidate would be working as part of a highly experienced DDR/LPDDR design and verification team, targeting the current and next generation technology. Theoretical and practical background in DDR or LPDDR is a solid plus.</p>\n<p><strong>Key Responsibilities</strong></p>\n<ul>\n<li>Work on digital design based on predefined RTL coding style including Verilog and System Verilog, clean RTL check violations in lint, CDC, DFT, and synthesis</li>\n<li>Solid debugging skills and ability to root cause issues including both simulation and silicon</li>\n<li>Good knowledge of SNPS EDA tools like VCS, Verdi, Spyglass, DC, Formality</li>\n<li>Good communication skills for interacting between different design groups and customer support teams are required</li>\n</ul>\n<p><strong>Preferred Qualifications</strong></p>\n<ul>\n<li>Strong desire to learn and explore new technologies</li>\n<li>Demonstrates good analysis and problem-solving skills</li>\n<li>Knowledge in interface technologies such as DDR, HBM, UCIe is a plus</li>\n<li>Scripting experience in Shell, Perl, Python, and TCL is a plus</li>\n<li>Knowledge of analogic circuit is a plus</li>\n<li>Interacting with Application Engineers for customer support</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family</li>\n<li>In addition to company holidays, we have ETO and FTO Programs</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back</li>\n<li>Save for your future with our retirement plans that vary by region and country</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_d8aebec8-f44","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/wuhan/ddr-lpddr-ip-design-sr-staff-engineer/44408/100326868048?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["ASIC design","RTL coding","Verilog","System Verilog","lint","CDC","DFT","synthesis","VCS","Verdi","Spyglass","DC","Formality"],"x-skills-preferred":["DDR","LPDDR","HBM","UCIe","Shell scripting","Perl scripting","Python scripting","TCL scripting","analogic circuit"],"datePosted":"2026-09-09T15:05:07.038Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Wuhan, Hubei"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC design, RTL coding, Verilog, System Verilog, lint, CDC, DFT, synthesis, VCS, Verdi, Spyglass, DC, Formality, DDR, LPDDR, HBM, UCIe, Shell scripting, Perl scripting, Python scripting, TCL scripting, analogic circuit"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_a00e9144-424"},"title":"DDR/LPDDR IP Design Principal Engineer","description":"<p>We are seeking a highly motivated and innovative senior engineer with wide-spectrum knowledge of generic ASIC design methodology, and simulation/silicon debug skills.</p>\n<p>The successful candidate will work as part of a highly experienced DDR/LPDDR design and verification team, targeting current and next-generation technology. A theoretical and practical background in DDR or LPDDR is a solid plus.</p>\n<p><strong>Key Responsibilities</strong></p>\n<ul>\n<li>Work on digital design based on predefined RTL coding style, including Verilog and System Verilog, clean RTL check violations in lint, CDC, DFT, and synthesis</li>\n<li>Solid debugging skills and ability to root cause issues, including both simulation and silicon</li>\n<li>Good knowledge of SNPS EDA tools like VCS, Verdi, Spyglass, DC, Formality</li>\n<li>Good communication skills for interacting between different design groups and customer support teams</li>\n</ul>\n<p><strong>Preferred Qualifications</strong></p>\n<ul>\n<li>Strong desire to learn and explore new technologies</li>\n<li>Demonstrates good analysis and problem-solving skills</li>\n<li>Knowledge in interface technologies such as DDR, HBM, UCIe is a plus</li>\n<li>Scripting experience in Shell, Perl, Python, and TCL is a plus</li>\n<li>Knowledge of analogic circuit is a plus</li>\n<li>Interacting with Application Engineers for customer support</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans</li>\n<li>Time away programs, including ETO and FTO</li>\n<li>Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance</li>\n<li>ESPP: purchase Synopsys common stock at a 15% discount</li>\n<li>Retirement plans that vary by region and country</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_a00e9144-424","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/wuhan/ddr-lpddr-ip-design-principal-engineer/44408/100326868032?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC design","RTL coding","Verilog","System Verilog","lint","CDC","DFT","synthesis","VCS","Verdi","Spyglass","DC","Formality"],"x-skills-preferred":["DDR","LPDDR","HBM","UCIe","Shell scripting","Perl scripting","Python scripting","TCL scripting","analogic circuit"],"datePosted":"2026-09-08T14:05:17.768Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Wuhan, Hubei"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC design, RTL coding, Verilog, System Verilog, lint, CDC, DFT, synthesis, VCS, Verdi, Spyglass, DC, Formality, DDR, LPDDR, HBM, UCIe, Shell scripting, Perl scripting, Python scripting, TCL scripting, analogic circuit"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_4251c883-eb0"},"title":"Electronic Systems Engineer - Software","description":"<p>We are seeking an entry-level Electronic Systems Engineer - Software to join our team at Cummins Inc. in Wuhan, China. As an integral part of our Engineering organisation, you will create software that is sold as part of our products. This role involves understanding stakeholder requirements, developing specifications, designing, implementing, testing, and releasing software that controls our products in various customer applications.</p>\n<p><strong>Key Responsibilities:</strong></p>\n<p>You will investigate product software problems, understand causal mechanisms, recommend actions, and document results. You will apply and support the improvement of product software development processes and tools, including coding, compiling, testing, and hardware-in-the-loop test tools. Collaboration with product and software development teams is crucial to deliver verified software features, components, and builds. Your systems knowledge and expertise will help make informed decisions on software requirements, architecture, design, and testing that impact software quality and performance.</p>\n<p>You will be responsible for:</p>\n<ul>\n<li>Investigating and resolving moderately complex software issues</li>\n</ul>\n<ul>\n<li>Collaborating with cross-functional teams to deliver high-quality software features</li>\n</ul>\n<ul>\n<li>Using systems knowledge to make informed decisions on software requirements and architecture</li>\n</ul>\n<ul>\n<li>Applying industry best practices and robust software engineering principles</li>\n</ul>\n<ul>\n<li>Developing and executing verification and validation plans</li>\n</ul>\n<ul>\n<li>Communicating effectively with various stakeholders</li>\n</ul>\n<p><strong>Competencies:</strong></p>\n<ul>\n<li>Product Failure Mode Avoidance</li>\n</ul>\n<ul>\n<li>Product Function Modeling, Simulation, and Analysis</li>\n</ul>\n<ul>\n<li>Product Platform Planning and Architecting</li>\n</ul>\n<ul>\n<li>Product Software Design and Construction</li>\n</ul>\n<ul>\n<li>Product Verification and Validation Management</li>\n</ul>\n<ul>\n<li>System Requirements Engineering</li>\n</ul>\n<ul>\n<li>Systems Thinking</li>\n</ul>\n<ul>\n<li>Collaboration and Communication</li>\n</ul>\n<ul>\n<li>Decision Quality</li>\n</ul>\n<ul>\n<li>Self-Development</li>\n</ul>\n<ul>\n<li>Values Differences</li>\n</ul>\n<ul>\n<li>Statistical Methods</li>\n</ul>\n<ul>\n<li>Cross-Functional Design Integration</li>\n</ul>\n<ul>\n<li>Product Problem Solving</li>\n</ul>\n<ul>\n<li>Technical Documentation</li>\n</ul>\n<ul>\n<li>Product Development Execution, Monitoring, and Control</li>\n</ul>\n<p><strong>Education, Licenses, Certifications:</strong></p>\n<p>A Bachelor&#39;s degree in Engineering or a relevant STEM field is required. A post-graduate degree may be required for select roles. Licensing for compliance with export controls or sanctions regulations may also be necessary.</p>\n<p><strong>Experience:</strong></p>\n<p>This is an entry-level position, and preferred candidates will have relevant experience working in a temporary student employment environment or as an early career professional in a relevant technical discipline area. Knowledge of MS Office tools is also preferred.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_4251c883-eb0","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Cummins Inc.","sameAs":"https://cummins.jobs","logo":"https://logos.yubhub.co/cummins.jobs.png"},"x-apply-url":"https://cummins.jobs/wuhan-chn/electronic-systems-engineer-software/A3EF51D3B02E45C3A74184167CFB71F8/job/?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"entry","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Software Development","Systems Engineering","Product Development","Verification and Validation","Statistical Methods","Cross-Functional Design Integration"],"x-skills-preferred":["MS Office tools","Temporary student employment experience","Early career professional experience in a relevant technical discipline area"],"datePosted":"2026-08-07T16:00:50.377Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Wuhan"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Manufacturing","skills":"Software Development, Systems Engineering, Product Development, Verification and Validation, Statistical Methods, Cross-Functional Design Integration, MS Office tools, Temporary student employment experience, Early career professional experience in a relevant technical discipline area"}]}