This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

Responsibilities:

• Be responsible for the verification of ASIC design, architecture, golden models and micro-architecture of High Speed I/O controllers, like Ethernet and NVLink, at IP/sub-system levels using advanced DV methodologies such as UVM.
• Building reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
• Understanding the design specification and implementation, defining the verification scope, developing test plans, tests, and the verification infrastructure used to verify the correctness of the design.
• Collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

Requirements:

• Bachelors or Masters Degree (or equivalent experience) with 5+ years of relevant experience
• Experience at Unit/Sub-system/SOC level and expertise in SystemVerilog, UVM
• Expertise in comprehensive verification of IP or interconnect protocols (e.g. Ethernet, USB, SATA)
• Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies (UVM) and exposure to industry standard verification tools for simulation
• Excellent debugging, analytical, and problem solving skills
• Great communication and collaboration skills to interact within the team and across functional teams

Nice to Have:

• Good understanding of the system level architecture of HSIO-based designs, like Ethernet or CXL
• Experience with Perl, Python or similar scripting and/or SW programming languages is highly desirable
• Experience with AI-enabled code assist or root-cause analysis tools

You will also be eligible for equity and benefits.

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The successful candidate will lead the day-to-day technical ownership of a tightly coupled GPU supercomputing environment coordinated with multiple quantum modalities. This position is ideal for someone with experience building and operating production HPC environments, understanding low-level systems and networking, and working hands-on with quantum hardware.

Hybrid Quantum–HPC Platform Engineering

• Build, deploy, and operate a hybrid computing platform combining large-scale NVIDIA GPU clusters with physical quantum processors.
• Integrate quantum control systems and access nodes with HPC infrastructure using APIs, scientific applications, and orchestration frameworks.

HPC Systems & Operations

• Ensure reliability, performance, administration, and lifecycle management of the Quantum environment.
• Collaborate with networking and facilities teams to meet quantum hardware requirements.

Vendor & Partner Collaboration

• Serve as a technical interface to quantum hardware partners.
• Define hosting, systems architecture, and integration requirements for new quantum systems.

Application Enablement & Performance

• Deploy, optimize, and benchmark hybrid workloads across simulation, quantum error correction, and machine learning.
• Prototype and evaluate end-to-end workflows demonstrating platform capabilities.

Requirements:

• 12+ years of hands-on experience operating HPC or large-scale compute infrastructure.
• Bachelor’s or Master’s degree in Physics, Electrical/Computer Engineering, Computer Science.
• Strong background in Linux systems administration, job schedulers, and computing environments.
• Experience working in data center environments, including networking, storage, power, and operational constraints.
• Familiarity with quantum computing concepts and hardware architectures.

Benefits:

• Highly competitive salary
• Comprehensive benefits package
• Equity eligibility

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The successful candidate will serve as the primary point of contact for workplace and facilities matters, maintaining smooth daily operations and a safe, efficient environment.

Responsibilities:

• Manage day-to-day operational matters, ensuring efficient site operations
• Oversee site operations, including reception, security, business continuity, EHS, and sustainability initiatives
• Continuously improve the physical workplace to ensure it is safe, compliant, and supports employee productivity
• Collaborate with Site Leadership and the RESS Regional Lead to build and sustain an outstanding employee experience
• Prepare, manage, and forecast site operating budgets
• Oversee vendor relationships, contracts, and risk management processes
• Lead space planning and facilities coordination
• Support site logistics and operations

Requirements:

• 8+ years of experience in office management or facilities management
• Bachelor's degree in Business Administration or equivalent experience
• Outstanding communication and interpersonal skills
• Strong customer service orientation
• Ability to prioritise in a fast-paced environment

Benefits:

• Highly competitive salary
• Comprehensive benefits package
• Equity eligibility
• Visit www.nvidiabenefits.com/ for more information

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The successful candidate will:

• Research and craft architecture solutions for chip-to-chip communication, optimizing for performance, area, power, security, and resiliency
• Collaborate with other design teams to define interfaces and flows between NVLink blocks and the rest of the chip
• Perform architectural modeling, validation, definition, and documentation
• Drive implementation across design, verification, firmware, and software teams
• Work with switch teams to define NVLink fabric architecture
• Define network configuration and management flows

Requirements include:

• Master's or Ph.D. in Electrical Engineering, Computer Science, or Computer Engineering (or equivalent experience)
• At least 8 years of relevant experience in architecture, design, and verification
• Experience with innovative ASIC design processes
• Proven track record of shipping multiple projects with skills in processor and I/O architecture
• Proficiency in C++ and Verilog

NVIDIA offers equity and benefits to its employees.

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Job Overview: As a Physical Design Engineer, you will own RTL-to-gate synthesis and QoR convergence for complex digital blocks and hierarchical partitions. You will optimize synthesis strategies, constraints, and flows to meet performance, power, and area targets. Additionally, you will analyze design bottlenecks and QoR regressions, collaborating with various teams to resolve them.

Key Responsibilities:

• Own RTL-to-gate synthesis and QoR convergence for complex digital blocks and hierarchical partitions.
• Optimize synthesis strategies, constraints, and flows to meet performance, power, and area targets.
• Analyze design bottlenecks and QoR regressions, collaborating with RTL, timing, architecture, and physical design teams to resolve them.
• Support physical implementation from floorplanning and power planning through routing and timing closure.
• Automate design setup, execution, reporting, and issue triage while improving project-wide methodologies and best known methods.

Requirements:

• BSEE, MSEE, or equivalent experience.
• 2+ years of experience in synthesis and physical implementation on advanced process nodes.
• Strong proficiency with Synopsys Fusion Compiler, Cadence Genus, or comparable synthesis tools.
• Hands-on experience with synthesis constraints, timing analysis, QoR optimization, and the full place-and-route flow.
• Strong analytical and debugging skills across RTL, synthesis, timing, and physical implementation.
• Proficiency in Python, Perl, Tcl, and Make.
• Strong communication and multi-functional collaboration skills.

Benefits: You will also be eligible for equity and benefits.

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Your daily work will involve all aspects of physical chip development (RTL2GDS) – trial synthesis, power and clock distribution, place and route, timing closure, power and noise analysis and physical verification.

To be successful in this role, you will need to have a successful track record of delivering designs to production, and be able to assist in design flow development and debugging, including application of ML/AI solutions.

You will also need to be a validated strong power user of P&R, Timing Analysis, Physical Verification, IR Drop Analysis, CAD tools from Synopsys (ICC2/DC/PT/STAR/ICV), Cadence (Genus/Innovus/Tempus) and other major EDA companies.

If you are a great teammate with strong analytical and debugging skills, and proficiency using Python, Perl, Tcl, Make scripting, we would love to hear from you.

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You will analyze and optimize design constraints and synthesis parameters to achieve performance, power, and area targets. You will help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.

To be successful in this role, you will need to have a strong background in synthesis and timing, with hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence. You will also need expertise in analysis and fixing of timing paths through ECOs, including crosstalk and noise analysis.

In addition, you will need to have expertise in physical design and optimization, such as placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power. A background in logic synthesis and/or logical equivalence checking (LEC) is also required.

You will need to have expertise and in-depth knowledge of industry standard EDA tools (Synopsys PrimeTime or Cadence Tempus) and proficiency in Python, Tcl, and Make for automation and scripting tasks.

A background in domain-specific STA and timing convergence, such as CPUs, GPUs, or network processor implementation or SOCs, is a plus. Understanding of DFT logic and experience with DFT timing closure for various modes, such as scan shift and capture, transition faults, BIST, etc. is also a plus.

Knowledge of deep sub-micron technology and associated process variations effects, including modeling and converging considering process variations, is also a plus. Experience in methodology and/or flow development as well as automation is also a plus.

As a Senior ASIC Timing Engineer, you will be working on cutting-edge technology and will have the opportunity to make a significant impact on the success of our products. You will be part of a talented team of engineers who are passionate about their work and are committed to delivering high-quality results.

If you are a motivated and experienced engineer who is looking for a new challenge, we encourage you to apply for this exciting opportunity.

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