{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/city/thalwil/"},"x-facet":{"type":"city","slug":"thalwil","display":"Thalwil","count":1},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_477aff29-633"},"title":"ASIC Engineer","description":"<p>Join a multi-disciplined engineering team at Cisco focused on designing analog circuits and components for ASICSs deployed across a range of Cisco platforms. You will collaborate with industry-leading experts to meet power, performance, and area goals for high-volume, high-quality products.</p>\n<p><strong>Your Impact</strong></p>\n<ul>\n<li>Collaborate on the definition and design of high-performance analog circuits.</li>\n<li>Own physical design of analog circuits.</li>\n<li>Lead design verification activities and write comprehensive simulation plans and test benches.</li>\n<li>Drive signal and power integrity for ASIC integration and guide design changes.</li>\n<li>Analyse and validate ASIC subsystems and debug complex code.</li>\n</ul>\n<p><strong>Minimum Qualifications</strong></p>\n<ul>\n<li>Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 5+ years of ASIC design experience; or Master’s degree with 3+ years; or PhD with relevant experience.</li>\n<li>Strong background in analog and mixed-signal circuit design, layout, and verification.</li>\n<li>Experience with analog circuit design and verification tools.</li>\n<li>Experience with physical design, signal and power integrity, and debugging complex code.</li>\n<li>Ability to document functional and user specifications effectively.</li>\n</ul>\n<p><strong>Preferred Qualifications</strong></p>\n<ul>\n<li>Advanced knowledge of ASIC design tools, methodologies, and industry best practices.</li>\n<li>Expertise in power, performance, and area optimization for ASICs.</li>\n<li>Familiarity with ASIC tapeout processes and block-level issue resolution.</li>\n<li>Ability to drive development milestones and lead design reviews effectively.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">Job Data by <a href=\"https://yubhub.co\">YubHub</a>.</p>","url":"https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Thalwil-Switzerland/ASIC-Engineer_2021353-1","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Cisco","sameAs":"https://www.cisco.com","logo":"https://logos.yubhub.co/cisco.com.png"},"x-apply-url":"https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Thalwil-Switzerland/ASIC-Engineer_2021353-1","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["analog circuit design","mixed-signal circuit design","ASIC design","physical design","signal and power integrity","debugging complex code"],"x-skills-preferred":["ASIC design tools","power, performance, and area optimization","ASIC tapeout processes","design reviews"],"x-benefits":[],"x-licences":[],"x-visa-sponsorship":"unknown","x-visa-sponsorship-text":null,"x-work-authorisation":"unknown","x-work-authorisation-text":null,"datePosted":"2026-10-24T21:27:00.724Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Thalwil"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"analog circuit design, mixed-signal circuit design, ASIC design, physical design, signal and power integrity, debugging complex code, ASIC design tools, power, performance, and area optimization, ASIC tapeout processes, design reviews"}]}