As a Staff Software Engineer at Tenable, you will solve some of the team's toughest technical problems and build solutions that hold up as the product grows. You will partner with product managers, architects, and other engineers on technical approach and planning, contributing perspectives that can extend beyond your immediate area when it's useful. You will act as a go-to technical resource for complex design and architecture questions, helping ensure solutions hold up against business needs, compliance standards, and long-term maintainability.

Your responsibilities will include:

• Solving some of the team's toughest technical problems and building solutions that hold up as the product grows
• Partnering with product managers, architects, and other engineers on technical approach and planning
• Acting as a go-to technical resource for complex design and architecture questions
• Taking ownership of the most complex technical issues that come up in your systems, driving root cause analysis and fixes that hold up over time
• Mentoring other engineers through code review, design discussions, and everyday guidance

You will also have the opportunity to:

• Take deep ownership of significant, technically demanding components, and help evolve core infrastructure so it stays reliable and scalable as the product grows
• Work with a high degree of independence on complex technical initiatives
• Help shape automation, testing, and deployment practices that raise the bar for reliability and velocity

To be successful in this role, you will need:

• A BSc in Computer Science or an equivalent degree from a recognised institution, or an exceptional track record in server-side development with advanced technical expertise
• 8+ years of professional experience in software engineering, with a demonstrated ability to take on complex, ambiguous problems independently and consistently deliver high-quality outcomes
• Deep expertise in one or more programming languages such as C/C++, C#, Java, Go, Python
• Extensive experience building highly scalable, distributed systems, with a strong understanding of microservices architecture, API design, and cloud-native development
• Demonstrated success designing and deploying services at scale on cloud platforms such as AWS, Azure, or GCP

We offer a culture of belonging, respect, and excellence where you can be your best self. We are committed to promoting Equal Employment Opportunity (EEO) at Tenable.

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As a Staff Product Manager, you will play a key role in the product life cycle with an emphasis on customer requirements, as well as generating and defining the product vision. You will work closely with multiple departments, including product management, engineering, UX/UI, sales, customer support, finance, and marketing, to ensure customer requirements are met.

Your Opportunity:

• Own and lead the vision, strategy, and execution for the Cloud Threat Detection domain, driving end-to-end product development of threat detections and stories, AI risk assessment, eBPF agent, container runtime protection and more.
• Engage directly with customers and prospects to gather insights, validate assumptions, and ensure product decisions align with real-world security challenges.
• Collaborate cross-functionally with engineering, design, and research teams to deliver high-impact features and platform capabilities.
• Drive both inbound and outbound product efforts.
• Define product strategy and roadmap.

What You'll Need:

• 8+ years of proven experience in product management, focused on cloud-native security domains such as threat detection and stories, AI risk assessment, eBPF agent, and container runtime protection.
• Deep understanding of threat hunting, security orchestration, and public cloud environments (AWS, Azure, GCP, etc.), including security frameworks, key services, IAM concepts, and runtime protection.
• Proven ability to define and execute product strategy,from customer discovery to roadmap planning and successful release.
• Excellent English, both written and verbal, including great presentation skills.
• Bachelor’s degree in a technical field or equivalent practical experience.

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As a Senior Software Engineer - Cloud Security, you will design and develop complex, scalable, and high-performance features and systems, collaborating with product managers, architects, and fellow engineers to shape technical approaches and project plans.

Your responsibilities will include:

• Designing and developing complex, scalable, and high-performance features and systems
• Collaborating with product managers, architects, and fellow engineers to shape technical approaches and project plans
• Providing technical input and recommendations to ensure solutions align with business objectives, compliance standards, and long-term maintainability
• Diagnosing and resolving complex production issues within your team's systems
• Mentoring engineers through code review, pairing, and day-to-day guidance

You will also have the opportunity to:

• Develop and maintain key components and features, integrating new functionality and helping maintain the reliability and scalability of core infrastructure
• Contribute to the evolution of software applications, database integration, interfaces, and system enhancements to meet business needs
• Support automation, testing, and continuous deployment processes to ensure smooth and reliable delivery of new features
• Own well-scoped projects from design through delivery, contributing ideas to design decisions and technical direction within your team

To succeed in this role, you will need:

• A BSc in Computer Science or an equivalent degree from a recognised institution, or an exceptional track record in server-side development with advanced technical expertise
• 5+ years of professional experience in software engineering, with a proven ability to solve complex problems and deliver reliably within a team
• Deep expertise in one or more programming languages such as C/C++, C#, Java, Go, Python
• Solid experience building scalable systems, with a strong understanding of microservices architecture, API design, and cloud-native development
• Experience designing and deploying services on cloud platforms such as AWS, Azure, or GCP
• Strong technical skills, with experience reviewing code, mentoring less experienced engineers day-to-day, and contributing to technical decisions within the team
• Proven ability to manage multiple priorities and deliver reliably under tight deadlines

We offer a culture of belonging, respect, and excellence, where you can be your best self. We're committed to promoting Equal Employment Opportunity (EEO) at Tenable.

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You will combine deep technical expertise, strong customer relationships, and a forward-looking product vision to shape the platform’s evolution.

This is a high-impact individual contributor role with broad ownership across data, access, integrations, and shared customer experiences.

Your Opportunity:

• Define and drive the long-term vision, strategy, and roadmap for Tenable Cloud Security and AI Exposure Platform aspects, anticipating customer needs and opening new possibilities for the platform.
• Build close relationships with customers and prospects to understand their workflows, uncover unmet needs, and validate product direction.
• Lead technically complex capabilities across the unified data model, APIs, integrations, and access management, partnering with engineering on architectural decisions and tradeoffs.
• Drive innovation in how customers interact with, administer, and extend the platform, including experiences enabled by AI and agents.
• Lead strategic initiatives across product domains, engineering, and design, aligning stakeholders around shared priorities and resolving complex product tradeoffs.
• Shape a cohesive platform experience across onboarding, settings, navigation, resource organization, and licensing.
• Develop the platform’s integration ecosystem through API standards, developer experiences, and technology partnerships.
• Own outcomes from discovery through delivery and adoption, defining success metrics and using customer insights and usage data to guide investment.

What You'll Need:

• 5+ years of product management experience, including significant ownership of technically complex platform or enterprise software products.
• Deep technical understanding of data models, APIs, access control, and integrations, with the ability to engage in architectural discussions and make informed product decisions.
• A proven track record of building direct customer relationships and translating customer needs into synergistic platform capabilities with measurable value.
• Demonstrated ability to define a compelling long-term vision, identify opportunities for innovation, and translate them into an actionable roadmap.
• Proven success leading complex initiatives across multiple teams and influencing senior stakeholders without formal authority.
• Strong product judgment, including the ability to balance immediate customer needs with scalable platform investments.
• Ability to hold and combine both platform level considerations as well as domain specific constraints.
• Excellent English communication and presentation skills, with the ability to explain complex concepts clearly to technical and business audiences.
• Bachelor’s degree in a technical field or equivalent practical experience.

Experience with cloud security, enterprise SaaS platforms, or multi-product or platforms is a plus.

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You will work with Solution Architects to guide enterprise and strategic customers in architecting production-grade ML & AI applications on Databricks, while aligning their technical roadmap with the continually evolving Databricks Data Intelligence Platform.

The impact you will have:

• Architect production level ML & AI workloads for customers using our unified platform, including agents, end-to-end ML pipelines, training/inference optimisation, integration with cloud-native services, MLOps, etc.
• Serve as trusted practitioner for enterprise GenAI solutions, including RAG architectures, agentic systems, natural language querying of structured data, AI evaluation and observability, and monitoring systems
• Build, scale, and optimise customer AI workloads and apply best in class MLOps to productionise these workloads across a variety of domains
• Provide advanced technical support to Solution Architects during the technical sale ranging from feature engineering, training, tracking, serving to model monitoring all within a single platform, as well as participating in the larger ML SME community in Databricks
• Collaborate cross-functionally with the product and engineering teams to represent the voice of the customer, define priorities and influence the product roadmap, helping with the adoption of Databricks’ AI offerings

What we look for:

• 7+ years of hands-on industry ML experience in at least one of the following:
• ML Engineer: Build and maintain production-grade cloud infrastructure that supports the deployment of ML applications, including drift monitoring.
• AI Engineer: Experience with the latest techniques in LLMs & agentic systems including vector databases, fine-tuning LLMs, AI guardrail systems, and deploying LLMs with tools such as HuggingFace, Langchain, and OpenAI
• Experience with data engineering, or a good understanding of the concept of data engineering
• Experience communicating and/or teaching technical concepts to non-technical and technical audiences alike
• Passion for collaboration, life-long learning, and driving business value through ML & AI
• [Preferred] 5+ years customer-facing experience in a pre-sales or post-sales role
• Can meet expectations for technical training and role-specific outcomes within 3 months of hire

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Responsibilities:

• Join the design team for performance and power management related IPs.

• Design according to specifications and performance requirements.

• Work in a combined design and verification team which develops core IPs within the Networking silicon.

• Work closely with multiple teams within the organisations such as Architecture, Micro-Architecture, verification and Post-Silicon validation.

Requirements:

• 5+ years of proven experience in RTL Design.

• B.SC./ M.SC. in Electrical Engineering or Computer Engineering.

• A great teammate with good communication and interpersonal skills

• High level English

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You’ll lead a portfolio and roadmap of projects that encompass agentic-AI for data-center management, predictive-resiliency, optimization and more. By collaborating closely with subject-matter-experts (SMEs), applied-researchers, product-managers, architects, data-engineers and other stakeholders you will push the envelope forward in using cutting-edge technologies and data-driven insights to improve NVIDIA's products.

Responsibilities:

• Build a shared roadmap and vision for AI based data-center management solutions spanning LLM intelligence for troubleshooting, predictive-resiliency and AIOPS, black-box optimization and performance tuning.
• Work closely with engineering and reliability teams to scope and define workflows utilizing and benefitting from AI/ML.
• Drive the integration of AI capabilities into system architecture and engineering workflows.
• Identify system-level opportunities for failure management, automated troubleshooting, performance improvement, and resource optimization.
• Translate system behavior, dependencies, data, and operational constraints into formulated research problems.

Requirements:

• Ph.D in electrical engineering, machine-learning, computer-science or another relevant field.
• 10+ years of deep technical experience in high-performance network architecture, data center networking, or distributed systems design.
• Mastery of high-speed interconnect protocols including InfiniBand and/or advanced Ethernet architectures.
• Thorough experience driving high-impact projects centered on modern AI/ML such as LLMs/agents, deep-learning, black-box optimization or another relevant field.
• Deep knowledge of AI/ML and networking-hardware/system-architecture.
• Excellent ability to convey and communicate data-based insights to stakeholders and management.
• Experience demonstrating an excellent track of collaboration with hands-on teams.

Nice to Have:

• Demonstrated track record of architecting and deploying multi-thousand-node GPU clusters for hyperscale cloud environments.
• Deep knowledge of NVIDIA networking technologies, including BlueField DPUs, Quantum InfiniBand switches, and Spectrum Ethernet platforms.
• Expertise in in-network computing, telemetry, adaptive routing, and telemetry-driven network optimization.
• High energy and a positive, proactive and curious approach.

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You will act as a technical engine , refining Secure PLC processes, driving complex security certifications, and building automated workflows that scale governance across hardware, firmware, and software products. Integrate global cybersecurity regulations directly into modern hardware and software engineering workflows.

Responsibilities:

• Translate Regulations into Technical Requirements: Analyze global cybersecurity regulations and legal mandates, converting complex compliance standards into actionable technical specifications and engineering rules.
• Architect Secure PLC Workflows: Optimize, adapt, and scale Secure Product Development Lifecycle processes, embedding security engineering frameworks directly into active software, firmware, and hardware development pipelines.
• Drive Technical Certifications and Audits: Lead end-to-end security evaluations and certification initiatives, conducting deep-dive technical reviews and working directly with lab evaluators and engineering teams.
• Build AI and Engineering Automation: Implement hands-on automation frameworks and agentic AI workflows to streamline compliance tracking, evidence collection, and security verification directly within engineering systems.
• Partner Across Technical and Executive Teams: Serve as the technical authority partnering with Hardware, Software, Product Management, and Legal teams to deliver actionable insight into our overall product security architecture and compliance readiness.

Requirements:

• Broad Compliance Framework Mastery: Extensive background in secure product and system development lifecycle frameworks, risk management standards, and a strong awareness of global security regulatory trends.
• Education and Experience: BSc or MSc in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience, with 5+ years of experience in security engineering, product security governance, or secure development programs.
• Deep Secure Development Mastery: Practical expertise with secure development lifecycles, threat modeling, risk engineering, and hardware/software security practices.
• Technical and System-Level Depth: Ability to analyze system architectures, low-level firmware, and codebases to ensure technical implementations match governance mandates.
• Technical Evaluation Experience: Direct experience leading hardware, firmware, or software products through third-party security evaluations, testing, or formal validations.
• Hands-On Coding and Automation Skills: Shown ability to write code and build automation scripts, AI workflows, or tooling to address complex engineering and operational security tasks.
• Multi-Functional Technical Leadership: Strong communication and engineering collaboration skills to drive alignment and execution across multidisciplinary technical teams.

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As a Chip Design Verification Engineer, you'll design and implement the next generation state-of-the-art Switch Silicon chips, making a real impact in a dynamic, technology-focused company while developing high-speed communication devices with the highest throughput and lowest latency.

Responsibilities:

• Work in a design and verification team that develops the front-end design for the Switch silicon and the GPU.
• Develop verification components and reference models, verify and simulate chip blocks according to specifications under challenging constraints with a high orientation to power, area, and performance.
• Work closely with multiple teams within organisations such as Architecture, Micro-Architecture, and FW.

Requirements:

• Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate with high scores, or equivalent experience.
• Completion of programming and logic design courses with high scores.
• 3-5 years of experience in RTL verification.
• A team player with good communication and interpersonal skills.

Benefits:

• Join a team of passionate engineers working on cutting-edge technology.
• Opportunity to develop high-speed communication devices with the highest throughput and lowest latency.

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As a Chip Design Engineer at NVIDIA's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

Responsibilities

• Work in a combined design and verification team which develops some of the switch silicon core units.
• Plan and Design RTL units / blocks according to Arch & Micro arch specifications under challenging constraints with high orientation to power, area, and performance.
• Build reference models, verify and simulate chip blocks/entities according to specifications.
• Work closely with multiple teams within organizations such as Architecture, Micro-Architecture, and FW.

Requirements

• B.Sc. in Electrical Engineering or Computer Engineering.
• 4+ years of experience in RTL design or RTL verification.
• Previous experience in networking - an advantage.
• A team player with good communication and interpersonal skills.

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You will be joining a combined design and verification team for performance and power management related IPs. Your responsibilities will include building reference models, verifying and simulating according to specifications and performance requirements, and working closely with multiple teams within the organization such as Architecture, Micro-Architecture, and design.

To be successful in this role, you will need:

• 3+ years of experience in RTL Verification.
• B.SC./ M.SC. in Electrical Engineering or Computer Engineering.
• Good communication and interpersonal skills.

Experience with System-Verilog UVM is an advantage.

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Responsibilities:

• Act as technical liaison for our technical teams.
• Project manage highly impactful large and small scale data center and lab projects.
• Participate in the installation, monitoring, maintenance, support, and optimization of all production server hardware.
• Contribute to the development of the global DC knowledge base.
• Lead teams to deploy new data center infrastructure, deliver server upgrades, integration, rebuild and other projects as required.
• Build plans to optimize power, cooling and network resources.
• Inventing the forecast to efficiently match supply to demand.
• Hunt for and resolve issues as well as analyze data looking for trends and systemic issues.

Requirements:

• 5+ years of experience in large-scale data center hardware deployments, building data centers and directly leading data center relocation projects.
• Technical certification and/or relevant work experience.
• Ability to understand internal customer problem and provide technical solution in timely manner.
• Demonstrable ability to prioritize effectively, and experience with technical project management.
• Understanding of Data Center infrastructure including power, cooling, structured cabling (copper, fiber).
• Experience in developing and reviewing MOP and SOPs, to minimize our operating risks.
• Strong interpersonal skills and ability to communicate effectively with a diverse group of customers and staff.
• Deep understanding of data center power and cooling (liquid, air etc..) infrastructure, network and cabling infrastructure and root cause analysis skills.

Nice to Have:

• Knowledge of programming languages (Python, SQL, Bash etc.).
• Experience with Nautobot/Netbox, monitoring tools, Service Now and Inventory Management tools.
• You're a self-starter with an attitude for growth, continuous learning, and constantly looking to improve the team and build strong business relationships.
• Attention to detail with superb interpersonal skills and the ability to effectively manage multiple priorities.
• Theoretical and/or hands-on knowledge of liquid cooling infrastructure.

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You will work on some of the most groundbreaking technology as a IC-System Architect for High-Speed Networks at NVIDIA focusing on improving our ASIC solution.

Responsibilities:

• Crafting and architecting the ASIC - System requirements for NVIDIA Systems focusing on ASIC yield improvements.
• Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and hardware teams, to ensure the successful execution of the project optimizing High-speed networking system in the out of space environment.
• Leading the development and implementation of the systems to ensure world-class performance, reliability and at scale high quality ASIC manufacturing.
• Successfully implementing and managing projects to meet ambitious deadlines and performance targets.

Requirements:

• BSc or MSc in Electrical Engineering or equivalent experience.
• 8+ years of experience in Chip design, System and HW.
• Deep understanding of how to build and integrate systems with various technology components.
• Proficiency in advanced system-level Architecture.
• Excellent communication skills to effectively work with diverse teams and collaborators.
• Can-do attitude and high energy with leadership and excellent interpersonal skills and possess the ability to learn sophisticated concepts in a fast-paced environment.
• Possess strong managerial, problem solving and critical thinking skills.
• Attention to details on design and high focus on design quality.

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Our next-generation InfiniBand, NVL and Ethernet switches will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used in vast industries.

You will work on some of the most groundbreaking technology as a System Architect for High-Speed Networks at NVIDIA focusing on deployment of system in Space.

Responsibilities:

• Define and lead the Architecture of Power, Thermal and more ASIC requirement for system to be sent to Space.
• Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and hardware teams, to ensure the successful execution of the project optimizing High-speed networking system in the out of space environment.
• Crafting and architecting the ASIC and System requirements for NVIDIA Systems to be sent to space.
• Leading the development and implementation of the systems to ensure world-class performance and reliability.
• Successfully implementing and managing projects to meet ambitious deadlines and performance targets.

Requirements:

• BSc or MSc in Electrical Engineering or equivalent experience.
• 8+ years of experience in Space environment Systems.
• Deep understanding of how to build and integrate systems to be sent to space with various technology components.
• Proficiency in advanced system-level space systems.
• Excellent communication skills to effectively work with diverse teams and collaborators.
• Can-do attitude and high energy with leadership and excellent interpersonal skills and possess the ability to learn sophisticated concepts in a fast-paced environment.
• Possess strong managerial, problem solving and critical thinking skills.
• Attention to details on design and high focus on design quality.

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What you'll be doing:

• Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
• Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
• Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
• Taking part in flows development.

What we need to see:

• B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent experience.
• 5+ years of relevant experience.
• Proven experience in RTL2GDS flows and methodologies.
• Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
• Deep understanding of all aspects of Physical construction and Integration.
• Knowledge in Physical Design Verification methodology LVS/DRC.
• Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
• Great teammate.

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In this Architect role, you will define the Architecture of the firmware management of our next-generation switches that support many innovative compute clusters and supercomputers.

Responsibilities:

• Collaborate with multi-functional teams, including other architecture teams, system software, firmware, and hardware teams, to ensure the successful execution of the project.
• Define the build framework for firmware management, power, and thermal running on switches.
• Help determine and implement the strategic vision for NVIDIA networking alongside adjacent software and hardware architects.

Requirements:

• BSc or MSc in Electrical Engineering / Computer Science or equivalent experience.
• 5+ years of practical experience in firmware design and/or firmware architecture.
• Excellent communication skills to effectively work with diverse teams and collaborators.
• Can-do attitude and high energy with leadership and excellent interpersonal skills, and the ability to learn sophisticated concepts in a fast-paced environment.
• Strong managerial, problem-solving, and critical thinking skills.

Preferred Qualifications:

• Knowledge of Ethernet/IP technologies, cloud, or data-center technologies.
• Experience in programming computer networks.
• Strong understanding of system build principles.

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Our future InfiniBand, NVL, and Ethernet switches will be central to connecting and powering the world’s most advanced compute clusters. These include supercomputers dedicated to AI research and high-performance clusters in various sectors.

As an Architect of Advanced Packaging at NVIDIA, you will engage with innovative technology. You will help create next-generation large radix switches. The products you develop will support many pioneering compute clusters and supercomputers.

Responsibilities:

• Collaborate with cross-functional teams, including other architecture teams, logic build, system and hardware teams, to ensure the successful execution of the project optimizing our solution.
• Crafting and architecting advanced packaging solutions for NVIDIA Systems.
• Analyzing and determining the best approaches for our switch system solutions.
• Successfully implementing and managing projects to meet ambitious performance targets.

Requirements:

• BSc or MSc in Electrical Engineering / Computer Science or equivalent experience.
• A proven track record with a minimum of 8 years of experience in Advanced Packaging.
• Deep understanding of how to build and integrate systems with various technology components.
• Proficiency in advanced system-level high-speed connectivity.
• Excellent communication skills to effectively work with diverse teams and collaborators.
• Can-do attitude and high energy with leadership and excellent interpersonal skills and possess the ability to learn sophisticated concepts in a fast-paced environment.
• Possess strong managerial, problem-solving, and critical thinking skills.
• Attention to details on building and high focus on build quality.

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As a Senior HPC DevOps Engineer, you'll be a key player in groundbreaking advancements in artificial intelligence and GPU computing.

Responsibilities:

• Design, implement, and maintain large-scale HPC/AI clusters with state-of-the-art monitoring, logging, and alerting systems.
• Utilize and develop tools to manage infrastructure as code, ensuring scalable and repeatable deployments.
• Develop and maintain continuous integration and continuous delivery (CI/CD) pipelines to automate and streamline deployment processes.
• Develop automation scripts and tools to automate deployment, configuration management, and operational monitoring.
• Develop complex networking automations.
• Perform comprehensive troubleshooting from bare metal to application level, ensuring system reliability and efficiency.
• Serve as a technical resource, developing and sharing best practices with internal teams.
• Support R&D activities and engage in proof of concepts (POCs) and proof of values (POVs) for future improvements.

Requirements:

• B.Sc. in Computer Science, Engineering, or a related field
• 5+ years of experience
• Advanced proficiency in programming and scripting languages, with a solid understanding of object-oriented programming principles.
• Familiarity with Jenkins, Ansible, Puppet/Chef.
• Deep understanding of Kubernetes and container-related microservice technologies.
• Hands-on experience with event streaming or message queue technologies e.g. Apache Kafka.
• Experience with multiple storage solutions like Lustre, GPFS, ZFS, and XFS.
• Expertise with virtual systems (VMware, Hyper-V, KVM, Citrix).
• Familiarity with cloud platforms (AWS, Azure, Google Cloud).

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Key Responsibilities:

• Define and develop characterization and validation techniques for post-silicon bring-up and production testing.
• Lead methodology planning for future products and serve as the synchronization point between teams.
• Drive alignment on tooling, flows, and coverage requirements ahead of tape-out and first silicon.
• Translate product requirements and silicon behavior into structured characterization plans.
• Lead methodology transfer into execution, ensuring tooling, methods, and engineers are in place for a smooth handoff.
• Identify methodology gaps early in the program cycle and resolve them through cross-functional collaboration.

Requirements:

• B.Sc. in Electrical Engineering (or equivalent experience).
• 8+ years of experience with DFT, IC silicon validation, product engineering, or test engineering.
• 2+ years of managerial experience.
• Ability to work in a fast-paced, multifaceted environment with technical excellence and innovative thinking.
• Strong cross-functional communication skills.
• Hands-on engineering background with the ability to be technically authoritative.

Preferred Qualifications:

• Experience in developing verification environments and random-based verification using tools like simulation tools, Verilog, and debug tools.
• Experience with Specman/UVM.
• Understanding of RTL design (Verilog).
• Product engineering experience.

What We Offer:

• Opportunity to work on cutting-edge technologies.
• Collaborative and dynamic work environment.
• Chance to make a significant contribution to NVIDIA's products and achievements.

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The successful candidate will show strong background in C++ programming, ability to work independently and quickly learn new technology, good communication and motivated to solve sophisticated problems.

Responsibilities:

• Develop state-of-the-art, low-overhead, fine-precision tools for boosting performance of systems that combine CPU, GPU and DPU hardware units
• Work with emerging HW and SW solutions before they reach the market
• Partner closely with multi-disciplinary global SW and HW teams to continuously deliver innovation and improvements

Requirements:

• Bachelor’s Degree in Computer Science
• 5+ years experience developing high-performance applications using modern C++ (C++20)
• Excellent English
• A passion for clean, elegant, well documented source code!
• Ability to study sophisticated technologies with sparse guidance
• Great teamwork skills

Preferred Qualifications:

• Linux kernel development experience
• Development experience with Python, developer tools

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Responsibilities:

• Lead the ASIC development from concept and architecture stages through micro-architecture, design, verification, and physical design until tape-out.
• Post-Silicon Activities; Oversee chip power-on, bring-up, quality phases, and mass production.
• Execution Plans; Define and implement execution plans in collaboration with cross-discipline leaders in unit level, full-chip, physical design, and firmware/software emulation.
• Roadmap Definition; Contribute to the definition of NVIDIA's switch ASIC roadmap.

Requirements:

• BS or MS in Computer or Electrical Engineering or equivalent experience.
• 15+ overall years of proven experience in chip design.
• 8+ years of experience in chip design/verification management, leading teams of at least 8 direct reports.
• Proficiency in RTL design (Verilog), verification (UVM, System Verilog), System-On-Chip design/integration flow, and design automation.
• High system view with ability to collaborate with multiple interfaces.
• Strong analytical and problem-solving skills.
• Excellent communication and teamwork abilities.
• Experience in synthesis, and physical design is a plus.

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Key responsibilities include:

• Analyzing power data and driving ASIC teams to improve power efficiency
• Researching, developing, and deploying power analysis and reduction techniques
• Collaborating with architects, performance engineers, software engineers, and physical design teams
• Developing techniques to model, analyze, and reduce power consumption of NVIDIA Switches product line

Requirements:

• BSC or MS in Computer Engineering or Electrical Engineering
• 5+ years of experience in chip design
• Good interpersonal skills and ability to collaborate with design teams
• Familiarity with Verilog and ASIC design or verification
• Strong coding/automation skills in Python, Perl, and C++

Nice to have:

• Experience with Power Artist, PTPX (Prime Power RTL, RTL Architect)
• Strong understanding of energy consumption, estimation, data movement, and low power design

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What You'll Be Doing:

• Work in a design/verification team which develops core units within the Switch silicon as a dynamic verification or RTL design engineer.
• Build reference models, verify and simulate chip blocks/entities according to specifications under challenging constraints with high orientation to power, area, and performance.
• Design RTL of units/blocks according to Arch. specifications under challenging constraints with high orientation to power, area, and performance.
• RTL synthesis, timing, supporting verification, and silicon post TO activities.
• Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.

What We Need To See:

• Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience.
• 5+ years of experience in chip design.
• Knowledge in network protocols and/or HPC and distributed calculations - advantage.
• A team player with good communication and interpersonal skills.

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You will work in a combined design and verification team which develops some of the switch silicon core units.

Your responsibilities will include:

• Building reference models, verifying and simulating chip blocks/entities according to specifications under challenging constraints with high orientation to power, area, and performance.
• Working closely with multiple teams within organisations such as Architecture, Micro-Architecture, and FW.

To be successful in this role, you will need:

• A B.Sc. in Electrical/Computer Engineering or equivalent experience.
• 5+ years of experience in Verification or RTL design.
• Knowledge in network protocols and/or HPC.
• Good communication and interpersonal skills.

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Responsibilities:

• Acting as the technical lead for SOC clocks development , leading the implementation of the clocking logic from specification through tape-out and bring-up
• Working with the architecture and micro-architecture teams on the SOC clock and reset scheme: collecting clocking requirements from units across the chip, feeding back implementation and timing considerations, and translating the agreed scheme into a verifiable design
• Writing and reviewing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization
• Leading and mentoring other RTL engineers working on clocking: reviewing designs, setting coding and quality standards, and distributing work across the team
• Working hand-in-hand with the Physical Design (backend) team on clock tree implementation, SDC/timing constraints, partitioning, floorplan feedback, trial synthesis, and timing convergence
• Partnering with Design Verification on clocking testplans, functional and gate-level debug, and coverage closure
• Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows
• Representing clocking implementation in cross-functional design reviews with architecture, PD, DV, DFT, and CAD stakeholders

Requirements:

• B.Sc./M.Sc. in Electrical Engineering or Computer Engineering
• 8+ years of relevant experience in RTL/logic design, with multiple chips taken to tape-out
• Demonstrated technical leadership: leading a design area through implementation and tape-out, mentoring engineers, and coordinating across teams
• Expert hands-on RTL design skills in Verilog/SystemVerilog, with strong understanding of how RTL choices affect synthesis results, timing, area, and power
• Deep understanding of clocking and reset design: clock gating, clock muxing and dividers, glitchless clock switching, reset synchronization, and clock domain crossing
• Proficiency with design quality tooling , lint, CDC/RDC, formal verification, synthesis, and static timing analysis (STA) , including the ability to interpret results and drive fixes back into the RTL
• Experience taking a design from architecture and micro-architecture specification through verification, physical implementation, and silicon bring-up
• Great teammate with strong communication skills across micro-architecture, DV, backend, DFT, and software teams

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In this role, you will own the clock generation, distribution, and control logic for the entire chip , PLL and reference clock integration, clock muxing and dividers, glitchless switching, clock gating, reset synchronization, and the clock domain crossing infrastructure that every unit on the die depends on.

Responsibilities:

• Owning the SOC clocking logic end to end: writing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization, from micro-architecture specification through tape-out
• Defining and implementing the SOC clock and reset architecture together with the micro-architecture team , collecting clocking requirements from every unit on the chip and turning them into a coherent, verifiable design
• Owning clock domain crossing infrastructure and CDC closure across the SOC
• Partnering with the micro-architecture team to review specifications, close on design intent, and provide feedback on implementation cost, timing, area, and power
• Working hand-in-hand with the Physical Design (backend) team on clock tree implementation and constraints, partitioning, floorplan and timing feedback, trial synthesis, congestion and timing convergence, and physical design readiness
• Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows
• Driving design quality: lint, CDC/RDC, formal checks, synthesis QoR, connectivity and structural checks
• Supporting SOC-level chip build and assembly, and developing/deploying automation flows that make RTL integration and design quality checking repeatable and scalable
• Supporting emulation, firmware, and post-silicon bring-up customers of your design

Requirements:

• B.Sc./M.Sc. in Electrical Engineering or Computer Engineering
• 3+ years of relevant experience in RTL/logic design
• Solid hands-on RTL design skills in Verilog/SystemVerilog, with a good understanding of synthesis, timing, and how RTL choices affect the physical implementation
• Experience taking a design from micro-architecture specification through verification and physical implementation
• Solid understanding of clocking and reset concepts: clock gating, clock muxing and dividers, glitchless clock switching, reset synchronization, and clock domain crossing
• Familiarity with design quality tooling (lint, CDC/RDC, formal, synthesis)
• Great teammate with strong communication skills across micro-architecture, DV, and backend teams

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In this role, you will be a key contributor to defining the architecture and improving network performance for AI and High Performance Computing (HPC) workloads. You will model advanced network topologies, configurations, logic, and traffic patterns, and analyze their effect on end-to-end performance.

Responsibilities:

• Analyze and model NVIDIA's AI and HPC offerings, deep dive into network behavior for training and inference, and generate insights to directly impact the architecture of next-generation AI systems.
• Write production-quality C++ and Python code daily, hands-on modeling of advanced network topologies, configurations, and traffic patterns representing real-life AI workloads, and analyze their effect on the system's performance.
• Actively support the HW and SW development life cycles, map existing and candidate features into the simulation domain to enable their analysis, impact assessment, and optimization.
• Take full independent ownership of the performance modeling roadmap for a defined set of features, interface directly with internal clients, communicate analysis conclusions effectively, and iterate on them.
• Improve the quality of the simulation as a software product, ensuring robustness and reliability.

Requirements:

• BSc or above in Computer Science, Electrical Engineering, or a related field.
• 5+ years of recent hands-on coding experience with strong proficiency in C++ and Python.
• End-to-end system perspective, capable of bridging the gap between hardware behavior, micro-architecture, and software performance.
• Project ownership capability with proven ability to lead technical initiatives, prioritize features, and manage project lifecycles autonomously with minimal supervision.

Preferred qualifications:

• Strong background in communication networks technology, deep understanding of Ethernet, NVLink, and/or Infiniband technologies, data center infrastructure, and network protocols.
• Familiarity with discrete event simulators (e.g., OMNeT++, SystemC, or proprietary architectural simulators).
• Advanced degree or experience focusing on computer architecture, algorithms, networking, or distributed systems.

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As a Chip Design Engineer at NVIDIA's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips.

Responsibilities:

• Work in a design/verification team which develops core units within the Switch silicon.
• Micro-architecture of dynamic verification environments planning for units and modules.
• Design dynamic verification environments of units/blocks according to Arch. specifications under challenging constraints with high orientation to power, area, and performance.
• Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.

Requirements:

• Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience.
• 5+ years of experience in RTL design/dynamic verification.
• Knowledge in network protocols and/or HPC and distributed calculations - advantage.
• A team player with good communication and interpersonal skills.

NVIDIA is widely considered to be one of the technology world’s most desirable employers.

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In this role, you will be responsible for developing and optimizing the network simulation service. You will enhance the simulator performance and quality and scale it to support massive loads, additional clients, and unique use cases. You will work on integrating this infrastructure with cloud computation services and ensure the simulation is available as a service for AI agents and internal customers.

Responsibilities:

• Design and develop simulation capabilities, integrating internal and external libraries and maintaining a clean, scalable architecture for a complex software project.
• Expand the simulation versatility to accommodate advanced use cases and bleeding-edge requirements. Provide innovative solutions to scalability and fidelity trade-offs of the simulator.
• Improve the quality of the simulation as a software product, ensuring robustness and reliability.
• Expose the simulation as a service to facilitate easier access for different stakeholders.
• Enhance simulation runtime and memory consumption through creative optimization techniques.
• Integrate a new simulation management system, making simulated experiments data accessible to all users.
• Collaborate with DevOps engineers to develop our CI/CD infrastructure for the networking simulation service, ensuring efficient deployment and smooth integration processes.

Requirements:

• BSc or above in Computer Science, Computer Engineering, or a related field.
• 5+ years of relevant practical experience in software development, including significant work on a large-scale software system with strict performance considerations.
• Proficiency in C++ and Python with knowledge of optimization techniques for improving system performance.
• In-depth knowledge of computer science fundamentals, and computer architecture.
• Excellent system perspective – you must be able to grasp the impact each layer on the system and the users.
• Independent and motivated individual with strong communication skills.

Nice to Have:

• Development experience in a large, multidisciplinary simulation environment with many collaborators and diverse technical challenges.
• Familiarity with discrete event simulators (e.g., OMNeT++, SystemC, or proprietary architectural simulators).
• Knowledge of multi-core computation, code parallelization, and relevant technologies (e.g., MPI).
• Prior experience with cloud computing and parallelization of computational workloads.
• Experience in developing CI/CD pipelines and integrating services

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Identity is the key to unlocking the potential of AI. Okta secures AI by building the trusted, neutral infrastructure that enables organisations to safely embrace this new era. This work requires a relentless drive to solve complex challenges with real-world stakes. We are looking for builders and owners who operate with speed and urgency and execute with excellence.

This is an opportunity to do career-defining work. We're all in on this mission. If you are too, let's talk.

The Identity Security Posture Management (ISPM) Team

At ISPM (previously known as Spera), we are revolutionising the field of identity security, providing comprehensive solutions to address the challenges faced by modern organisations. Our platform provides security leaders with end-to-end contextual visibility of their identity landscape, reducing risks, enhancing operational efficiency, and ensuring compliance.

With an exceptional team dedicated to pushing boundaries and achieving remarkable results, we are seeking a talented engineer to join us in shaping the future of identity security.

This role requires working from the office three times a week.

What you'll be doing

As a Staff Software Engineer at ISPM, you will play a critical role in building our platform. Your expertise and contributions will have a direct impact on the success and effectiveness of our product. Specifically, your responsibilities will include:

• Lead, design, architect and build high-quality scalable software by introducing best practices around software engineering architecture and processes
• Raise the bar on engineering excellence by improving standard methodologies, producing best-in-class code, documentation, testing, and monitoring
• Collaborate with product and R&D engineers to translate product requirements into technical solutions
• Identify and resolve technical issues and performance bottlenecks
• Stay up to date with the latest industry trends and technologies to continuously improve our products
• Be a mentor for colleagues and help promote knowledge-sharing

What you'll bring to the role

• 7+ years of experience as a software engineer, preferably in a fast-paced environment
• 3+ years of programming experience with Python, specifically focused on backend development
• A proven track record of successfully building and delivering large-scale systems
• Solid understanding of software engineering principles, design patterns, and best practices
• Excellent problem-solving skills and a detail-oriented mindset
• Strong communication and collaboration abilities to work effectively within a team

Extra credit if you have experience in any of the following

• Experience with Snowflake or other data warehousing platforms
• Experience with Amazon Web Services and modern cloud stack

The Okta Experience

• Supporting Your Well-Being
• Driving Social Impact
• Developing Talent and Fostering Connection + Community

We are intentional about connection. Our global community, spanning over 20 offices worldwide, is united by a drive to innovate. Your journey begins with an immersive, in-person onboarding experience designed to accelerate your impact and connect you to our mission and team from day one.

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In this role, you will manage a team of skilled verification engineers, providing technical leadership and overseeing the execution of verification plans.

Key Responsibilities:

• Lead, mentor, and develop a team of software verification engineers, promoting technical excellence and professional growth.
• Provide technical guidance and hands-on mentorship, driving the creation of comprehensive verification plans and automated environments using Python.
• Lead end-to-end feature validation, ensuring robust hardware-software interoperability for high-end hardware and software.
• Conduct code reviews, define engineering procedures, and identify, analyze, and report software defects.
• Drive improvements in performance, quality, and stability for software acceleration solutions, collaborating with R&D.
• Partner with cross-functional teams across multiple engineering organizations worldwide.

Requirements:

• Bachelor's degree in Computer Science, Software Engineering, or a related field (or equivalent experience).
• 3+ years of experience in a managerial or team lead position, with a proven track record of leading engineering teams.
• 8+ years of overall experience in software development or verification, with a strong technical background.
• Expertise in Python, particularly in testing complex embedded systems or firmware-integrated environments.
• Strong verification skills with experience in developing modern software testing and QA automation frameworks.
• Knowledge of networking and compute infrastructure (servers, switches, routers, TCP/UDP).
• Familiarity with Linux distributions (CentOS/RedHat, Ubuntu) and experience in software debugging and problem-solving.
• Understanding of how to optimize environments for performance and deploy infrastructure based on innovative technologies and high-end hardware.

Preferred Qualifications:

• Experience with PyTest or other modern Python testing tools.
• Proficiency with data search and analytics engines (Elasticsearch, Kibana, Grafana).
• Hands-on experience with virtualization in Linux (QEMU/KVM).
• Background in CI/CD methodologies, infrastructure, and toolsets (Jenkins, Git).
• Knowledge of Docker, Kubernetes, and understanding of C/C++ toolchain in Linux.

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We're looking for a Product Marketing Manager to turn Weavy's innovation into clear, compelling stories that drive activation and growth.

What you'll do at Figma Weave:

• Plan and execute launches for new features, models, and workflows
• Own the full top funnel from visit to subscription; track conversion, optimize the user journey, and improve both B2C and B2B funnels
• Build and optimize in-product and email communications
• Maintain Figma Weave's product narrative and ensure consistency across web, app, social, and PR materials
• Create case studies, success stories, and internal enablement docs; support partner and affiliate initiatives
• Partner with growth and product to measure funnel performance, activation rates, and adoption; translate insights into action

Requirements:

• 6+ years of relevant experience for PLG-driven products, ideally in creative tech, AI tools, or design platforms
• Experience building and executing GTM plans
• Exceptional storytelling skills
• Hands-on, data-driven mindset
• Collaborative and curious nature

Nice to have:

• Familiarity with affiliate, referral, or partner-led growth loops
• Comfort using AI and analytics tools for messaging, data analysis, or workflow automation

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In this role, you'll work directly with engineering teams, researchers, and technical leaders from enterprise healthcare organizations, biotech companies, start-ups, and research institutions.

You will help them compose, build, and deploy accelerated AI solutions using NVIDIA platforms.

Responsibilities:

• Serve as a trusted technical advisor to the healthcare and life sciences ecosystem.
• Partner with ecosystem developers to integrate NVIDIA specialized platforms, including NVIDIA Clara, BioNeMo, and Parabricks.
• Map, build, and expand a rich ecosystem of strategic healthcare partners and developers.
• Work closely with partner engineering teams, technical leaders, and decision-makers to unpack goals and tackle complex technical challenges.
• Advocate for the healthcare developer's technical needs and funnel feedback to NVIDIA's product and engineering teams.

Requirements:

• BS/MS/PhD in Computer Science, Bioinformatics, Computational Biology, Biomedical Engineering, or an AI-related field or equivalent experience.
• 5+ years of overall industry experience in software engineering, developer relations, or technical partnerships, including 2+ years of hands-on experience applying AI/ML to healthcare, life sciences, or genomics.
• Proven experience leading technical partnerships and ecosystem engagement.
• Excellent interpersonal skills enable you to connect complex life science concepts with AI engineering.

Nice to Have:

• Deep familiarity with NVIDIA's healthcare platforms, including BioNeMo, Clara, and/or Parabricks.
• Experience driving developer adoption or leading technical teamworks within biotech, digital health, medtech, or pharmaceutical enterprises at scale.
• Hands-on experience with foundational biological models, structural biology tools, or processing massive genomic, clinical, or electronic health record (EHR) datasets.
• A builder attitude with a passion for using technology and community engagement to solve global health, clinical, and biological challenges.

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As a Senior Software Engineer for KAI, you will help build the future of AI scheduling in the Kubernetes ecosystem, working on challenging problems spanning workload scheduling, Kubernetes internals, and large-scale AI infrastructure.

Responsibilities:

• Develop clean, maintainable, and well-tested software in Go.
• Design and implement scalability improvements for KAI, helping it operate efficiently in massive-scale deployments (thousands of nodes) while addressing Kubernetes scaling constraints and bottlenecks.
• Apply strong algorithmic thinking to solve complex AI workload scheduling and placement challenges, balancing performance, fairness, cluster utilization, topology constraints, and scalability.
• Conduct code and design reviews to uphold high-quality standards and mentor team members.
• Work closely with contributors, users, and customers, helping translate feedback from production deployments into product and engineering improvements.
• Collaborate with related upstream projects (schedulers, AI frameworks, cluster autoscalers, Kubernetes SIGs/WGs, etc.) and contribute to community and ecosystem discussions.

Requirements:

• B.Sc. or M.Sc. in Computer Science or a related field or equivalent experience.
• 8+ years of experience in backend software development, including system design and architecture.
• 4+ years of advanced Kubernetes development experience, including designing and implementing CRDs and controllers, with deep expertise in Kubernetes internals, networking, storage, and cluster architecture.
• Strong algorithmic skills with experience tackling complex optimization and distributed systems challenges.
• Strong technical skills and a proven ability to collaborate with and mentor other engineers.

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We're building the next chapter of AI-native craft and creativity - where craft and technology meet. Our unified platform bridges the gap between AI capabilities and human creativity, and lets professional creatives and designers harness the power of the world’s leading AI models without losing precision, expression, or soul.

We're looking for experienced full-stack engineers to join the Figma Weave team. You’ll contribute to our core mission by designing and scaling reliable, secure, and intuitive systems across Figma Weave.

What you’ll do at Figma Weave:

• Design, build, test, and ship high-quality features across the stack, using technologies like TypeScript, React, Ruby, Go, and more
• Own key parts of the product that impact user experience, internal productivity, or revenue operations
• Collaborate with cross-functional partners in product, design, data science, support, and sales to shape product direction and solve complex problems
• Operate and monitor the systems you build, with a strong focus on reliability, security, performance, and user experience
• Contribute to team culture by mentoring peers, providing feedback, and helping foster a collaborative and inclusive engineering environment

We’d Love to Hear From You If You Have:

• 5+ years of professional software engineering experience, with a track record of shipping and maintaining complex systems or products in production
• Full-stack experience with modern front-end frameworks (e.g., React/TypeScript) and back-end technologies (e.g., Ruby, Go, Node.js, PostgreSQL)
• Strong collaboration and communication skills, with experience working effectively across functions

While it’s not required, it’s an added plus if you also have:

• Experience with Rust, WebAssembly, or graphics rendering technologies
• Prior work on extensibility platforms (plugins, APIs, widgets), or experience contributing to open source developer communities
• Passion for crafting excellent developer or user experiences, and an eye for elegant, maintainable architecture
• Enthusiasm for learning and teaching - whether mentoring teammates, leading initiatives, or sharing knowledge in code reviews or pairing sessions

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locationsIsrael, Tel AvivIsrael, Yokneam

time typeFull time

posted onPosted Yesterday

job requisition idJR2018953

NVIDIA is at the forefront of the AI revolution, delivering brand new accelerated compute platforms for global impact. Our Networking Research group is seeking a talented and motivated Software Engineer to spearhead the integration of autonomous AI agents across our internal and external platforms. In this high-impact role, you will architect the backbone for AI agent interaction, design scalable frameworks and SW development platforms. You will be a key player in redefining how our tools and services leverage generative AI. If you are passionate about building the practical infrastructure that brings intelligent agents to life, we want to hear from you.

What you'll be doing:

• Architect and build robust, scalable frameworks and APIs to integrate AI agents with NVIDIA's suite of developer tools, simulation platforms, and enterprise software.

• Collaborate with research, applied AI, and product teams to understand agent capabilities and translate them into production-ready services and features.

• Design and implement CI/CD pipelines and MLOps for the AI agent and SW simulation products, including testing, deployment, monitoring, and continuous improvement.

• Optimize the performance, latency, and resource consumption of deployed AI agents, ensuring they operate efficiently within our compute infrastructure.

• Develop internal tooling and automation to streamline the onboarding of new AI agents and enhance the observability of agent fleets.

• Champion guidelines for secure and reliable agent-based systems, including data handling, access control, and interaction protocols.

• Serve as a key technical resource for solving sophisticated integration issues between AI agents and target applications.

What we need to see:

• BSc or above in Computer Science, Computer Engineering, or a related field, or equivalent experience.

• 3+ years of hands-on experience in software engineering, with a focus on backend systems, cloud services, or infrastructure.

• Proven experience with AI/ML frameworks (e.g., PyTorch, TensorFlow) and a strong understanding of large language models (LLMs), transformers, and agent-based architectures (e.g., LangChain, LlamaIndex).

• Proven experience in architecting, building and deploying complex integrations between AI agents and external tools, APIs, or software services.

• Expert-level programming skills in Python. Experience with C++ is a strong plus.

• Experience designing, building, and maintaining RESTful APIs, gRPC, and other service-to-service communication protocols.

• Excellent problem-solving skills and the ability to navigate complex, ambiguous technical challenges.

• Strong communication and interpersonal skills, with a proven ability to collaborate effectively across multidisciplinary teams.

Ways to stand out from the crowd:

• Hands-on experience building or fine-tuning LLMs or other generative models.

• Prior experience with MLOPs, and agentic infrastructure.

• Contributions to open-source AI/ML projects. Experience with Infrastructure as Code (Terraform, Ansible). Prior experience in developing platforms for internal developer communities.

• Knowledge of cloud platforms (AWS, GCP, Azure), container orchestration (Kubernetes, Docker), and building scalable microservices.

• Familiarity with vector databases (e.g., Milvus, Pinecone) and model serving infrastructure (e.g., Triton Inference Server).

NVIDIA is home to some of the most innovative and dedicated professionals in the industry. We are committed to fostering a diverse work environment and are proud to be an equal-opportunity employer.

NVIDIA pioneered accelerated computing. Today, our AI infrastructure powers global intelligence, transforming every industry.

Learn more about NVIDIA.

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You will model the performance of complex AI workloads to identify bottlenecks and recommend system-level optimizations. You will analyze brand-new AI models, distributed training techniques, and inference workloads to understand their infrastructure requirements.

You will build platforms, simulations, and HW platforms, execute AI workloads, and build analytical tools to evaluate trade-offs across compute, memory, storage, and network behavior. You will translate research insights and workload behavior into actionable software, hardware, and networking architecture requirements.

You will partner with architecture, software, and product teams to influence future NVIDIA networking and AI infrastructure roadmaps. You will drive architectural innovation by applying deep workload analysis to real-world advanced machine learning frameworks.

Requirements:

• B.Sc. Or M.Sc. in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience.

• 3+ years of relevant industry or research experience.

• Strong machine learning or data science background, with hands-on experience in LLMs, generative AI, or deep learning systems.

• Strong systems-level thinking, capable of estimating end-to-end requirements across the AI stack.

• Shown ability to translate research findings and product requirements into clear software and hardware specifications.

• Excellent research skills, including the ability to digest academic papers, self-learn new domains, and independently test hypotheses.

• Advanced programming skills for performance modeling, data analysis, and prototyping.

• Excellent communication skills, demonstrating proficiency in presenting complex technical findings clearly and confidently.

Nice to Have:

• Experience with distributed training, distributed inference, or large-scale AI serving systems.

• Experience in Agentic programming, and AI tools

• Familiarity with GPU clusters, collective communication, storage systems, or AI networking bottlenecks.

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As a Chip Design Engineer at NVIDIA's Networking business unit, you'll join a group of engineers to design and implement the next generation state-of-the-art Switch Silicon chips.

In this position, you'll develop high-speed communication devices, delivering the highest throughput and lowest latency.

Responsibilities:

• Work in a design/verification team which develops core units within the Switch silicon.
• Micro-architecture of rtl verification environments planning for units and modules.
• Design RTL of units/blocks according to Arch. specifications under challenging constraints with high orientation to power, area, and performance.
• RTL synthesis, timing, supporting verification, and silicon post TO activities.
• Work closely with multiple teams within organisations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.

Requirements:

• Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience.
• 5+ years of experience in RTL design.
• Knowledge in network protocols and/or HPC and distributed calculations - advantage.
• A team player with good communication and interpersonal skills.

NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us.

If you're creative and autonomous, and love the challenge of crafting the highest performance & lowest power silicon possible, we want to hear from you.

Come, join our Switch Silicon design team and help us build the next chip in this exciting and quickly growing field.

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Key Responsibilities:

• Thoroughly understand our networking solutions across all performance related aspects
• Develop a C++ simulation model to define and evaluate architectural options for our next generation of networking products
• Understand different trade-offs related to solving performance bottlenecks
• Collaborate and lead technical solutions within architecture, research, hardware, and software teams
• Analyze and model the communication patterns of key DL, GAI, inference, and training applications
• Explore innovative ideas to improve and optimize our chip systems performance

Requirements:

• BSc/MSc in Computer Science, Electrical Engineering, from a known university
• Excellent verbal and written communication skills
• High level of ownership and the ability to drive solutions and initiatives
• Proficiency in C++ and Python
• 3+ years of hands-on experience
• Strong debug skills

Nice to Have:

• Master's degree in Electrical Engineering, Computer Science or related technical field
• Demonstrated ability to innovate and lead new technologies leading to product impact
• Experience with NVLink/Ethernet/IB technologies

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In this position, you'll work in a dynamic verification environment, planning for units, infrastructures, and system-level verification. You'll also work closely with multiple teams within the organisation, including Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.

Your responsibilities will include driving the FullChip verification execution, including staging plans of projects and deliveries.

We're looking for an electrical engineering graduate with 2+ years of experience in dynamic verification. Knowledge of network protocols and/or HPC and distributed calculations is an advantage.

As a team player with good communication and interpersonal skills, you'll fit right in with our collaborative and fast-paced environment.

If you're creative and autonomous, and love the challenge of crafting the highest performance & lowest power silicon possible, we want to hear from you. Come, join our Switch Silicon design team and help us build the next chip in this exciting and quickly growing field.

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In this position, you will research and develop techniques to GPU accelerate workloads in deep learning, machine learning or other AI domains. You will work directly with other technical experts in their fields (industry and academia) to perform in-depth analysis and optimization of complex AI and HPC algorithms to ensure optimal AI solutions on modern CPU and GPU architectures. You will publish and/or present discovered optimization techniques in developer blogs or relevant conferences to engage and educate the developer community. You will influence the design of next-generation hardware architectures, software, and programming models in collaboration with research, hardware, system software, libraries, and tools teams at NVIDIA.

To succeed in this role, you will need:

• An advanced degree in Computer Science, Computer Engineering, or related computationally focused science degree (or equivalent experience)
• 8+ years of relevant experience in software development or research work
• Programming fluency in C/C++ with a deep understanding of algorithms and software development
• A background that includes parallel programming, e.g., CUDA, OpenACC, OpenMP, MPI, pthreads, etc.
• Hands on experience doing low-level performance optimizations
• In-depth expertise with CPU and GPU architecture fundamentals
• Effective communication and organization skills, with a logical approach to problem solving, good time management, and prioritization skills

If you have expertise in parallelization and performance optimization of Deep Learning models arising from Natural Language Processing, Computer Vision, Recommender Systems, etc., and excellent understanding of linear algebra, you will stand out from the crowd.

NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Are you a creative and autonomous computer scientist with a genuine passion for parallel computing? If so, we want to hear from you. Come, join our AI Compute DevTech team and help build the real-time, cost-effective computing platform driving our success in this exciting and quickly growing field.

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Responsibilities:

• Develop cycle-accurate simulation components to evaluate and analyze micro-architecture and architectural options for our next generation of switches.
• Learn and understand the switch ASIC across all performance related aspects
• Focus on switch hardware modeling.
• Analyze and model the communication patterns of key DL, GAI inference and training applications.
• Explore innovative ideas to improve and optimize our chip systems performance.

Requirements:

• BSc/MSc in Electrical Engineering, Computer Science from a known university.
• Experience in developing simulation models.
• 2+ years of experience in C++ and Python.
• Strong debug skills.
• Excellent verbal and written communication skills.

Nice to Have:

• Master's degree in Electrical Engineering, Computer Science or related technical field.
• 5+ years of relevant practical experience.
• Experience with network simulation tools (omnet, ns3, sst, gem5)
• Demonstrated ability to innovate and lead new technologies leading to product impact.
• Experience with NVLink/Ethernet/IB technologies.

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Key responsibilities include:

• Delivering networking features and their verification aspects
• Defining, developing, and maintaining verification infrastructure and regression test suites
• Working with continuous integration system, regression tools, automating builds, running test suites, and analyzing results

Requirements include:

• B.Sc. in Computer Science, Computer Engineering, Electrical Engineering, or Communication Engineering
• 5+ years of relevant experience working with established brands
• Experience with verification and automation
• Programming knowledge in C and C++, object-oriented OOP
• Knowledge in Linux

Preferred qualifications include:

• Background with C/C++ as well as Git
• Experience with Python
• Experience with networking applications and protocols
• Background with CI methodology & tools (Gerrit, Jenkins, etc.)

If you are a creative and autonomous engineer who loves a challenge, come and be part of the best chip design team in the industry!

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We are looking for a best-in-class Chip Design Engineer to join our team. You will have a B.SC./M.SC. or equivalent experience in Electrical Engineering/Communication Engineering/Computer Engineering and 5+ years of proven experience in RTL Frontend ASIC Verification (Chip Design).

As a Senior Chip Design Verification Engineer, you will be responsible for:

• Joining the Tel Aviv or Beer-Sheva group, working on RiscV processors platform.
• Verification for chip blocks according to specifications under challenging constraints and with high orientation to power, area, and performance.
• Daily work might involve any or all aspects of chip development including verification, integration, debug...
• Work closely with firmware and other groups around the globe.

To succeed in this role, you will need:

• B.SC./M.SC. or equivalent experience in Electrical Engineering/Communication Engineering/Computer Engineering.
• 5+ years of proven experience in RTL Frontend ASIC Verification (Chip Design).
• High Level of English.

If you have extensive experience in RTL Frontend ASIC Verification (Chip Design), strong experience and knowledge in Specman, and a vast background and knowledge in system-level aspects, you will stand out from the crowd.

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The ideal candidate will have a B.SC./M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience, with 5+ years of experience in Physical Design. You should be familiar with physical design flows and methodologies, including PNR, STA, and physical verification. Experience with physical design EDA tools such as Synopsys and Cadence is also required.

As a great teammate, you will take part in flows development and be exposed to a variety of challenging designs, including high cell count and HS blocks. You will resolve complex timing and congestion problems, and contribute to the development of our groundbreaking and innovative chips.

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To succeed in this role, you will need 3+ years of experience in RTL design verification, a B.Sc. in Electrical Engineering or Computer Engineering, and excellent communication and interpersonal skills. A background in Specman and System-Verilog UVM is also desirable, as is knowledge in Networking.

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Your daily work will involve all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification. You will also take part in flow development and act as Partition/Unit level physical design technical leader and focal point.

To succeed in this role, you will need a B.SC./M.SC. in Electrical Engineering/Computer Engineering, 5+ years of experience in physical design, proven experience in RTL2GDS flows and methodologies, knowledge in physical design flows and methodologies (PNR, STA, physical verification), familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.), and great teamwork skills.

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Responsibilities

• Design & Implement: Architect and develop high-performance diagnostic tools and frameworks using Python, tailored for NVIDIA's latest networking platforms.
• Performance Optimization: Drive end-to-end development focusing on software that performs efficiently, ensuring diagnostic suites can handle high-throughput data and real-time monitoring without latency.
• System Diagnostics: Take charge of developing features that bridge the gap between complex hardware behaviors and software-level diagnostics.
• Collaborative Problem Solving: Partner with hardware, firmware, and driver teams to address real-world challenges that demand innovative solutions and a customer-centric approach.
• Autonomous Execution: Own the full software development lifecycle of diagnostic features, from initial hardware specification to deployment in dynamic environments.

Requirements

• B.Sc or equivalent experience in Computer Engineering, Computer Science, Electrical Engineering, or a related field.
• 5+ years of hands-on experience in the software development lifecycle, with a proven track record in performance-critical systems.
• Python Mastery: Advanced programming skills in Python, with a focus on writing optimized, efficient, and scalable code for hardware interfacing.
• Networking & HW Background: Solid understanding of networking protocols (TCP/IP, InfiniBand, or Ethernet) and hardware-level interaction.
• Linux Expertise: Strong familiarity with Linux environments, associated debugging tools, and system-level performance tuning.
• Strong analytical and debugging skills.

Nice to Have

• Performance Tooling: Experience with performance profiling, optimization, and low-level hardware communication (e.g., PCIe, I2C).
• Low-Level Knowledge: Background in C/C++, RT embedded development, or driver development within a Linux environment.
• Technical Leadership: Experience leading technical projects or mentoring team members in a dynamic setting.
• Problem Solving: Confirmed experience in root-causing complex system-level issues and solving customer-facing hardware challenges.

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The NVIDIA System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.

Responsibilities: Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design). Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues. Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks. Taking part in flows development and deployment.

Requirements: B.SC./ M.SC. in Electrical Engineering/Computer Engineering. 7+ years of actual design experience in chip design. Solid hands-on RTL design skills in System-Verilog. Proficiency in at least one scripting languages like python, bash, tcl. Great teammate.

Benefits: Passion for quality. Experience with delivery to physical design, emulation, firmware and other customers.

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As a member of this team, you will design, develop, optimize and maintain APIs, tools and libraries for Switching, Routing, Analytics, Telemetry and more. You will collaborate with team members, Architects, QA teams, and customers to innovate and rapidly develop POC prototypes that can then be developed into full-fledged products/solutions.

To succeed in this role, you will need a B.Sc in Software Engineering / Computer Science / related field, 2+ years of experience in C Programming, strong analytical skills, knowledge of algorithms and proficient with data structures. Previous experience with Ethernet Switching or Routing protocols, hands-on Linux development, user-space and/or kernel-space are also desirable.

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We are looking for a Senior QA Software Engineer who combines network protocol expertise with strong Python automation skills. Does debugging a BGP EVPN route leak excite you as much as refactoring a test framework? Then we should talk!

Responsibilities

We don't just complete checklists; we collaborate closely with R&D to lead the quality of new features from design to deployment. In this role, we:

• Review architectural designs and requirements for new features introduced to the product
• Drive the design, development, and execution of tests across functional, performance, and security scopes as part of SW GA and update releases
• Develop Python automation suites built on clean OOP principles
• Chase down defects and validate fixes until we fully resolve the root cause
• Leverage the SimX platform to validate code and debug the ASIC long before hardware arrives

Requirements

• Combined network engineering depth with thorough software habits
• 5+ years of hands-on QA or networking experience, backed by CCNP-equivalent protocol knowledge: L2 (VLAN, STP), L3 (BGP, OSPF), EVPN, VXLAN, and advanced features like PFC, ECN, RoCE, and QoS
• Production-quality Python engineering,specifically, strong OOP design and hands-on experience with Pytest
• Deep Linux proficiency (at an LPIC-1 or LPIC-2 level) to navigate system internals, analyze logs, and debug effectively
• Clear verbal and written communication, with professional proficiency in written and spoken English
• B.Sc. or B.A. or equivalent experience in Computer Science, Electrical Engineering, or a similar background

Ways to stand out from the crowd

• Experience with Docker and traffic generation tools (Ixia, TRex, Scapy)
• Hands-on experience integrating tests into CI/CD pipelines (Jenkins, GitLab CI)
• Working knowledge of virtualization platforms (KVM, VMware)

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We are looking for an experienced DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.

Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you.

As a DFT ATPG Engineer, you will be in charge of state of the art Design for Test/ATPG flows and implementation. You will take full ATPG ownership end to end on a project, from Arch & planning to pattern generation, verification and post Silicon bring up and diagnosis. You will also invent and maintain automation flows that provide the short test time to production.

To succeed in this role, you will need to have 3+ years of hands on DFT/ATPG experience knowledge & technical experience in DFT ASIC Design and in ATPG tools. You will also need strong programming skills in scripting languages, a BSc. in Electrical Engineering or Computer engineering, and be a quick learner, proactive and self-motivated, eager to learn and contribute, sense of ownership, commitment, and responsibility.

Knowledge of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation is also required. Experience in Mentor TestKompress ATPG tool and retargeting flow is a plus. Programming languages such as TCL, PRL, Phyton & Unix shell scripts are also necessary. Experience with ATE and Silicon bring-up is highly valued.

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Enhance NVIDIA's GPU Networking offerings for accelerating AI workloads, such as NVIDIA Dynamo, NVIDIA NIXL and NVIDIA UCX, tailored to the unique requirements of AI workloads.

Co-design hardware features (e.g., in GPUs, DPUs, or interconnects) that accelerate data movement and enable new capabilities for inference and model serving.

Identify and evaluate new technologies, innovations and partner relationships for alignment with our technology roadmap and business value.

Lead architecture and design of new technologies and innovations such as runtime systems, communication libraries, AI-specific technologies.

Lead proof-of-concept development to evaluate and drive such technologies.

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This position offers the opportunity to have a real impact in an applied research-focused team in a dynamic company. The Applied AI Architecture group focuses on applied research. As a member of the team, you will publish your work and share code as an open source. In addition, you will join a groundbreaking initiative at the intersection of AI and biology. This collaborative project aims to develop both foundational and generative AI models, as well as agentic AI systems, redefining our understanding of complex biological systems and enabling advanced diagnostics and novel scientific insights, while strengthening NVIDIA’s Health Platform ecosystem.

Responsibilities:

• Conceptualize, design, and implement novel deep learning architectures for biological data, with a strong focus on large-scale models such as Large Language Models (LLMs), Transformers, and State Space Models (SSMs).

• Develop multimodal learning systems that integrate heterogeneous data types (e.g., clinical time-series, imaging, genomics, and text) for improved representation and prediction.

• Develop both foundational and generative models and agentic AI systems, including multi-step reasoning, tool use, and autonomous decision-making capabilities.

• Develop digital twin systems for healthcare, combining mechanistic models, physiological data, and AI to simulate disease progression, treatment response, and patient-specific trajectories.

• Implement deep learning systems integrated with agents, enabling end-to-end workflows that combine learning, planning, and execution.

• Evaluate model performance, analyze results, and iterate on designs to achieve optimal outcomes.

• Apply your knowledge of distributed training to build high-quality code for training, optimizing, and deploying large-scale models, while managing complex datasets.

• Collaborate closely with a diverse team of researchers, bioinformaticians, and domain experts in a highly interdisciplinary environment.

Requirements:

We are looking for individuals who demonstrate a strong foundation in deep learning and a proven ability to translate innovative ideas into practical, scalable systems.

• PhD in Machine Learning, Computer Science, Engineering, or a related discipline.

• 8+ years of hands-on experience in developing, training, and deploying deep learning models at scale, including LLMs, Transformers, SSMs, and/or generative models.

• Experience with multimodal learning and integrating diverse data modalities is highly valued.

• Experience with agentic AI frameworks or systems (e.g., tool-augmented models, planning-based agents, or multi-agent systems) is a strong advantage.

• Strong expertise in distributed training, optimization, and inference.

• Proven ability to lead independent research, implement robust solutions, and rigorously evaluate performance.

• Track record of publications and presentations at top conferences.

• Strong programming skills in Python and C++, with experience in PyTorch and/or CUDA.

• Excellent communication skills and ability to thrive in a dynamic, research-driven team. Mentoring experience is a plus.

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As a Senior Software Engineer at NVIDIA, you will be part of a group of firmware verification engineers, using your expertise in C++ and Python in an Agile methodology.

Develop the verification process, aligning with quality standards and project timelines.

Design and implement new features in the core of NVIDIA Switch and GPUs

Drive and facilitate the planning, scheduling, and execution of the project and activities of the team

Collaborate with architecture and different software design teams as part of the software development lifecycle.

Work in pre and post-silicon development environments of next-generation NVIDIA networking products.

Gain a deep understanding of networking technology, system debugging and stacks, as well as the HW/FW/SW relationship.

Innovate! Bring NVIDIA's FW switching products to shine in customer's view

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Your primary responsibilities will include:

• Verifying chip blocks/entities according to specifications
• Integrating and creating Full-Chip models
• Collaborating with organisation-wide groups

To succeed in this role, you'll need:

• A Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or Communication Engineering
• At least two years of experience in verification or a similar position
• A high level of English proficiency
• Excellent teamwork skills

To stand out from the crowd, you'll have:

• Validated experience in Verification
• Experience with Specman
• Background in UVM/SV
• Knowledge of HDL (Verilog/VHDL)

If you're passionate about verification and want to be part of a dynamic team, apply now!

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In this position, you'll work in a dynamic verification environment, planning for units infrastructures and system level. You'll work closely with multiple teams within organisations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.

Your responsibilities will include driving the FullChip verification execution, including staging plans of projects and deliveries.

To succeed in this role, you'll need an Electrical Engineering B.Sc. or Computer Engineering B.Sc. degree with high scores or equivalent experience. You'll also require 8+ years of experience in dynamic verification, knowledge of network protocols and/or HPC and distributed calculations, and strong communication and interpersonal skills.

If you're a team player with a passion for crafting high-performance and low-power silicon, we want to hear from you. Join our Switch Silicon design team and help us build the next chip in this exciting field.

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Joining NVIDIA means being part of a team renowned for its inventions, such as NVIDIA Cosmos, Llama-Nemotron, Sana, and contributing to impactful work that influences various applications. We offer a collaborative environment that fosters professional growth. You will have the opportunity to collaborate with some of the brightest minds in the field, both within NVIDIA's global network and with leading companies worldwide, making this role perfect for those passionate about advancing AI technology and eager to make a significant impact on the future of the field.

Responsibilities:

• Invent and build ground-breaking techniques for efficient multi-modality model creation and publish the findings in leading journals and conferences.
• Combine traditional diffusion technologies with the latest and greatest LLMs.
• Contribute to NVIDIA's AI enterprise software to ensure robust and scalable solutions.
• Collaborate with internal and external teams worldwide to drive research and development in multi-modal learning, using different professions and resources across the company.
• Partner with leading scientific organizations and industry pioneers to remain at the forefront of technological advancements and integrate the latest innovations into practical applications.

Requirements:

• PhD. in Computer Science, Electrical Engineering, or a closely related field, or equivalent experience.
• At least 3 years of relevant research experience
• Publications in prestigious conferences and journals like NeurIPS, ICLR, and CVPR
• In-depth understanding and active research experience in leading generative AI techniques, with a track record of contributing to advancements in this area
• Extensive experience in image and video understanding, generation, and reasoning.

Ways to stand out from the crowd:

• High proficiency in programming and coding
• Degree from a top-tier institution or equivalent experience in a world-class industrial research group
• Substantial contributions to the multi-modality or diffusion forefront of research.
• Experience in research fields of LLMs.

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