Responsibilities

• Designing and developing power-efficient memory PHY architectures.
• Driving the creation and optimization of effective power models for memory subsystems.
• Taking responsibility for project outcomes and ensuring high-quality deliverables.
• Utilizing tools such as Power Artist and PTPX for power analysis and optimization.
• Collaborating closely with large cross-functional teams,including engineering, product management, and customers,to align requirements and integration.
• Mentoring engineers and sharing best practices.
• Evaluating new technologies or architectural improvements.
• Supporting IP integration and validation efforts.

The Impact You Will Have

• Advance Synopsys’ leadership in memory PHY innovation.
• Drive efficient power modeling practices that enhance product performance and competitiveness.
• Take ownership of outcomes, ensuring projects meet and exceed expectations.
• Shape future technology and product direction.
• Support robust, scalable architectures.
• Foster a collaborative and inclusive team culture across large, multidisciplinary groups.
• Deliver solutions trusted by leading semiconductor companies.

Requirements

• 15+ years in memory PHY architecture and power modeling.
• Expertise with industry-standard design and simulation tools, including Power Artist and PTPX.
• Proven experience driving efficient power models and taking responsibility for outcomes.
• BSEE/MSEE required.
• Strong analytical and communication skills.
• Strong digital and/or analog design skills.
• Ability to work effectively with large cross-functional teams.

Benefits

• Comprehensive health, wellness, and financial benefits.
• Annual bonus, equity, and other discretionary bonuses.
• ESPP: Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
• Retirement plans that vary by region and country.

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As a graduate, you'll dive into projects that align with strategic focus areas such as AI transformation, employee experience, skills development, or business impact and consulting. Your responsibilities will include:

• Learning about each participating HR team's operations and contributing to day-to-day work
• Completing project work aligned with the rotation's strategic focus area
• Gathering information, reviewing data, and documenting observations to inform decisions
• Researching, developing, or improving resources, processes, tools, and solutions
• Collaborating with team members and stakeholders, applying feedback, and adapting to changing priorities
• Sharing progress, key learnings, and recommendations through regular check-ins and a capstone presentation

To succeed in this role, you'll need:

• A bachelor's or master's degree in Human Resources, Business Administration, Industrial-Organizational Psychology, Organizational Psychology, or a related field
• Demonstrated experience using AI tools to support research, analysis, productivity, process improvement, or employee-focused solutions
• Strong analytical, communication, and problem-solving skills
• Curiosity, adaptability, and a willingness to learn across HR functions and program focus areas
• Ability to take ownership of projects, set goals and success measures, manage milestones, and deliver high-quality outcomes
• Strong collaboration and stakeholder-management skills

Key Program Facts

• Program Length: 24 months with 4 planned rotations across HR functions
• Location: Sunnyvale, California
• Working Model: Hybrid (In-Office 3 days per week)
• Full-Time/Part-Time: Full-time, permanent position
• Start Date: January 2027

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You have spent years deep in the hardware verification world, not just running tools but understanding why designs fail at bring-up and what it takes to get a prototype stable enough to hand off to software teams. You will work with ZS5, ZeBu-200, and HAPS platforms, and you will help customers see how AI-driven verification changes what is possible.

Responsibilities

• Architect pre-sales and post-sale technical engagements for Emulation (ZS5, ZeBu-200) and HAPS FPGA prototyping platforms, working directly with prospective and existing customers to shape solutions around their design challenges

• Present tailored hardware assisted verification solutions that address customer-specific needs around partitioning, performance, debug, and integration with their existing RTL and validation flows

• Create and deploy Agentic AI agents and skills for hardware assisted verification platforms at customer sites, driving adoption of AI-based support models

• Conduct technical evaluations, proof-of-concept projects, and benchmarks that demonstrate how ZS5, ZeBu-200, and HAPS solve the customer's real problems, not just theoretical capabilities

• Collaborate closely with the sales team to shape opportunity strategy, qualify technical fit, handle objections, and move deals through the pipeline

• Deliver compelling product demonstrations, technical presentations, and architecture reviews to engineering teams and executive stakeholders

• Build and maintain trusted advisor relationships with customer architects and engineering leaders that extend beyond individual sales cycles

The Impact You Will Have

• Your technical credibility and solution design will directly win competitive deals, growing ZS5, ZeBu-200, and HAPS revenue and expanding Synopsys footprint in strategic accounts

• Proof-of-concept work you lead will de-risk customer decisions and shorten sales cycles by proving value early and clearly

• Solutions you architect will set customers up for long-term success, reducing post-sale friction and creating expansion opportunities across their design teams

• Customer insights you bring back will shape product roadmap priorities and help R&D build features that win in the field

• Relationships you establish with key technical buyers will open doors for the sales team and create multi-year partnership opportunities

• Technical content and competitive positioning you develop will strengthen the entire field team's ability to sell HAPS and Emulation platforms effectively

• Your ability to translate complex prototyping challenges into clear business value will elevate how customers perceive Synopsys technical leadership

Requirements

• Bachelor's or Master's in Electronics Engineering, Computer Engineering, or related field

• 15+ years of hands-on experience in Emulation, FPGA-based prototyping, ASIC design, or SoC validation, with deep understanding of RTL-to-hardware workflows and design challenges

• Strong command of FPGA architectures (Xilinx, Intel, or similar), RTL design in Verilog or VHDL, synthesis flows, and hardware bring-up and debug

• Comfort with travel to customer sites for evaluations, presentations, and technical engagements

• Experience with ZS5, ZeBu-200, HAPS platforms, ProtoCompiler, or similar FPGA prototyping tools is a strong plus

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You have spent years in the trenches of ASIC design, and you know that the cleanest RTL and the best synthesis settings mean nothing if the customer cannot actually use them. You have debugged enough late-stage timing failures to recognize the synthesis decision that caused it three weeks earlier, and you care enough to prevent that from happening again.

Responsibilities

• Own technical relationships with customer RTL, synthesis, formal verification, and physical design teams from flow evaluation through tapeout, serving as their trusted technical partner for Synopsys synthesis and equivalence checking products
• Debug complex synthesis and Formality issues reported by customers, reproduce problems in your own environment when possible, isolate root causes, and deliver clear recommendations or escalate to R&D with well-documented test cases
• Guide customers on RTL-to-netlist methodology using Fusion Compiler, Design Compiler, RTL Architect, and Formality, including advice on hierarchy, datapath optimization, physical-aware synthesis, clock gating, multi-bit registers, and handoff to place-and-route
• Analyze synthesis results, timing reports, constraint files, library characterization, and PPA outcomes to explain design behavior, identify optimization opportunities, and improve correlation with downstream implementation
• Create and maintain reusable scripts, reference flows, application notes, debug guides, and training materials that scale across customer programs and can be shared with global applications teams
• Translate recurring customer challenges and feature requests into clear use cases and product feedback for Synopsys R&D, and validate fixes and enhancements in real customer contexts
• Support technical evaluations, benchmarks, design reviews, and adoption of new synthesis and formal verification technologies across customer design teams

The Impact You Will Have

• Customers will ship complex SoCs on schedule because you helped them resolve synthesis and equivalence checking issues that would have blocked tapeout
• Design teams will achieve better power, performance, and area outcomes because you identified RTL, constraint, or methodology improvements they could not see on their own
• Synopsys products will become more robust and easier to deploy because you brought field observations back to R&D as reproducible test cases and actionable feature requests
• Customer synthesis flows will scale and stabilize across programs because you built reference methodologies, scripts, and documentation that teams can reuse without starting from scratch
• Engineers at customer sites will trust Synopsys as a technical partner, not just a vendor, because you showed up during the hard problems and helped them solve it
• Your colleagues across global applications, support, and product engineering teams will benefit from the knowledge you share, the materials you create, and the mentorship you provide
• Synopsys will win competitive evaluations and expand deployments because customers see the value you deliver during technical engagements and benchmarks

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent hands-on experience in ASIC design or EDA applications
• 5 or more years of hands-on experience in ASIC or SoC design, logic synthesis, formal equivalence checking, or EDA applications engineering, with at least one production design cycle or tapeout under your belt
• Strong working knowledge of Verilog or SystemVerilog RTL, logic synthesis fundamentals, timing constraints (SDC), standard-cell libraries, and RTL-to-netlist design flows
• Practical experience with formal equivalence checking tools, including the ability to set up comparisons, investigate setup issues, and analyze proof failures or inconclusive results
• Proficiency with Tcl scripting and Linux command-line environments, you can write or modify scripts to automate flow setup, parse reports, and accelerate debug
• Direct experience with Synopsys Design Compiler, Fusion Compiler, RTL Architect, or Formality is a strong plus, as is familiarity with static timing analysis tools like PrimeTime
• Experience with UPF, low-power design, hierarchical SoCs, advanced process nodes, or physical-aware synthesis is valuable but not required

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As a Senior Principal Engineer, you will lead Signal Integrity and Power Integrity investigations and drive resolution of complex design challenges. You will define and execute SI/PI strategies for advanced SerDes products, including package, channel, and 3DIC considerations. You will also develop and maintain SI/PI requirements for PCIe and Ethernet products across chip, package, board, and system levels.

Responsibilities:

• Lead Signal Integrity and Power Integrity investigations and drive resolution of complex design challenges.
• Define and execute SI/PI strategies for advanced SerDes products, including package, channel, and 3DIC considerations.
• Develop and maintain SI/PI requirements for PCIe and Ethernet products across chip, package, board, and system levels.
• Perform channel feasibility analysis, modeling, simulation, and correlation activities.
• Review and sign off SI/PI aspects of SerDes transmitter, receiver, and test chip designs.
• Collaborate with architecture, design, package, and applications engineering teams throughout product development.
• Participate in industry standards activities and apply emerging best practices.
• Support customer engagements and technical debug activities.

Requirements:

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering with at least 15+ years of direct industry experience.
• Proven experience in Signal Integrity and Power Integrity for high-speed SerDes designs.
• Expertise in PCIe and/or Ethernet systems and channel design.
• Strong knowledge of NRZ/PAM4 signaling, S-parameter modeling, and SI simulation methodologies.
• Experience with HFSS, ADS, HSpice, MATLAB, and IBIS-AMI.
• Understanding of package, substrate, and PCB technologies.

Benefits:

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

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Responsibilities

• Engage directly with new and existing customers to understand their signal integrity, power integrity, and advanced packaging challenges, then demonstrate how Synopsys tools solve them in their specific design context
• Run multi-physics simulations using HFSS, SIwave, Q3D, Ansys, Clarity, or similar tools to validate product performance and guide customer evaluations
• Provide technical support and troubleshooting for customers working on 3D IC and advanced packaging designs, helping them set up models, interpret results, and optimize workflows
• Collaborate with product management and R&D teams to feed customer insights back into the roadmap and help prioritize feature development
• Travel to customer sites to conduct onsite evaluations, training sessions, and technical reviews, roughly 25% of the time
• Build and deliver technical presentations, application notes, and proof-of-concept demos that show measurable value in real customer scenarios
• Stay current on signal integrity, power integrity, and thermal analysis trends in advanced packaging and communicate those insights internally and externally

The Impact You Will Have

• You will directly influence whether customers adopt Synopsys tools by showing them how to solve problems they could not solve before
• Your simulations and technical guidance will help customers catch design issues earlier, reducing costly respins and time to market
• The feedback you bring back from the field will shape product priorities and feature development, making the tools better for the next customer
• You will expand Synopsys footprint in advanced packaging by proving value in 3D IC, chiplet, and heterogeneous integration designs
• Your technical credibility will build long-term customer relationships that lead to broader tool adoption and renewals
• You will help customers navigate complex tradeoffs in signal integrity, power delivery, and thermal management, enabling them to ship more reliable products
• The evaluations and demos you run will become case studies and reference designs that accelerate adoption across other accounts

Requirements

• Minimum 2 years of hands-on experience in 3D IC and advanced packaging design or analysis
• Proficiency with at least one of the following: HFSS, SIwave, Q3D, Ansys, or Clarity, with the ability to set up, run, and interpret multi-physics simulations
• Strong working knowledge of signal integrity and power integrity principles, including transmission line effects, crosstalk, PDN analysis, and resonance
• Demonstrated ability to work directly with customers, whether in evaluations, support, or training contexts
• Willingness and ability to travel to customer sites approximately 25% of the time
• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field
• Experience with thermal or electrothermal analysis is a plus and will broaden the range of problems you can help customers solve

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Responsibilities

• Develop and deploy AI-driven solutions for verification, synthesis, constraints, and DFT workflows.
• Architect reusable subsystem reference designs for Synopsys IP.
• Debug and optimize front-end design methodologies and automation flows.
• Drive adoption of best practices across design and verification teams.
• Collaborate with EDA, IP, and customer-facing engineers to solve complex design challenges.
• Mentor engineers through technical leadership and knowledge sharing.

Requirements

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of ASIC, SoC, or IP design and verification experience.
• Expertise in verification, synthesis, timing constraints, DFT, CDC/RDC, or lint methodologies.
• Strong experience with Synopsys tools such as VCS, VC SpyGlass, Fusion Compiler, Design Compiler, and TestMAX.
• Proficient in SystemVerilog, UVM, Tcl, Python, or similar languages.
• Demonstrated technical leadership and influence across cross-functional engineering teams.

Benefits

• Comprehensive medical and healthcare plans
• Time away programs
• Family support
• ESPP
• Retirement plans
• Competitive salaries

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You have spent a decade learning that rolling out a new process across 30,000 people is not about writing the perfect document, it is about understanding why the team in Bangalore does things differently than the team in Munich and finding a way that works for both.

Your responsibilities will include:

• Leading corporate-level engineering transformation programs that change how Synopsys develops, releases, and qualifies software products across global teams
• Defining and rolling out scalable processes for product development, release management, and compliance, working directly with product teams to ensure adoption sticks
• Guiding cross-functional product teams through industry standard compliance requirements, translating regulatory and market needs into executable engineering plans

The base salary range for this position is $189,000-$283,000.

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You will work on Fusion Compiler, the tool that powers physical design for the most advanced chips in the world. The problems are real, the customers are demanding, and what you build will matter.

Responsibilities

• Develop and enhance clock tree synthesis and clock optimization algorithms in Fusion Compiler, focusing on skew balancing, useful skew, buffering strategies, and insertion delay optimization
• Debug timing and clocking issues in customer designs across advanced process nodes (16nm to 5nm), identify root causes, and translate findings into product improvements
• Design and prototype new CTS and post-CTS optimization flows that integrate into customer methodologies and improve quality of results, runtime, and convergence predictability
• Collaborate directly with R&D engineers, Customer Application Engineers, and Account Consultants to understand real-world design challenges and align product direction with customer needs
• Implement and test new features in C++, Python, and Tcl, ensuring correctness, performance, and maintainability across large, complex codebases
• Analyze clock architecture tradeoffs including skew, latency, OCV-aware optimization, and uncertainty to drive better design outcomes across market verticals
• Contribute to continuous improvement of clock quality of results, addressing power, timing closure, and robustness across evolving process technologies

Requirements

• Master's degree in Computer Science, Computer Engineering, Electronics Engineering, Mathematics, or related field with 2+ years of professional experience, or Ph.D. in a related field
• Strong proficiency in C++ for performance-critical algorithm development and systems software
• Experience with clock tree synthesis, static timing analysis, timing closure, or physical synthesis flows in an EDA or semiconductor design context
• Solid understanding of clock architecture concepts including skew, latency, insertion delay, transition, uncertainty, and OCV-aware optimization
• Familiarity with VLSI processes and physical design methodology, including timing, area, power, congestion, and signal integrity tradeoffs
• Working knowledge of Python and Tcl for scripting, automation, and tool integration
• Experience with advanced technology nodes (16nm to 5nm) is a plus, understanding the unique challenges of finFET and gate-all-around processes strengthens your ability to solve real customer problems

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As a Principal Technical Program Manager, you will manage end-to-end IP development programs for tier-one customers, from initial requirements through silicon bring-up, ensuring delivery against committed schedules and specifications.

Your responsibilities will include:

• Managing IP development programs, serving as primary technical and operational point of contact between customers and Synopsys cross-functional teams
• Planning and driving program schedules across standard IP deliveries, custom IP development, and foundry process technology node transitions
• Identifying, tracking, and escalating technical and schedule risks, driving issues to resolution across internal development teams and external customer stakeholders
• Coordinating IP integration activities with customer SoC design teams, ensuring successful acquisition, integration, and silicon validation
• Translating customer SoC requirements into actionable development plans, working with R&D to align IP roadmaps with customer product timelines
• Communicating program status, risks, and dependencies to stakeholders at multiple levels

The impact you will have:

• Enabling customers to meet their SoC tape-out schedules by delivering IP on time and to specification
• Reducing customer integration risk by proactively identifying and resolving technical issues
• Expanding Synopsys IP footprint in customer roadmaps
• Improving cross-functional execution by creating clarity across geographically distributed teams
• Strengthening customer relationships through consistent delivery and technical credibility

To succeed in this role, you will need:

• A Bachelor's degree in Electrical Engineering or equivalent with 10 to 15+ years of relevant experience in program management or technical leadership roles
• Proven track record managing programs in analog and digital SoC design environments
• Deep knowledge of IC manufacturing, process technology, design flow, and sign-off processes
• Understanding of memory and standard cell design
• Experience working directly with customers in a technical or program capacity
• Ability to manage multiple concurrent programs with competing priorities
• Strong technical communication skills

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As part of the Corporate Strategy team, you will:

• Define the company's overall medium/long-term ambitions and strategy through the annual corporate strategic planning process, including analysis of the industry landscape and trends, competitive dynamics, assessment of the company's business portfolio, and identification of business performance improvement opportunities.
• Collaborate with the Corporate Development team in defining proactive, strategy-driven M&A plans and strategic partnerships, driving due diligence on strategic acquisitions, and supporting cross-functional integration planning.
• Lead C-suite level projects to address specific strategic questions/issues/opportunities across businesses and functions, owning the end-to-end work process: framing the question/issue, structuring an approach to address it, developing hypotheses, conducting analyses, and articulating actionable recommendations.
• Partner with Business Units for the development of their respective business strategies, identifying priority initiatives and investments across product/engineering, go-to-market, and operations.
• Work cross-functionally to drive the operationalization of critical cross-unit strategic initiatives from set-up to impact, establishing strategic KPIs and a program management structure.
• Support the CEO, CSO, and other senior executives on strategy-related communications.

Key qualifications:

• Experience in management consulting; experience in investment (e.g., private equity, investment fund, investment banking) is valued but not a prerequisite.
• Strong Excel modeling skills required; due diligence experience is highly valued; financial modeling experience, such as P&L, market model, business case, etc., is valued.
• Knowledge of the Semiconductor or Software industry is valued, but not a prerequisite.
• MBA degree is valued, but not a prerequisite.
• Growth mindset, eager to be stretched and learn.
• Commitment to excellence and attention to detail.
• Motivated to be part of a small, highly dynamic team working on C-Suite level topics in a fast-paced environment.
• Excellent analytical/problem-solving and communication skills to generate insights and articulate an independent point of view backed by data/facts.
• Comfortable working with senior leaders; ability to develop trust-based relationships and drive alignment of different stakeholder groups.
• Intellectual curiosity and creativity combined with hands-on action/results orientation.
• Passion for technology and the transformative potential of AI.

The Corporate Strategy team is based in our headquarters located in Sunnyvale (Bay Area, California). Due to the nature of this role, 5 days per week of in-person presence is expected.

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Key Responsibilities:

• Own and strategically manage complex calendars across multiple time zones, proactively resolving conflicts, protecting focus time, and making real-time decisions aligned to business priorities.
• Make all travel arrangements.
• Proactively develop positive working relationships with key partners and vendors, as well as across internal departments.
• Act as a gatekeeper and partner, ensuring leaders spend time on the highest-impact priorities.
• Collaborate with other assistants to organize and execute team activities.
• Handle expense reports and reconciliation.
• Work closely with other assistants on collaborative company-wide projects and initiatives.

Qualifications:

• 2+ years of experience providing administrative assistance.
• Ability to prioritize and handle multiple assignments at any given time.
• Light project management and event planning experience.
• Demonstrated ability to make decisions independently with limited context.
• Strong business judgment and the confidence to push back when needed.
• Experience supporting leaders in fast-paced, high-growth or technical environments.
• Impeccable attention to detail.
• Highly motivated, organized individual who is able to work effectively with minimal supervision.

The base salary range for this role is $108,000 to $143,000. The starting salary will be determined by job-related knowledge, skills, experience, and the market location. We offer a comprehensive benefits program, including medical, dental, and vision insurance, company-paid life insurance, short and long-term disability insurance, flexible spending account, health savings account, tuition reimbursement, and more.

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Responsibilities

• Analyze requirements and design robust software architecture.

• Lead, mentor, and manage a team of developers and architects.

• Create data models, flowcharts, and optimize applications.

• Oversee software launches and ensure project success.

• Coordinate with cross-functional engineering teams.

• Troubleshoot and improve development processes.

The Impact You Will Have

• Drive innovation in memory development and EDA software.

• Enhance performance and reliability of key Synopsys tools.

• Provide strategic leadership and mentorship to your team.

• Influence project direction and technology adoption.

• Improve workflows and ensure secure, high-quality deliverables.

Requirements

• Minimum 15 years of software development and leadership experience.

• Excellent C/C++ programming and engineering skills.

• Strong algorithm/data structure design expertise.

• SQL/database proficiency; Linux platform experience.

• Ability to manage, mentor, and motivate technical teams.

• BS/MS in Computer Science or equivalent.

• Experience with cloud platforms, such as AWS, Google Cloud or Azure is a plus

• Experience with spice simulation & cell/logic characterization is a plus

Benefits

• Comprehensive health, wellness, and financial benefits.

• Annual bonus, equity, and other discretionary bonuses.

• ESPP: Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.

• Retirement plans that vary by region and country.

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Responsibilities:

• Drive end-to-end technical program management for HAV platforms
• Partner closely with Product Management to translate MRDs and PRDs into executable program plans
• Collaborate with account and field teams, product engineering teams, and internal stakeholders to align execution with customer engagements
• Drive cross-functional core teams across hardware and software engineering, Manufacturing Operations, and go-to-market teams
• Own program planning, dependency management, risk mitigation, and execution tracking
• Drive release readiness across hardware, software, licensing, documentation, and enablement
• Continuously improve execution rigor, scalability, and operational excellence across HAV programs

The Impact You Will Have:

• Enabling predictable, high-quality execution of the HAV roadmap
• Improving customer satisfaction through disciplined delivery and alignment to market and customer needs
• Accelerating time-to-market for next-generation HAV platforms and solutions
• Strengthening cross-functional execution and accountability across the HAV organization
• Ensuring Synopsys HAV portfolio meets market needs, cost targets, quality, and time-to-market objectives

Requirements:

• 15+ years of experience in product and/or program management
• Strong understanding of hardware/software flows, ideally with experience in emulation, prototyping, or complex HW/SW systems
• Proven experience driving large, cross-functional programs with hardware and software components
• Demonstrated ability to deliver complex programs on time and with high quality
• BS in EE, CS, CE, or related field; MS preferred
• Excellent communication, organization, and stakeholder-management skills

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As a Senior Product Engineer, you will engineer the future of timing signoff for designs that power everything from data centers to mobile devices. You have spent years in the trenches of timing signoff and understand the difference between a clean sign-off and one that comes back to haunt you three weeks before tapeout.

Your responsibilities will include:

• Driving production deployment of PrimeTime capabilities, including HyperGrid distributed STA, native IR-aware timing analysis, and thermal-aware signoff
• Leading direct technical engagements with design teams at leading-edge accounts, translating their advanced-node challenges into concrete product requirements
• Partnering with R&D teams to evaluate new architectures, validating functionality, and identifying performance bottlenecks
• Owning beta programs and pre-production evaluations, defining test plans, and tracking results
• Resolving critical customer escalations through structured root-cause analysis and building effective workarounds

The impact you will have:

• Enabling customers to achieve timing signoff on designs that would otherwise miss their tapeout windows
• Shaping the PrimeTime roadmap by connecting real customer pain points with engineering priorities
• Accelerating time-to-production for next-generation capabilities like ML-based corner optimization
• Building reusable deployment methodologies that scale across the customer base

To succeed in this role, you will need:

• A BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline
• Deep hands-on experience with PrimeTime or comparable timing signoff tools across multiple production tapeouts
• Strong understanding of static timing analysis fundamentals, including setup/hold analysis and clock domain crossing
• Proficiency in Tcl and Python for automation, analysis, and debugging of complex timing scenarios
• A track record of solving hard technical problems in EDA, ASIC/SoC design, or physical implementation environments

You will be part of the PrimeTime Product Engineering team, working at the intersection of R&D, Product Management, and customer-facing Application Engineering. This team drives the technical strategy and production readiness for Synopsys timing signoff solutions.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

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You will support customers in feature-specific requirement assessment and integration into the complex ecosystem, assist with silicon/system bring-up and debugging of critical issues, and collaborate with internal teams to enable and deliver tailored solutions to customers.

Your responsibilities will include:

• Acting as a trusted advisor for Interface IP customers
• Supporting customers in feature-specific requirement assessment and integration
• Assisting with silicon/system bring-up and debugging of critical issues
• Collaborating with internal teams to enable and deliver tailored solutions
• Staying updated with the latest industry specifications and applications
• Participating in occasional travel to support customer engagements and silicon bring-up activities

The impact you will have:

• Enhance the usability and adoption of Synopsys' Interface IP products
• Facilitate successful integration of IP into customer designs
• Improve customer satisfaction by resolving technical issues efficiently
• Drive innovation by working with cutting-edge technologies and industry specifications
• Strengthen Synopsys' market position through successful customer engagements and support

Requirements:

• Bachelor's and/or Master's Degree in Electrical Engineering or similar with a focus on VLSI design
• At least 10 years of design, verification, or application engineering experience
• Proficiency in RTL coding using Verilog/VHDL
• Experience with high-speed protocols such as Ethernet or PCIe
• Hands-on experience with simulation, synthesis, and static timing analysis (STA)
• Familiarity with UNIX environments and ASIC/SoC tape-out processes
• Knowledge of CDC, RDC, Lint, DFT, STA, and LEC is a plus

Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

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Responsibilities:

• Develop well-defined features, application components, and AI workflows
• Contribute across the development lifecycle, including implementation, testing, deployment, documentation, and production support
• Gain hands-on experience with AI frameworks and APIs such as LangChain, LangGraph, OpenAI, Gemini, and Glean
• Integrate with systems such as ERP, HRIS, MRP, PDM, and DCIM
• Build user interfaces using React, TypeScript, and modern frontend frameworks
• Implement backend services and automation scripts for data processing and workflow orchestration
• Write tests, troubleshoot defects, and participate in code reviews

Requirements:

• 2+ years of hands-on software development experience
• Working proficiency in one or more programming languages such as TypeScript, Python, Go, Java, C#, or C++
• Solid understanding of programming fundamentals, data structures, debugging, and software testing
• Experience building web applications or backend services using frameworks such as React, Next.js, Node.js, or FastAPI
• Familiarity with RESTful APIs, databases, and basic application integration concepts

Preferred:

• Experience building an AI-powered application, chatbot, or automation workflow
• Exposure to LangChain, LangGraph, OpenAI, Gemini, Glean, or similar frameworks and APIs
• Familiarity with Workato, Boomi, or other integration and automation platforms

Benefits:

• Medical, dental, and vision insurance
• 100% paid for by CoreWeave
• Company-paid Life Insurance
• Voluntary supplemental life insurance
• Short and long-term disability insurance
• Flexible Spending Account
• Health Savings Account
• Tuition Reimbursement
• Ability to Participate in Employee Stock Purchase Program (ESPP)
• Mental Wellness Benefits through Spring Health
• Family-Forming support provided by Carrot
• Paid Parental Leave
• Flexible, full-service childcare support with Kinside
• 401(k) with a generous employer match
• Flexible PTO
• Catered lunch each day in our office and data center locations

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As a Senior Account Solutions Architect, you will work hands-on with some of the most advanced AI teams in the world as they build, train, deploy, and scale their workflows. You will help AI teams solve real-world problems by deepening platform adoption, identifying and driving expansion opportunities, strengthening relationships with key technical stakeholders, and serving as a trusted advisor as customers scale their AI workloads in production.

Responsibilities:

• Partner with Account Managers on the commercial motion
• Work with Specialist Field Engineers for deep domain expertise
• Ensure customers are getting maximum value from CoreWeave
• Represent the voice of the customer internally
• Surface product feedback from the field
• Proactively address technical blockers and business-critical needs

Qualifications:

• 4+ years of relevant experience in a solutions engineer, AI-oriented solutions consultant, or technical field engineering role
• Proficiency in Python
• Hands-on experience training, fine-tuning, evaluating, and deploying deep learning models
• Experience designing and deploying production LLM-powered applications
• Familiarity with running AI workloads on at least one major cloud platform (AWS, GCP, or Azure)
• Demonstrated ability to break down and solve complex technical problems with enterprise customers
• Excellent written and verbal communication and presentation skills

Preferred Skills:

• Working knowledge of cloud infrastructure for AI workloads
• Familiarity with one or more deep learning frameworks (PyTorch) and modern LLM stack (VLLM, langchain / LlamaIndex)
• Experience using Slurm or Kubernetes for ML job orchestration
• Experience with hyperparameter optimization and experiment tracking tools
• Background in ML Engineering, AI Engineering, MLOps, or LLMOps

Benefits:

• Medical, dental, and vision insurance
• 100% paid for by CoreWeave
• Company-paid Life Insurance
• Voluntary supplemental life insurance
• Short and long-term disability insurance
• Flexible Spending Account
• Health Savings Account
• Tuition Reimbursement
• Ability to Participate in Employee Stock Purchase Program (ESPP)
• Mental Wellness Benefits through Spring Health
• Family-Forming support provided by Carrot
• Paid Parental Leave
• Flexible, full-service childcare support with Kinside
• 401(k) with a generous employer match
• Flexible PTO
• Catered lunch each day in our office and data center locations

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You will develop reference designs and subsystem-level architectures that demonstrate best practices for integrating Synopsys IP into complex SoC environments. You will drive subsystem verification, validation, and silicon readiness to accelerate customer adoption and deployment.

Key responsibilities include:

• Leading technical customer engagements for the integration, bring-up, and deployment of Memory Interface PHY and Controller IP
• Developing reference designs and subsystem-level architectures
• Applying hands-on expertise to integrate memory and interface IP into production SoC designs
• Solving complex customer challenges involving IP integration, performance optimization, interoperability, silicon bring-up, and deployment
• Serving as a key technical interface between customers and internal engineering teams
• Providing technical leadership, training, workshops, and presentations to support customer implementation, architecture decisions, and technology adoption
• Bringing customer feedback and deployment insights back to product and engineering teams to improve product quality, usability, integration flows, and deployment readiness

The ideal candidate will have:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
• 15+ years of industry experience in SoC design, verification, implementation, or silicon development
• Hands-on experience with Memory Interface IP such as DDR, LPDDR, and HBM, or Interface IP such as PCIe, Ethernet, CXL, or UCIe
• Proven experience developing reference designs, integrating complex IP subsystems into SoCs, and successfully delivering silicon-proven solutions into production
• Strong understanding of Controller IP, PHY integration, AMBA/AXI interfaces, ASIC design flows, SoC architecture, and backend design considerations

We offer a comprehensive range of health, wellness, and financial benefits.

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You have spent enough time in the FPGA prototyping world to know where designs break down. You listen first, map design challenges, and shape your technical approach around solving real problems. You have debugged enough prototypes to anticipate questions before they are asked, and you use that credibility to de-risk evaluations and accelerate decisions.

Responsibilities

• Lead pre-sales technical engagements for HAPS FPGA prototyping platforms and ProtoCompiler
• Present tailored prototyping solutions addressing customer-specific needs around partitioning, performance, debug, and integration with their existing RTL-to-hardware workflows
• Conduct technical evaluations, proof-of-concept projects, and benchmarks demonstrating how HAPS solves customer problems
• Collaborate with the sales team to shape opportunity strategy, qualify technical fit, handle objections, and move deals through the pipeline
• Deliver compelling product demonstrations, technical presentations, and architecture reviews to engineering teams and executive stakeholders

The Impact You Will Have

• Your technical credibility and solution design will directly win competitive deals, growing HAPS revenue and expanding Synopsys footprint in strategic accounts
• Proof-of-concept work you lead will de-risk customer decisions and shorten sales cycles
• Solutions you architect will set customers up for long-term success, reducing post-sale friction and creating expansion opportunities
• Customer insights you bring back from the field will shape product roadmap priorities and help R&D build features that win in real-world engagements

Requirements

• Bachelor's or Master's in Electronics Engineering, Computer Engineering, or related field
• 1-2+ years of hands-on experience in FPGA-based prototyping, ASIC design, or SoC validation
• Strong command of FPGA architectures, RTL design, synthesis flows, and hardware bring-up and debug techniques
• Comfort with travel to customer sites for evaluations, presentations, and technical engagements
• Experience with HAPS platforms, ProtoCompiler, or similar FPGA prototyping tools is highly desirable

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You have spent the better part of your career translating product ambition into silicon reality. You know that the hardest part of any SoC is not the individual IP blocks, it is making them work together as a coherent system that actually ships. You think in subsystems, not just components. You have sat in enough bring-up sessions to know that the decisions you make today about interconnect topology, power domains, or protocol alignment will either save or cost your team six months down the line.

You are comfortable walking into a room with conflicting requirements from software, verification, and implementation teams and walking out with an architecture that makes sense for all of them. You do not need perfect specs to start. You ask the right questions, model the critical paths, and make the call. You have a point of view on what makes a subsystem robust, and you are not afraid to push back when a proposal does not hold up under real-world constraints. At Synopsys, you will work on IP subsystems that power everything from automotive AI to 5G infrastructure, and the architecture decisions you make will matter.

Responsibilities

• Define subsystem architectures for memory controllers, interconnect clusters, compute blocks, power management units, or communication subsystems, translating product requirements into detailed specs that balance performance, power, area, security, and functionality
• Integrate multiple IP blocks into cohesive subsystems, ensuring proper interoperability, dataflow alignment, and interface compatibility with SoC-level interconnects and firmware requirements
• Lead architecture exploration activities including IP selection, subsystem modeling, and validation of candidate architectures using simulation and analysis tools
• Coordinate with SoC architects, verification teams, software engineers, and physical design groups to ensure subsystem feasibility, correctness, and alignment with platform constraints
• Define verification requirements for subsystem functionality, performance corner cases, power states, and protocol compatibility, working with DV teams to ensure comprehensive validation coverage
• Produce architecture documents, subsystem specifications, engineering guidelines, and implementation requirements that clearly communicate architectural intent to technical and non-technical stakeholders
• Participate in silicon bring-up, debug sessions, and subsystem-level performance characterization to validate architectural decisions in real hardware

Requirements

• Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field with 15+ years of overall semiconductor experience
• 10+ years in semiconductor design, IP integration, or SoC/subsystem architecture roles with proven track record of delivering complex subsystems to production
• Deep expertise in Verilog and SystemVerilog for RTL design and simulation, with hands-on experience using industry-standard simulation tools
• Strong working knowledge of interface protocols such as AMBA APB, AXI, CHI, DDR, PCIe, Ethernet, USB, or UFS, including protocol-level debugging and performance analysis
• Experience with synthesis, lint, CDC, low power design flows, and verification closure using SystemVerilog UVM, BFM development, or test environment creation
• Demonstrated ability to coordinate cross-disciplinary teams including hardware, firmware, software, verification, and physical design groups to drive complex projects to completion
• Excellent technical writing and communication skills with a track record of producing clear architecture documents and specifications that drive alignment across diverse engineering teams

Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• Time away: company holidays, ETO and FTO Programs
• Family support: maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Retirement plans: save for your future with our retirement plans that vary by region and country
• Competitive salaries

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Responsibilities

• Lead pre-sales technical engagements for ZS5, ZeBu-200, and HAPS FPGA prototyping platforms
• Present tailored hardware-assisted verification solutions that address customer-specific needs
• Conduct technical evaluations, proof-of-concept projects, and benchmarks
• Deploy AI-based hardware-assisted verification platforms at customer sites
• Collaborate closely with the sales team to shape opportunity strategy
• Deliver compelling product demonstrations, technical presentations, and architecture reviews

The Impact You Will Have

• Your technical credibility and solution design will directly win competitive deals
• Proof-of-concept work you lead will de-risk customer decisions and shorten sales cycles
• Solutions you architect will set customers up for long-term success
• Customer insights you bring back from the field will shape product roadmap priorities

What You'll Need

• Bachelor's or Master's in Electronics Engineering, Computer Engineering, or related field
• 12-15 years of hands-on experience in emulation, FPGA-based prototyping, ASIC design, or SoC validation
• Strong command of FPGA architectures such as Xilinx or Intel, RTL design in Verilog or VHDL, synthesis flows, and hardware bring-up and debug techniques
• Experience with ZS5, ZeBu, HAPS platforms, or ProtoCompiler is highly desirable

Benefits

• Competitive salary range: $184,000 - $276,000 per year

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You will lead pre-sales technical engagements for ZS5, ZeBu-200, and HAPS FPGA prototyping platforms, working directly with prospective customers to understand their SoC, GPU, and AI design validation challenges. You will present tailored hardware-assisted verification solutions that address customer-specific needs around partitioning, performance, debug, and integration with their existing design flows.

Key responsibilities include:

• Leading pre-sales technical engagements for ZS5, ZeBu-200, and HAPS FPGA prototyping platforms
• Presenting tailored hardware-assisted verification solutions
• Conducting technical evaluations, proof-of-concept projects, and benchmarks
• Deploying AI-based hardware-assisted verification platforms at customer sites
• Collaborating closely with the sales team to shape opportunity strategy
• Delivering compelling product demonstrations, technical presentations, and architecture reviews

The ideal candidate will have:

• Bachelor's or Master's in Electronics Engineering, Computer Engineering, or related field
• 5-6 years of hands-on experience in emulation, FPGA-based prototyping, ASIC design, or SoC validation
• Strong command of FPGA architectures such as Xilinx or Intel, RTL design in Verilog or VHDL, synthesis flows, and hardware bring-up and debug
• Experience with ZS5, ZeBu, HAPS platforms, or ProtoCompiler is a strong plus

In this role, you will have a significant impact on the company's success, including:

• Winning competitive deals and growing ZS5, ZeBu-200, and HAPS revenue
• De-risking customer decisions and shortening sales cycles
• Setting customers up for long-term success and creating expansion opportunities
• Shaping product roadmap priorities and helping R&D build features that win in the field

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You will lead pre-sales technical engagements for ZeBu-200, ZS5 Emulation, and HAPS FPGA prototyping platforms, working directly with prospective customers to understand their SoC, GPU, and AI design validation challenges. You will present tailored hardware-assisted verification solutions that address customer-specific needs around partitioning, performance, debug, and integration with their existing RTL and simulation flows.

Key responsibilities include:

• Leading pre-sales technical engagements for ZeBu-200, ZS5 Emulation, and HAPS FPGA prototyping platforms
• Presenting tailored hardware-assisted verification solutions to address customer-specific needs
• Conducting technical evaluations, proof-of-concept projects, and benchmarks to demonstrate platform value
• Deploying AI-based hardware-assisted verification platforms at customer sites
• Collaborating with the sales team to shape opportunity strategy and move deals through the pipeline

The ideal candidate will have:

• Bachelor's or Master's in Electronics Engineering, Computer Engineering, or related field
• 10-12 years of hands-on experience in emulation, FPGA-based prototyping, ASIC design, or SoC validation
• Strong command of FPGA architectures, RTL design, synthesis flows, and hardware bring-up and debug
• Experience with ZeBu, HAPS platforms, ProtoCompiler, or similar FPGA prototyping and emulation tools is highly desirable

In this role, you will have a significant impact on the company's success, including:

• Winning competitive deals and growing revenue
• De-risking customer decisions and shortening sales cycles
• Setting customers up for long-term success and creating expansion opportunities
• Shaping product roadmap priorities and helping R&D build features that win in the field

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Your role will involve leading pre-sales technical engagements for these platforms, working directly with prospective customers to understand their SoC, GPU, and AI design validation challenges. You will present tailored hardware-assisted verification solutions that address customer-specific needs around partitioning, performance, debug, and integration with their existing design and verification flows.

Key responsibilities include:

• Leading pre-sales technical engagements for ZS5, ZeBu-200, and HAPS FPGA prototyping platforms
• Presenting tailored hardware-assisted verification solutions to address customer-specific needs
• Conducting technical evaluations, proof-of-concept projects, and benchmarks to demonstrate how Synopsys platforms solve customer problems
• Deploying AI-based hardware-assisted verification platforms at customer sites and guiding integration
• Collaborating with the sales team to shape opportunity strategy and move deals through the pipeline
• Delivering compelling product demonstrations, technical presentations, and architecture reviews

The impact you will have includes:

• Directly winning competitive deals and growing ZS5, ZeBu-200, and HAPS revenue
• De-risking customer decisions and shortening sales cycles through proof-of-concept work
• Setting customers up for long-term success and creating expansion opportunities
• Shaping product roadmap priorities and helping R&D build features that win in competitive evaluations

Requirements include:

• Bachelor's or Master's in Electronics Engineering, Computer Engineering, or related field
• 12-15 years of hands-on experience in emulation, FPGA-based prototyping, ASIC design, or SoC validation
• Strong command of FPGA architectures, RTL design, synthesis flows, and hardware bring-up and debug techniques
• Experience with ZS5, ZeBu, HAPS platforms, or ProtoCompiler is highly desirable

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As a member of the Data Platforms Team, you will have the opportunity to drive technical decision-making, mentor engineers, and grow team capability. You will champion event-driven architecture adoption, identify and develop applications for the organization's data, design and implement the platform to deliver data to teams, and develop a stream processing architecture.

Responsibilities:

• Drive technical decision-making to accelerate delivery, mentor engineers, and grow team capability
• Champion event-driven architecture adoption and build consensus across the organization
• Identify and develop applications for the organization's data
• Design and implement the platform to deliver data to teams with a focus on providing managed solutions
• Develop a stream processing architecture and solve for scalability and reliability
• Improve the performance, security, reliability, and scalability of our data platforms, and related services
• Establish guidelines, guard rails for data access and storage for stakeholder teams
• Ensure compliance with standards for data protection regulation

Requirements:

• 15+ years of experience in a software or infrastructure engineering industry
• Understand data consistency and concurrency models, can clearly define data models and establish guidelines around data management
• Familiar with distributed NewSQL datastores such as CockroachDB, TiDB, YDB, Yugabyte and/or stream processing tools such as NATS or Kafka
• Experience with designing and operating these systems at scale
• Familiar with Kubernetes and have interest or experience with using it for event-driven and/or stateful orchestration
• Production level proficiency in Go or Python

We offer a base salary range of $207,000 to $275,000, a discretionary bonus, equity awards, and a comprehensive benefits program.

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Responsibilities:

• Leading a global product and applications engineering organization
• Owning execution quality and outcomes for complex, high-visibility customer engagements
• Serving as a trusted partner to customer engineering leadership
• Driving cross-functional alignment to translate customer challenges into structured technical strategies
• Acting as the AI and digital transformation leader
• Building, mentoring, and retaining senior technical leaders and next-generation experts

The Impact You Will Have:

• Scale expertise through AI and disciplined execution
• Strengthen customer confidence by delivering consistent, predictable, and high-quality technical outcomes
• Elevate organizational maturity by standardizing best practices and modernizing execution models
• Build the next generation of leaders
• Drive transformation initiatives that position Synopsys as a leader in interface IP solutions
• Expand Synopsys’ influence and market share through strategic customer partnerships

What You'll Need:

• Advanced degree in Electrical Engineering or Computer Science, or equivalent depth of industry experience
• 10+ years of semiconductor industry leadership experience
• Proven track record of building and leading high-performing global engineering organizations
• Hands-on experience with SoC development including design, verification, implementation, and interface IP development/integration
• Exceptional executive-level communication and influence skills

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

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You have spent years turning ASIC designs into working FPGA prototypes, and you know the difference between RTL that compiles and RTL that actually runs reliably across multiple FPGAs at speed. The challenge excites you: partitioning a design that was never meant to be split, closing timing on a path that crosses three SLRs, or debugging a reset issue that only shows up in hardware after two hours of runtime.

You are equally comfortable writing SystemVerilog that synthesizes cleanly and Python scripts that automate the tedious parts of your workflow. When a bring-up fails, you reach for the logic analyzer, the scope, and the source code in that order, and you do not stop until you understand why. You have learned that production-quality tools matter as much as production-quality RTL, and you build both.

Responsibilities

• Develop FPGA-optimized implementations for HAPS platforms, addressing capacity limits, timing constraints, and multi-FPGA partitioning challenges
• Own the full FPGA development cycle from RTL modification through Vivado synthesis, place-and-route, timing closure, and hardware validation on AMD/Xilinx devices
• Drive board and system bring-up for HAPS prototyping hardware, including functional validation, performance characterization, signal integrity testing, and root-cause debug of complex hardware and RTL issues
• Develop production-ready test frameworks and automation tools using Python and C/C++ to validate high-speed interfaces, run PRBS testing, analyze eye diagrams, and measure jitter and link margins
• Build and maintain multi-FPGA solutions including partitioning strategies, inter-FPGA communication protocols, clock distribution networks, and reset architectures that work reliably across device boundaries
• Debug RTL, timing, clocking, and integration issues across simulation, emulation, and physical hardware using lab equipment including oscilloscopes, logic analyzers, protocol analyzers, and spectrum analyzers
• Collaborate with architecture, hardware, software, manufacturing, and verification teams to deliver prototyping solutions from concept through production deployment

The Impact You Will Have

• Enable customer ASIC designs to run on HAPS platforms months before silicon is available, directly accelerating their validation schedules and reducing risk
• Deliver FPGA implementations that close timing, meet performance targets, and run reliably in production test environments, reducing debug cycles and improving product quality
• Build automation tools and workflows that make FPGA bring-up faster and more repeatable for the entire HAPS Production Test Team
• Solve complex multi-FPGA partitioning and communication challenges that unlock prototyping for designs that would otherwise be too large or too fast for a single device
• Identify and resolve signal integrity, timing, and hardware issues that would otherwise delay product releases or cause field failures
• Create test frameworks and validation infrastructure that catch issues early and give manufacturing teams confidence in what they are shipping
• Contribute technical expertise and design documentation that raises the bar for how the team approaches FPGA development, bring-up, and production test

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• 10+ years of hands-on FPGA and RTL design experience
• Expert-level proficiency in SystemVerilog and Verilog for RTL design, with deep understanding of digital design fundamentals, clocking architectures, reset strategies, clock domain crossing, and timing analysis
• Extensive experience with AMD/Xilinx FPGA synthesis, place-and-route, and timing closure using Vivado, including optimization for resource utilization, SLR crossings, and routing congestion
• Strong programming skills in C/C++ and Python with a proven track record of developing production-quality software, automation frameworks, debug utilities, and engineering tools
• Proficiency using lab equipment including oscilloscopes, logic analyzers, protocol analyzers, and multimeters to debug and validate hardware systems
• Experience with signal integrity characterization, PRBS testing, eye diagram analysis, jitter measurement, and link margining is a strong plus

Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• Time away: company holidays, ETO and FTO Programs
• Family support: maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Retirement plans: save for your future with our retirement plans that vary by region and country
• Competitive salaries

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You have spent years in the EDA world, likely starting as an Applications Engineer or Product Specialist, and you have learned that the best technical wins come from understanding the customer's business problem before you ever open the demo. You know how to sit across from a VP of Engineering at a major semiconductor company and map their 3DIC roadmap to a multi-quarter technical campaign that actually closes.

Your responsibilities will include:

• Lead technical sales campaigns for 3DIC solutions across strategic semiconductor accounts
• Drive customer discovery sessions to uncover technical requirements, business drivers, and solution fit
• Serve as the primary business and sales focal point for 3DIC opportunities
• Build and maintain executive and technical relationships across customer organizations
• Work directly with Applications Engineering teams to align proof-of-concept activities, evaluations, and deployments with customer success criteria and timelines

The impact you will have:

• Expand 3DIC solution adoption across strategic accounts, directly driving revenue growth
• Shape customer roadmaps by identifying opportunities early and aligning Synopsys capabilities with their long-term technical and business objectives
• Accelerate deal cycles by managing complex technical campaigns with clarity
• Influence product direction by feeding market requirements, competitive insights, and customer feedback directly to Product Management and R&D teams

You will need:

• 5+ years of experience in EDA sales, Applications Engineering, or Product Specialist roles with a strong technical foundation in semiconductor design or advanced packaging technologies
• Direct experience in the 3D IC market segment, including familiarity with chiplet architectures, advantage packaging (interposer) and substrate design, and System Technology Co-Optimization (STCO)
• Proven ability to manage long-term enterprise sales engagements
• Strong relationship-building skills with a track record of developing executive and technical relationships across customer organizations
• Ability to collaborate internally with Product Management and R&D teams to align customer requirements with product capabilities and roadmaps

Rewards and benefits include a comprehensive range of health, wellness, and financial benefits.

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We are seeking an experienced semiconductor Project Engineering leader to serve as a Customer Quality Champion, Principal Project Engineering Manager. As a key member of our team, you will drive customer success, quality excellence, and continuous improvement.

What You'll Be Doing

• Serve as the Customer Quality Champion for assigned strategic customers, building trusted relationships, representing the voice of the customer, and driving successful outcomes.
• Develop deep understanding of customer workflows, product use, silicon bring-up, and debug challenges to assess quality risks, customer impact, and execution priorities.
• Lead cross-functional problem-solving and escalation management, driving 8D, RCCA, corrective and preventive actions through clear communication and closure.
• Proactively identify and mitigate customer quality and execution risks, translating feedback, bring-up findings, and lessons learned into systemic improvement actions.
• Drive quality operating rhythms and improvement programs through reviews, dashboards, metrics, action tracking, and clear tradeoff decisions across schedule, quality, and customer impact.

The Impact You Will Have

• Improve customer satisfaction, trust, and long-term partnerships through consistent quality execution and responsiveness.
• Reduce customer escalations by improving turnaround time, resolution effectiveness, and proactive issue management.
• Strengthen product quality and release readiness through risk management, prevention, and continuous improvement.
• Improve customer quality metrics, scorecards, and business review outcomes through disciplined quality focus and follow-through.
• Drive organizational alignment and accountability around customer requirements, commitments, and systemic issue resolution.

What You'll Need

• BS or MS in Electrical Engineering, Computer Engineering, or a related field, with 10+ years of semiconductor industry experience in engineering, quality, verification, methodology, program management, or customer-facing technical leadership.
• Strong digital and/or mixed-signal IP methodology expertise, including development, verification, integration, signoff, silicon validation, and bring-up.
• Proven experience leading customer escalations, 8Ds, RCCAs, corrective actions, and continuous improvement initiatives in complex semiconductor environments.
• Strong understanding of semiconductor product development, quality systems, risk management, and release-readiness processes, with the ability to lead cross-functional programs and drive results without direct authority.
• Excellent communication, executive presentation, stakeholder management, and execution discipline, including use of dashboards, metrics, status reporting, and tools such as Microsoft Project, Confluence, and Jira.

Who You Are

• A customer advocate and trusted advisor who builds credibility and long-term partnerships.
• A strong technical and quality leader with the judgment to guide complex customer and engineering situations.
• A structured problem solver who drives accountability, closure, and systemic issue resolution.
• A proactive risk manager who anticipates customer impact and acts early to prevent escalation.
• An effective communicator and champion of continuous improvement who works across customers, executives, and engineering teams.

Team You Will Be Part Of

You will work across Engineering, Verification, Methodology, Quality, Program Management, and Customer Support organizations to strengthen customer relationships, improve product quality, and drive continuous improvement across Synopsys.

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Key Responsibilities:

• Drive IC Validator evaluations and competitive benchmarks at leading semiconductor customers, from initial setup through production signoff adoption
• Develop, customize, and debug Physical Verification rule decks and runsets for DRC, LVS, FILL, and PERC across advanced process nodes
• Solve complex customer issues that span tool behavior, runset logic, design methodology, and foundry rule interpretation
• Lead technical demonstrations, training sessions, and hands-on customer engagements that move evaluations to deployment
• Build and support AI/ML and agentic applications for Physical Verification, including intelligent debug, violation classification, and workflow automation
• Collaborate with R&D, Product Engineering, and Sales to translate customer feedback into product requirements and enhancements
• Script and automate Physical Verification flows using Python, TCL, Perl, and shell scripting to improve customer productivity and adoption

The Impact You Will Have:

• Enable customers to tape out advanced-node designs on time by ensuring their Physical Verification flows are correct, efficient, and production-ready
• Accelerate IC Validator adoption at strategic accounts, directly contributing to Synopsys revenue and market position in Physical Verification
• Reduce customer debug time and engineering effort by deploying AI-assisted workflows that catch issues earlier and classify violations intelligently
• Influence the future of Synopsys Physical Verification tools by providing real-world customer feedback that shapes R&D priorities
• Build long-term technical relationships with customers that make Synopsys their trusted partner for signoff verification
• Help define how AI and agentic technologies will transform Physical Verification workflows across the semiconductor industry
• Improve foundry rule deck quality and deployment speed by identifying gaps, debugging issues, and working with ecosystem partners

Requirements:

• Bachelor's or Master's degree in Electrical Engineering, Computer Science, VLSI, or a related technical field
• 10+ years of hands-on industry experience in Physical Verification, including DRC, LVS, FILL, and PERC methodologies
• Deep experience with Physical Verification tools such as IC Validator, Calibre, Assura, or equivalent EDA solutions
• Strong scripting and automation skills in Python, TCL, Perl, or shell scripting for runset development and workflow automation
• Proven ability to develop, qualify, and debug Physical Verification rule decks and runsets for complex designs
• Familiarity with Physical Design flows using Fusion Compiler or Innovus, and custom layout environments like Custom Compiler or Virtuoso
• Experience driving customer evaluations, competitive benchmarks, and production deployment at semiconductor companies is a strong plus

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You have spent years making office environments actually work, not just look good in a facilities plan. You know that the difference between a site that hums and one that drains productivity is in the details: the HVAC system that was spec'd wrong, the move that got scheduled during a critical product deadline, the vendor who needs managing before they become a problem. You think in systems, not tickets. When someone says "the data center is down," you are already three steps ahead, diagnosing root cause and calling the right people.

Responsibilities

• Manage ongoing facilities projects across multiple Americas offices, from site selection and design review through construction oversight and final delivery
• Review and estimate costs for design work, equipment procurement, installation labor, materials, site preparation, and all associated project expenses
• Inspect construction and installation progress against drawings, specifications, schedules, and code requirements to ensure conformance and quality
• Maintain day-to-day operations by coordinating moves, adds, changes, office services, and mechanical, electrical, and plumbing systems across your portfolio of sites
• Oversee outside contractors and vendors, ensuring work quality, schedule adherence, and alignment with Synopsys standards and safety protocols
• Prepare and manage operating expense budgets, track expenditures, analyze variances, and recommend capital investments to support site and business objectives
• Provide regular project and operational updates to management, flagging risks early and proposing solutions with supporting data

The Impact You Will Have

• Enable uninterrupted engineering work across some of Synopsys's largest field offices by keeping critical systems running and projects on track
• Deliver high-quality, cost-effective facilities services that allow technical teams to focus on silicon innovation, not building issues
• Reduce operational risk and downtime by proactively maintaining MEP systems, data center environments, and office infrastructure
• Improve facilities asset efficiency and lifecycle performance through disciplined program management and continuous improvement
• Build strong vendor and contractor relationships that translate into better pricing, faster response times, and higher-quality outcomes
• Support business growth and site expansion by managing site selection, buildouts, and office reconfigurations that align with headcount and strategic plans
• Mentor junior facilities team members by modeling sound judgment, technical rigor, and a bias toward solving problems before they escalate

Requirements

• Bachelor's degree with 5 to 7+ years of facilities management, project management, or corporate workplace operations experience
• Demonstrated project management experience in a corporate or high-tech environment, ideally managing multiple concurrent projects across distributed sites
• Working knowledge of mechanical, electrical, and plumbing systems, including troubleshooting, vendor management, and compliance with applicable codes
• Experience preparing and managing budgets, analyzing cost variances, and making data-driven recommendations on capital and operating expenses
• Proficiency with Excel for budget tracking and analysis, PowerPoint for stakeholder updates, and Microsoft Word for documentation and reporting
• Willingness and ability to travel regularly across the Americas to visit sites, oversee projects, and support field offices as needed
• Availability for 24/7 on-call status to respond to urgent facilities issues, system failures, or critical site needs

Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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At Synopsys, you will work at the intersection of digital IP development, AI methodology adoption, and EDA tooling, driving programs that shape how semiconductor design gets done.

What You'll Be Doing

• Manage execution of multiple programs focused on digital design flows, AI methodology deployment, and operational improvements across Interface IP R&D teams
• Partner with technical leaders across engineering disciplines, product teams, and EDA technology experts to define program objectives, scope, and deliverables
• Develop and maintain comprehensive program plans, dashboards, and analytics that track progress, surface risks, and enable data-driven decision making
• Collaborate with senior leadership to align program goals with company strategy and ensure visibility into critical business initiatives
• Present program status, risks, and outcomes to executive audiences, translating technical complexity into clear business impact
• Run team operations including newsletters, internal websites, Jira tracking, and cross-functional coordination mechanisms
• Work across global teams to identify workflow gaps, drive operational improvements, and enable adoption of best-in-class digital methodologies

The Impact You Will Have

• Scale the adoption of advanced digital methodologies and AI practices across multiple digital IP product lines, directly improving design productivity and quality
• Influence cross-functional teams to adopt new workflows and tools ahead of industry trends, strengthening Synopsys market position
• Drive measurable project success by closing workflow gaps, enabling operational improvements, and reducing time-to-market for IP releases
• Enable communication and coordination across geographically distributed teams, ensuring alignment and reducing friction in complex program execution
• Facilitate smooth execution of Digital Methodology team initiatives that directly affect how hundreds of engineers design and verify semiconductor IP
• Support advancement of innovations in quality, productivity, and execution excellence that become repeatable practices across the organisation
• Create visibility into program health and technical progress that allows leadership to make faster, better-informed decisions

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, Data Science, or related discipline
• 10+ years of experience in the semiconductor industry with a strong foundation in digital design, verification, or EDA tooling
• Proven experience as a Technical Program Manager leading complex, cross-functional programs in semiconductor development environments
• Strong project management skills with demonstrated ability to manage multiple priorities, build program plans, and drive execution to completion
• Exceptional written and verbal communication skills, including experience preparing and presenting to executive audiences
• Strong analytical and problem-solving skills with the ability to create dashboards, track metrics, and use data to drive decisions
• Understanding of artificial intelligence or machine learning methodologies and their application to semiconductor design flows
• Familiarity with MS Office Suite, Unix, and Perforce
• Experience with digital front-end flows, Synopsys verification tools, and Fusion Compiler is a plus
• PMP or other relevant program management certifications are a plus

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You will serve as a key partner to IFM leadership and service teams, providing operational direction, coaching, escalation support, and continuous-improvement guidance. You will also provide governance and oversight of hard facilities services and critical building infrastructure, including mechanical, electrical, plumbing, building management systems, data center support infrastructure, generators, UPS systems, elevators, lighting, roofs, and other building systems.

Your responsibilities will include:

• Providing business oversight and governance of IFM services
• Serving as a key partner to IFM leadership and service teams
• Providing governance and oversight of hard facilities services and critical building infrastructure
• Overseeing maintenance strategies, preventive and corrective maintenance programs, inspections, repairs, planned shutdowns, vendor activities, and service-restoration efforts
• Developing and maintaining Facilities Management playbooks, operating procedures, service standards, governance practices, escalation processes, and performance measures
• Monitoring service delivery and building performance, identifying recurring issues and operational risks, and working with service providers to implement corrective actions and continuous improvements
• Supporting workplace and portfolio planning through attendance, occupancy, capacity, utilization, and space-allocation analysis
• Partnering with business leaders and workplace teams on relocations, organizational changes, flexible-seating strategies, workplace optimization, and post-acquisition integrations
• Supporting annual operating planning, budgeting, forecasting, expense analysis, contract planning, project estimates, and cost-optimization initiatives
• Partnering with Procurement on vendor sourcing by developing requirements, evaluating proposals, participating in RFP scoring, validating pricing and scope, and supporting contracting and implementation
• Providing business governance for workplace and facilities technology platforms, including IWMS and work-order-management systems
• Partnering with technology teams and service providers on system enhancements, platform migrations, integrations, reporting requirements, user adoption, and operational continuity
• Developing workplace and facilities dashboards, analytics, and reporting that provide visibility into attendance, utilization, capacity, service delivery, maintenance performance, and operational trends
• Maintaining Real Estate & Facilities business-continuity and emergency-response programs, including recovery planning, exercises, and after-action reviews

You will have the opportunity to make a significant impact on the organization by:

• Strengthening the Facilities Management operating model
• Improving the reliability and resilience of critical building systems
• Helping outsourced service-provider teams develop into capable and trusted partners
• Providing better-informed workplace and real estate portfolio decisions
• Improving visibility into workplace and facilities performance
• Identifying opportunities to optimize space, maintenance practices, service delivery, vendor performance, and operating costs
• Improving operational resilience and preparedness across critical workplace and building functions

To be successful in this role, you will need:

• Significant progressive experience in Facilities Management, Corporate Real Estate operations, Workplace Operations, building operations, or a related field
• Demonstrated experience overseeing outsourced facilities-management providers and multiple hard- and soft-service lines
• Strong working knowledge of commercial building systems, including HVAC, electrical, plumbing, building management systems, emergency power, UPS systems, elevators, and other critical facility infrastructure
• Experience overseeing preventive and corrective maintenance programs, inspections, repairs, planned shutdowns, vendor service activities, and operational issue resolution
• Experience using work-order, maintenance, asset, and service-performance data to improve building reliability and operational performance
• Experience developing operating procedures, maintenance and service standards, governance practices, escalation processes, and performance measures
• Experience with workplace planning, occupancy, capacity, utilization, space allocation, and workplace-optimization initiatives
• Experience supporting annual budgets, forecasts, expense analysis, vendor contracts, project estimates, and cost-management initiatives
• Experience with vendor sourcing and procurement processes, including requirements development, proposal evaluation, RFP scoring, pricing review, and contract implementation
• Experience with IWMS, CMMS, work-order-management, workplace-experience, or similar facilities technology platforms
• Strong analytical capabilities and experience developing dashboards, reporting, metrics, or decision-support tools
• Experience with RE & Facilities department business continuity, emergency preparedness, or operational-resilience programs
• Strong written, verbal, presentation, and stakeholder-management skills
• Ability to work effectively across Finance, Procurement, HR, IT, Security, Legal, business leadership, engineering teams, and external service providers
• Bachelor's degree in Facilities Management, Engineering, Business, Real Estate, Construction Management, or a related discipline, or equivalent relevant experience
• Professional certification such as CFM, MCR, PMP, or a related credential is preferred
• Experience supporting a geographically dispersed or global workplace portfolio is preferred

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You have spent years turning complex system requirements into working silicon, and you know that the hardest part is not writing RTL, it is making the right architectural decisions in week two that keep your team from hitting a wall in month six. You have led design teams through the full cycle, from early partitioning conversations to timing closure, and you understand that leadership at this level means knowing when to dive into the details and when to step back and let your engineers solve it.

Responsibilities

• Lead design teams of junior and senior engineers through full ASIC and FPGA development cycles, from specification to GDSII handoff
• Partition and architect complex SOC designs from customer requirements, creating high-level and micro-architectures that balance performance, area, and power
• Drive RTL development using SystemVerilog, ensuring designs meet quality standards through code reviews, lint checks, CDC/RDC analysis, and synthesis readiness
• Collaborate directly with verification, DFT, and physical design teams to resolve integration issues, timing closure challenges, and design-for-test requirements
• Implement complex industry-standard protocols including PCIe, Ethernet, and UCIe within customer-specific SOC designs
• Develop and refine ASIC design flows and methodologies using Synopsys and vendor tools for simulation, synthesis, static timing analysis, and signoff
• Work hands-on with customers ranging from startups to industry leaders across automotive, aerospace, defense, and high-performance computing markets

The Impact You Will Have

• Your architectural decisions will directly determine whether customer designs meet aggressive PPA targets in advanced process nodes
• The teams you build and lead will deliver turnkey SOC designs that power next-generation AI, autonomous vehicles, and mission-critical aerospace systems
• Your design methodologies will become reusable frameworks that accelerate future customer engagements across the Solutions group
• The RTL quality standards you enforce will reduce verification cycles and prevent costly respins for multi-million-dollar tape-outs
• Your ability to navigate complex customer requirements will unlock new business opportunities and long-term partnerships
• The engineers you mentor will grow into technical leaders who carry forward the rigor and craft you bring to every design
• Your work will help Synopsys customers ship products faster, with higher confidence, in markets where failure is not an option

Requirements

• Bachelor's degree in Electrical Engineering or Computer Engineering
• 15+ years of hands-on experience designing and verifying ASIC or FPGA devices through multiple tape-outs or production releases
• Proven experience leading design teams, including mentoring engineers and managing technical execution across project milestones
• Deep understanding of the full ASIC design flow from micro-architecture through RTL development, synthesis, timing closure, and physical design handoff
• Strong SystemVerilog RTL coding skills with demonstrated ability to design and review complex control and datapath logic
• Working knowledge of industry-standard protocols such as PCIe, Ethernet, or UCIe in real production designs
• Experience with ASIC development tools including simulators, lint tools, CDC/RDC checkers, synthesis tools, and static timing analysis platforms

Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• Time away programs including ETO and FTO
• Family support including maternity and paternity leave, parenting resources, adoption and surrogacy assistance
• ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Retirement plans that vary by region and country
• Competitive salaries

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About the Team

The IT GTM Systems team owns the architecture, administration, and continuous improvement of the go-to-market technology stack that powers CoreWeave’s Sales, RevOps, Marketing, Legal, Finance, and Deal Desk functions. We partner closely with cross-functional stakeholders and external implementation partners to design scalable Salesforce-based solutions that support CoreWeave’s rapid growth, including billing integrations, multi-org consolidation, international expansion, and compliance initiatives.

Key Responsibilities

As a Business Systems Engineer (GTM), you’ll join the IT GTM Systems team as a hands-on Salesforce developer and administrator. You’ll help build, configure, and maintain the Salesforce ecosystem that supports CoreWeave’s GTM organization while translating business requirements into scalable, well-architected solutions.

• Design, build, and maintain Salesforce solutions, including flows, validation rules, custom objects, page layouts, permission sets, and other declarative configurations, to support GTM business processes.

• Partner with RevOps, Marketing Operations, Legal, Finance, Deal Desk, and other cross-functional teams to gather requirements and translate them into scalable technical designs.

• Perform day-to-day Salesforce administration, including user management, data quality, security and access controls, and system health monitoring.

• Support and contribute to larger GTM systems initiatives, including billing integrations, multi-org consolidation, international and multi-currency expansion, and compliance projects.

• Troubleshoot and resolve production issues by identifying root causes and implementing durable fixes.

• Collaborate with external implementation partners and consultants to support project delivery.

• Write and maintain clear technical documentation for solutions, processes, and configurations.

• Participate in testing, quality assurance, and change management processes to support high-quality, SOX-compliant releases.

• Communicate effectively with technical and non-technical stakeholders, providing clear status updates and surfacing risks proactively.

Qualifications

• 2+ years of hands-on experience in Salesforce development and/or administration, ideally supporting a GTM, Sales, or RevOps organization.

• Strong working knowledge of core Salesforce capabilities, including Sales Cloud, Flow and process automation, validation rules, permission sets and profiles, reports and dashboards, and data management.

• Excellent written and verbal communication skills, with the ability to explain technical concepts to non-technical stakeholders.

• Demonstrated ability to work cross-functionally and build strong relationships with business and technical partners.

• Strong team player with a collaborative, solutions-oriented mindset.

• Detail-oriented, organized, and able to prioritize effectively in a fast-paced, high-growth environment.

• Bachelor’s degree in a related field or equivalent practical experience.

Preferred Skills

• Salesforce Administrator certification (ADM 201 or equivalent).

• Salesforce Platform Developer I certification.

• Working knowledge of Apex, SOQL, Lightning Web Components, or other Salesforce development tools.

• Experience supporting Salesforce integrations, multi-org environments, international expansion, or multi-currency implementations.

• Experience working in a SOX-controlled environment or supporting formal change management and release processes.

Why CoreWeave?

At CoreWeave, we work hard, have fun, and move fast! We’re in an exciting stage of hyper-growth that you will not want to miss out on. We’re not afraid of a little chaos, and we’re constantly learning. Our team cares deeply about how we build our product and how we work together, which is represented through our core values:

• Be Curious at Your Core

• Act Like an Owner

• Empower Employees

• Deliver Best-in-Class Client Experiences

• Achieve More Together

We support and encourage an entrepreneurial outlook and independent thinking. We foster an environment that encourages collaboration and enables the development of innovative solutions to complex problems. As we get set for takeoff, the organization's growth opportunities are constantly expanding. You will be surrounded by some of the best talent in the industry, who will want to learn from you, too. Come join us!

The base salary range for this role is $120,000 to $160,000. The starting salary will be determined by job-related knowledge, skills, experience, and the market location. We strive for both market alignment and internal equity when determining compensation. In addition to base salary, our total rewards package includes a discretionary bonus, equity awards, and a comprehensive benefits program (all based on eligibility).

What We Offer

In addition to a competitive salary, we offer a variety of benefits to support your needs. The benefits below reflect our US-based offerings for full-time employees; for roles in other locations, benefits vary and are shared during the hiring process. These include:

• Medical, dental, and vision insurance - 100% paid for by CoreWeave

• Company-paid Life Insurance

• Voluntary supplemental life insurance

• Short and long-term disability insurance

• Flexible Spending Account

• Health Savings Account

• Tuition Reimbursement

• Ability to Participate in Employee Stock Purchase Program (ESPP)

• Mental Wellness Benefits through Spring Health

• Family-Forming support provided by Carrot

• Paid Parental Leave

• Flexible, full-service childcare support with Kinside

• 401(k) with a generous employer match

• Flexible PTO

• Catered lunch each day in our office and data center locations

• A casual work environment

• A work culture focused on innovative disruption

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You will engage directly with customers to identify high-value problems, particularly around optimizing power, performance, and area (PPA), and achieving multi-physics closure in design.

Key responsibilities include:

• Analyzing and interpreting market trends to inform the Synopsys SCA roadmap, with a focus on advanced nodes and GenAI/Agentic flows.
• Collaborating with DRIs and field partners to pinpoint product gaps and evaluate new opportunities for tool enhancement and innovation.
• Defining and prioritizing product roadmaps by crafting Market Requirements Documents (MRDs) and partnering with Product Engineers to develop Product Requirements Documents (PRDs).
• Writing code prototypes for new features and products, serving as "executable specifications" to demonstrate functionality and requirements to development teams.
• Managing release readiness, including defining criteria for Alpha, Beta, Limited Customer Availability (LCA), and General Availability (GA) stages.
• Enabling partners and field teams with training, strategic campaigns, and benchmarks to ensure new products deliver on promised value.
• Representing Synopsys as a subject matter expert at customer forums, including TRMs and MRMs, and driving thought leadership at industry conferences.

The impact you will have:

• Accelerate the adoption of Synopsys solutions, driving improved PPA outcomes for customers.
• Shape the direction of Synopsys’s product offerings by identifying and acting on emerging industry trends.
• Build stronger customer relationships through direct engagement, enabling tailored solutions that address their most critical challenges.
• Enhance Synopsys’s reputation as a technology leader by presenting at industry events and fostering thought leadership.
• Streamline product development processes through executable specifications, ensuring clarity and alignment across teams.
• Increase the commercial success of new products by ensuring release readiness and effective go-to-market strategies.
• Elevate partner and sales enablement, empowering teams to communicate product value and drive adoption.

Requirements:

• Deep technical expertise in EDA tools, especially in synthesis, RTL architecture, place and route and ECO methodologies.
• Proven experience in product management, including roadmap prioritization, MRD/PRD development, and release readiness.
• Strong coding skills for prototyping features and creating executable specifications.
• Ability to analyze market trends, customer feedback, and competitive landscapes to inform product strategy.
• Experience collaborating with cross-functional teams (engineering, sales, marketing, partners) in a fast-paced environment.
• Familiarity presenting at industry forums, conferences, and customer meetings as a subject matter expert.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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The Digital Methodology Center of Excellence (DMCoE) develops and deploys industry-leading methodologies that enable successful adoption of Synopsys TestMAX solutions and advanced Design-for-Testability technologies across the semiconductor ecosystem.

You are a recognized DFT expert with extensive experience architecting and deploying test solutions for complex ASIC and SoC designs. You possess deep knowledge of scan architectures, ATPG, test access infrastructures, and DFT standards, coupled with the ability to influence technical strategies across organizations.

Responsibilities

• Define and drive corporate and customer-facing DFT methodologies for next-generation ASIC and SoC designs.
• Serve as a technical leader and subject matter expert for Synopsys TestMAX DFT, ATPG, diagnosis, and silicon lifecycle solutions.
• Lead deployment of advanced DFT architectures including scan compression, hierarchical DFT, boundary scan, IEEE 1500 wrapper solutions, IJTAG infrastructures, and embedded test technologies.
• Architect scalable test access and instrumentation networks leveraging IEEE 1149.1, IEEE 1149.6, IEEE 1687 (IJTAG), and IEEE 1500 standards.
• Develop best practices for DFT insertion, ATPG generation, pattern validation, diagnosis, and coverage optimization.
• Drive adoption of reusable methodologies, automation frameworks, and signoff criteria across multiple programs and business units.
• Collaborate with R&D organizations to influence future product capabilities and roadmap priorities.
• Provide technical leadership for strategic customer engagements, methodology reviews, and complex technical escalations.
• Mentor engineers across multiple teams and contribute to the development of the organization's DFT expertise.

The Impact You Will Have

• Enable successful deployment of industry-leading DFT methodologies across the world's most advanced semiconductor programs.
• Drive measurable improvements in test quality, manufacturability, and silicon reliability.
• Influence next-generation TestMAX capabilities through direct customer engagement and technical leadership.
• Accelerate adoption of advanced standards-based test architectures across strategic customer accounts.
• Improve engineering productivity through methodology standardization, automation, and best-practice development.
• Establish Synopsys as the trusted advisor and technology leader in DFT and manufacturing test solutions.
• Contribute to breakthrough technologies powering AI, automotive, networking, and high-performance computing applications.

Requirements

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 15+ years of experience in Semiconductor or EDA industry with a focus on DFT, ATPG, and manufacturing test methodologies.
• Demonstrated expertise in architecting and implementing DFT solutions for large-scale ASIC and SoC designs.
• Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG solutions.
• Strong understanding of:
• Scan insertion and scan compression
• Hierarchical DFT methodologies
• ATPG and diagnosis
• Stuck-at, transition, path-delay, bridge, and cell-aware fault models
• Coverage analysis and optimization
• Test cost and pattern count reduction techniques
• Expertise with standards including:
• IEEE 1149.1 (JTAG)
• IEEE 1149.6 (AC JTAG)
• IEEE 1687 (IJTAG)
• IEEE 1500
• Experience developing and deploying:
• JTAG / TAP Architectures
• Boundary Scan Networks
• IJTAG Instrumentation Networks
• Embedded Instrument Access Solutions
• Expertise in deploying and integrating DFT IP including:
• Codec / Embedded Compression
• OCC (On-Chip Clock Controller)
• LBIST
• TAP Controllers
• JTAG and IJTAG Infrastructure
• TDR Networks
• IEEE 1500 Wrappers
• Strong understanding of RTL-to-GDSII implementation flows and interactions between DFT, synthesis, physical design, timing closure, and signoff.
• Proficiency with Tcl, Python, Perl, Shell, or similar scripting languages for methodology development and automation.

Benefits

• Comprehensive medical and healthcare plans
• Time away programs
• Family support
• ESPP
• Retirement plans
• Competitive salaries

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Your expertise spans developing and enhancing physical design methodologies and automation solutions using TCL, Python, Perl, or Pandas. You're adept at performing static timing analysis, clock-tree synthesis, and ECO implementation using industry-standard tools like PrimeTime, ICC2, Fusion Compiler, or Cadence Innovus.

As a Physical Design Staff Engineer at Synopsys, you will drive timing closure, signoff readiness, and PPA optimization for advanced-node customer designs. You will develop and enhance physical design methodologies and automation solutions to improve design quality, predictability, and team efficiency. Your responsibilities also include:

• Performing static timing analysis, clock-tree synthesis, and ECO implementation using tools like PrimeTime, ICC2, Fusion Compiler, or Cadence Innovus
• Analyzing design data and trends to identify bottlenecks, predict issues, and build flows that make the next tapeout smoother than the last
• Collaborating with cross-functional engineering teams including design, verification, and CAD to ensure successful silicon delivery
• Contributing to AI-assisted and machine learning-driven design optimization initiatives, applying data-driven approaches to solve complex implementation challenges
• Troubleshooting complex physical design problems that do not have obvious answers, and developing scalable technical solutions that work across multiple projects

In this role, your methodologies and automation will directly reduce design cycle time and improve first-pass silicon success for Synopsys customers building chips at 3nm, 2nm, and beyond. Your contributions will shape how future tools and methodologies are developed at Synopsys.

To excel in this position, you need:

• A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field
• 5+ years of hands-on experience with ASIC physical design, implementation, and timing closure across block, subsystem, or chip-level designs
• Deep working knowledge of static timing analysis, clock-tree synthesis, signoff flows, and ECO methodologies
• Proficiency with industry-standard implementation tools such as Synopsys ICC2, Fusion Compiler, or Cadence Innovus
• Strong scripting and automation skills using TCL, Python, Perl, or similar languages to build flows and analyze data
• Experience with advanced-node semiconductor design at 7nm or below is a strong plus
• Exposure to machine learning, AI-assisted design optimization, or data-driven engineering workflows is a plus

In return for your expertise, Synopsys offers a comprehensive range of health, wellness, and financial benefits to cater to your needs.

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You are a seasoned RTL design leader with a strong record of driving complex ASIC digital subsystems from concept to silicon. You bring the technical depth to define architecture, translate requirements into clear specifications, and deliver high-quality, first-time-right RTL for robust, scalable subsystem designs.

What You Will Be Doing:

• Leading the subsystem lifecycle from requirements and architecture definition through release
• Developing subsystem architecture, functional specifications, and high-quality RTL micro-architecture
• Driving design quality through RTL linting, CDC, RDC, and close partnership with verification, DFT, and implementation teams
• Integrating standard protocols such as UCIe, Ethernet, UALink, and AMBA into subsystem designs
• Applying low power and DFT design methodologies at the architectural level
• Mentoring junior engineers and contributing to technical reviews and design excellence

The Impact You Will Have:

• Delivering high-performance digital IP subsystems that power next-generation silicon solutions
• Enabling first-time-right RTL, helping reduce verification cycles and accelerate time-to-market
• Strengthening subsystem quality, scalability, and interoperability through rigorous design practices
• Influencing architectural decisions that shape the future of digital IP design at Synopsys
• Contributing to a collaborative, innovative engineering culture through mentorship and technical leadership

What You Will Need:

• BSEE, BSCE, MSEE, MSCE, or an advanced degree, plus 8+ years of direct experience in RTL design and subsystem architecture for complex ASIC or SoC projects
• Strong expertise in RTL coding using Verilog/System Verilog, along with linting, CDC, RDC, and formal verification tools
• Experience with standard protocols such as UCIe, Ethernet, UALink, and AMBA
• Solid knowledge of low power design methodologies, DFT architecture, and the broader ASIC design flow
• Proven ability to lead cross-functional efforts from specification through silicon

Rewards and Benefits:

• Comprehensive medical and healthcare plans that work for you and your family
• In addition to company holidays, we have ETO and FTO Programs
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• Purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Save for your future with our retirement plans that vary by region and country
• Competitive salaries

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You will be collaborating with cross-functional teams during early design stages to optimize and define SIPI performance requirements, including bump mapping and power estimation.

Key responsibilities include:

• Designing and developing advanced silicon package solutions such as silicon interposers, RDL fanout packages, and silicon bridge packages.
• Modeling and analyzing advanced package designs to ensure optimal electrical, thermal, and mechanical performance.
• Representing Synopsys on business unit projects as a technical leader and subject matter expert in advanced packaging.
• Resolving a wide range of design and integration issues using creative, data-driven approaches.
• Supporting customer engagements in exploring and implementing advanced package solutions with Synopsys IPs.
• Collaborating with global teams to share best practices and drive innovation in advanced packaging methodologies.

The ideal candidate will have:

• Bachelor’s degree in Electrical or Electronic Engineering (Master’s or PhD preferred).
• Minimum of 10 years’ relevant experience in advanced package design, model extraction, and analysis.
• Expert knowledge of advanced circuit and transmission line theory.
• Hands-on experience with TSMC, Intel, Samsung, or OSAT advanced package technologies.
• Proficiency in multi-physics analysis (EMIR, Thermal, Thermal-Mechanical, Electromagnetic, etc.).
• Familiarity with both Windows and Linux operating systems.
• Experience with industry-standard EDA tools such as Cadence APD, Innovus, Integrity-3DIC, Synopsys ICC2, 3DIC Compiler, and Fusion Compiler.

Benefits include:

• Comprehensive medical and healthcare plans
• Time away programs
• Family support
• ESPP
• Retirement plans
• Competitive salaries

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Your expertise lies in the RTL2GDS flow, particularly in the complex area where verification meets implementation and theory meets timing closure. You are skilled in debugging complex place-and-route issues, timing convergence challenges, congestion problems, power optimization opportunities, and physical implementation bottlenecks using Fusion Compiler.

Responsibilities

• Support customers through physical design implementation and design closure using Synopsys tools.
• Debug complex design challenges across timing, power, area, congestion, routing, and runtime optimization at advanced process nodes including 5nm and below.
• Help customers achieve implementation closure while meeting aggressive tapeout schedules and design quality requirements.
• Provide technical guidance on best practices for synthesis, place-and-route, timing closure, power optimization, and advanced implementation methodologies.
• Build and maintain automation scripts in TCL to streamline workflows and improve turnaround time for customer engagements.
• Utilize AI-powered tools and workflows to improve productivity, accelerate issue resolution, and enhance customer support effectiveness.
• Collaborate with internal R&D teams to reproduce customer issues, validate tool behavior, and feed real-world use cases back into product development.
• Present technical solutions and recommendations to senior customer engineers and design leads during critical project phases.
• Work across the full RTL-to-GDS flow, from implementation through signoff and tapeout readiness.

The Impact You Will Have

• Enable customers to achieve first-pass silicon success on high-performance chips powering AI, automotive, networking, and mobile applications.
• Improve customer productivity by helping them maximize the value of Fusion Compiler and advanced implementation methodologies.
• Reduce customer tapeout risk by identifying and resolving implementation challenges early in the design cycle.
• Influence Synopsys tool development by bringing real customer pain points and use cases directly to engineering teams.
• Accelerate customer productivity through automation, AI-assisted workflows, and best-practice methodologies that become adopted across their organizations.
• Build long-term technical relationships with leading semiconductor companies in the region, becoming their trusted advisor for implementation and design closure challenges.
• Help shape how advanced-node designs are implemented by solving problems at the edge of what today's tools and methodologies can achieve.
• Strengthen Synopsys's reputation as the partner that shows up when the hard problems need solving.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with at least 5 years of hands-on ASIC, physical design, implementation, or CAD engineering experience.
• Direct experience with RTL-to-GDS implementation flows, including synthesis, place-and-route, timing closure, and physical design optimization.
• Strong working knowledge of Fusion Compiler, ICC2, or equivalent digital implementation tools.
• Understanding of timing, power, congestion, routing, and design closure methodologies.
• Working knowledge of Formality, PrimeTime, or related EDA tools is a strong advantage.
• Proficiency in scripting with TCL and Python to automate design tasks and improve workflow efficiency.
• Experience with advanced process nodes (7nm and below) is a strong plus, especially if you have worked through design closure challenges at those nodes.
• Demonstrated ability to leverage AI tools and automation technologies to improve engineering productivity and problem-solving effectiveness.
• Business-level English proficiency with the ability to communicate technical concepts clearly in written and spoken form.
• Willingness to engage directly with customers, including senior engineers and design managers, in both remote and onsite settings.

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You will be the technical owner for the AI tools our employees use every day, on every surface they ship on: chat assistants, desktop apps, coding agents, AI terminals, AI browsers, workplace knowledge tools, and whatever comes next.

Your responsibilities will include:

• AI platform lifecycle and governance: Own the end-to-end lifecycle of employee-facing AI platforms across every surface they ship on
• Guardrails as enforceable controls: Design and implement AI guardrails as enforceable controls, in partnership with Enterprise Security and IT Identity and Access
• Infrastructure you'll own: The IT-owned control layer for CoreWeave's internal chatbots and agents
• Operations, reliability, and telemetry: Hold the AI services you own to SRE standards

Requirements:

• 6+ years in software engineering, site reliability engineering, or IT systems engineering
• 2+ years of hands-on experience building with or administering LLM-based products
• Strong software engineering skills in Python, Go, Rust, or TypeScript
• Experience operating services in production
• A working understanding of how enterprise IT control systems function

Preferred qualifications:

• Real-world experience administering one or more of these at enterprise scale: identity, endpoint management, or SaaS platforms
• Experience deploying and governing enterprise AI tools across a 1,000+ person organization
• Hands-on experience building custom Model Context Protocol (MCP) servers and integrations

We offer a competitive salary range of $182,000 to $242,000, a discretionary bonus, equity awards, and a comprehensive benefits program.

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About the role: The Data Service Team serves as the experts on managing data infrastructures as services for CoreWeave. The data infra includes but is not limited to managed databases, data ingestion, data flow, and data lake and analysis for CoreWeave and its customers.

As a Senior Manager, Managed Databases, you will:

• Build a world-class engineering team by hiring and developing the best talent in the industry.
• Solve very hard system-level problems to run the world's most demanding and advanced AI workloads.
• Design and implement services to deliver data to teams with a focus on providing managed solutions through APIs.
• Improve the performance, security, reliability, and scalability of our data services.
• Establish guidelines and guardrails for data access and storage for stakeholder teams.
• Ensure compliance with standards for data protection regulation.
• Analyze telemetry and system data to drive improvements in throughput, latency, and resilience.
• Work cross-functionally with platform, product, and infrastructure teams to deliver seamless storage capabilities across the stack.

Requirements:

• 5+ years of experience managing or leading data service infra teams.
• 5+ years of hands-on software or infrastructure engineering.
• Understanding of one of the database internals: MySQL, PostgreSQL, Aurora, CockroachDB, TiDB, MongoDB, CosmosDB, Oracle, SQL Server, DB2, SAP.
• Hands-on background with cloud-native and separating compute from storage architecture.
• Expert on life of a query and life of a transaction.
• Experience operating services in production and at scale.
• Knowledge of reliability engineering concepts such as testing, progressive deployments, error budgets, observability, and fault-tolerant design.
• Understanding of CAP theorem and concurrency models.
• Familiarity with Kubernetes.

Benefits:

• Medical, dental, and vision insurance.
• 100% paid for by CoreWeave.
• Company-paid Life Insurance.
• Voluntary supplemental life insurance.
• Short and long-term disability insurance.
• Flexible Spending Account.
• Health Savings Account.
• Tuition Reimbursement.
• Ability to Participate in Employee Stock Purchase Program (ESPP).
• Mental Wellness Benefits through Spring Health.
• Family-Forming support provided by Carrot.
• Paid Parental Leave.
• Flexible, full-service childcare support with Kinside.
• 401(k) with a generous employer match.
• Flexible PTO.
• Catered lunch each day in our office and data center locations.
• A casual work environment.
• A work culture focused on innovative disruption.

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Your exceptional verbal and written communication skills allow you to effectively collaborate with customers, R&D teams, and engineering leadership. You are recognized for your expertise in one or more key technology domains and are frequently relied upon for technical guidance on challenging integration and deployment topics.

You are excited about working with Synopsys' UCIe (Universal Chiplet Interconnect Express) IP and the latest industry specifications/applications on various market segments. You are ready to provide technical leadership for complex customer deployments, contribute to integration methodologies and best practices, and help drive product improvements through deep understanding of customer requirements.

Responsibilities:

• Understand complex IIP applications across diverse customer SoCs, chiplet architectures, and system implementations.
• Stay at the forefront of evolving ASIC/SoC design methodologies, advanced process technologies, and EDA tools.
• Provide expert guidance on challenging IIP integration topics including simulation, synthesis, floor planning, STA, DFT, package integration, silicon bring-up, validation, and system-level deployment.
• Lead technical reviews for highly complex customer programs and critical integration milestones.
• Serve as a recognized subject matter expert in one or more technology domains and provide technical consultation to customers, AE teams, and R&D organizations.
• Partner closely with customer engineering leadership to resolve challenging integration and deployment issues.
• Collaborate with R&D teams to identify recurring customer challenges and recommend product enhancements that improve deployment success.
• Develop and promote technical methodologies, best practices, application notes, and deployment guidance across the Applications Engineering organization.
• Mentor and develop applications engineers across multiple projects and technology areas.
• Participate in R&D design reviews and contribute technical insights that help improve future product deployment success.

The Impact You Will Have:

• Enable successful deployment of Synopsys UCIe IP in some of the industry's most advanced ASIC and SoC designs.
• Help customers overcome highly complex integration and deployment challenges through deep technical expertise.
• Drive customer success across multiple programs by advancing integration methodologies and technical best practices.
• Influence future product enhancements by translating customer deployment experiences into actionable recommendations.
• Develop methodologies and best practices that improve customer success across multiple programs.
• Strengthen Synopsys' technical leadership in advanced interface IP through domain expertise and customer engagement.
• Accelerate development of the Applications Engineering organization through mentoring and technical leadership.
• Build long-term partnerships with customer technical leadership and contribute to sustained customer success.

Requirements:

• Bachelor's and/or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields.
• Typically requires at least 15 years of design, verification, implementation, validation, or applications engineering experience.
• Deep expertise in ASIC Front-End or Back-End development and advanced SoC integration.
• Recognized expertise in one or more domains such as UCIe, PCIe/CXL, high-speed interface integration, silicon validation, implementation, or post-silicon bring-up.
• Strong analytical, reasoning, and problem-solving skills.
• Proven verbal and written communication skills.
• Demonstrated ability to influence technical direction through customer deployment experience and technical leadership.

Preferred Experience:

• Extensive experience with advanced technology processes (10nm/7nm/5nm/3nm and beyond).
• Strong understanding of Die-to-Die, PCIe, CXL, and chiplet ecosystems.
• Advanced silicon debug, validation, and hardware troubleshooting experience.
• Broad knowledge of EDA methodologies including P&R, Physical Verification, Signal Integrity, and Power Integrity.

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Key Responsibilities:

• Lead formal verification methodology deployment at customer sites
• Assess customer design environments and identify high-value blocks for formal analysis
• Debug and resolve tool performance issues
• Develop and deliver technical training on VC Formal features and best practices
• Collaborate with Synopsys R&D and product engineering teams to communicate customer requirements
• Apply formal verification techniques across property checking, datapath verification, and sequential equivalence checking
• Serve as the technical bridge between customers and internal engineering

The Impact You Will Have:

• Enable customers to close verification gaps that simulation alone cannot reach
• Drive adoption of formal methodologies that become standard practice in customer verification flows
• Improve tool performance and usability through direct customer feedback
• Build customer confidence in formal verification by delivering measurable results
• Reduce verification cycle time for complex designs
• Influence product direction by bringing field insights back to R&D
• Strengthen customer relationships through technical credibility and responsiveness

Requirements:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience
• 6+ years of hands-on experience in formal verification
• Deep expertise with formal verification tools, ideally including VC Formal or equivalent platforms
• Strong understanding of SystemVerilog Assertions (SVA) and formal testbench modeling
• Proven ability to debug tool performance issues and optimize formal runs
• Experience working directly with customers or cross-functional engineering teams
• Solid grasp of RTL design, verification methodologies, and the semiconductor development lifecycle

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The marimo team develops marimo, an open-source reactive computational notebook for Python, and molab, a rapidly growing cloud-hosted notebook service.

As an Engineering Manager, you will mentor engineers, provide regular feedback, and help develop their careers, while also helping hire and onboard new teammates.

Key Responsibilities:

• Lead engineering execution across marimo's open-source ecosystem and molab
• Manage and mentor engineers, support their career development, and help hire and onboard new teammates
• Shape architecture and technical direction with engineers
• Evaluate community feature requests and balance user needs with long-term maintainability
• Lead improvements to engineering productivity and software quality
• Establish clear ownership and practices for molab's production reliability

Qualifications:

• 5+ years of software engineering experience
• 2+ years of engineering management experience
• Proficient in Python
• Experience contributing to open-source projects
• Technical depth to lead design and architecture reviews

Preferred Skills:

• Experience maintaining and growing a widely used open-source project
• Experience building developer tools, especially for AI, ML, or data
• Familiarity with observability platforms, Kubernetes, and modern CI/CD practices

The base salary range for this role is $182,000 to $242,000.

Benefits include medical, dental, and vision insurance, company-paid life insurance, flexible spending account, health savings account, tuition reimbursement, and more.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

Responsibilities:

• Engage directly with customers to understand requirements, anticipate market shifts, identify future design trends, capture high-value problems, and translate them into comprehensive Marketing Requirements Documents (MRDs).
• Collaborate closely with product managers to identify and define new technologies, flows, and products to drive sustainable growth within the product line.
• Assimilate customer requirements, technology trends, and competitive intelligence to shape product roadmaps.
• Create compelling customer presentation materials to effectively communicate Synopsys’ technical value.
• Curate material describing customer use-cases to influence timing signoff roadmap and create differentiation.
• Conduct comparative studies of the product line against competitors and customer requirements.
• Analyze wins and losses technically to enhance future product offerings.
• Facilitate field communication and training sessions.
• Lead technical discussions in Standards bodies and partnerships with foundry vendors.
• Promote product lines through articles, white papers, application notes, seminars, and industry events.
• Produce thought leadership outbound collateral.
• Work closely with sales, engineering, and application engineering teams to communicate technical benefits and understand customer needs.
• Serve as a recognized expert and role model in the field, representing Synopsys internally and externally.

The Impact You Will Have:

• Drive the strategic direction and roadmap for the timing signoff product line and ensure Synopsys remains the thought and market leader in this domain.
• Contribute to the growth and sustainability of the product line through innovative technology definitions.
• Enhance customer satisfaction by translating their high-value problems into actionable product features.
• Strengthen Synopsys’ market position through effective communication and promotion of technology benefits.
• Foster strong, collaborative relationships with key customers, partners, and internal teams.
• Accelerate customer outcomes by delivering sustainable, differentiated product technologies that address real-world challenges.
• Foster a culture of collaboration, innovation, and continuous improvement across multi-disciplinary teams.
• Enable rapid adoption of new signoff technologies through compelling technical campaigns and beta programs.
• Expand the company’s reach via strategic partnerships and ecosystem development.
• Elevate customer satisfaction through tailored solutions and proactive engagement.

Requirements:

• 20+ years of relevant experience in technical field/product support or technical product management, ideally in EDA or semiconductor industries.
• Bachelor’s degree in electrical engineering (BS EE) or equivalent technical discipline.
• Deep expertise in static timing analysis, multidie signoff, and constraints management.
• Proven experience in one or more domains: Signoff, Digital Design/Implementation, Verification.
• Demonstrated ability to negotiate, influence, and lead in a matrixed organization.
• Exceptional written, verbal, presentation, and public-speaking skills.

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Responsibilities:

• Partner with cross-functional engineering, product, and business teams to define project scope, requirements, and success criteria.
• Develop and maintain comprehensive project plans, including schedules, resource allocation, dependencies, and risk mitigation strategies.
• Track project execution against plan, proactively identify risks and issues, and drive mitigation, escalation, and resolution.
• Communicate project status, milestones, and key risks to internal stakeholders and senior leadership with clarity and transparency.
• Represent R&D in customer engagements, ensuring alignment on commitments, execution plans, and delivery expectations.
• Evaluate and manage change requests and technical issues reported by customers, coordinating timely and effective responses.
• Manage product updates triggered silicon process updates, design updates, and customer feedback
• Collaborate closely with Sales, Marketing, Customer Support, and IP Program Management teams during pre-sales and post-sales activities.
• Ensure adherence to quality management system processes and drive continuous improvement in project execution.
• Mentor and guide team members, fostering a collaborative, accountable, and innovative working environment.

The Impact You Will Have:

• Enable the successful delivery of complex engineering programs on time, within scope, and within budget.
• Improve product quality, performance, and reliability, driving higher customer satisfaction and long-term partnerships.
• Establish and refine project management best practices that increase execution predictability and efficiency.
• Strengthen cross-functional alignment and collaboration across engineering, business, and customer-facing teams.
• Support the growth and evolution of the Synopsys IP and product portfolio by aligning technical execution with strategic business objectives.
• Reinforce Synopsys’ reputation as a technology leader through excellence in delivery, innovation, and customer impact.

Requirements:

• A degree in Engineering, Applied Science, or equivalent practical experience.
• 10+ years of experience in customer-facing project or program management roles within an engineering environment.
• Strong ability to manage customer expectations and communicate complex technical topics clearly and concisely.
• Proficiency with project management tools (MS Project preferred) and issue-tracking systems such as Jira.
• Working knowledge of UNIX/Linux environments.
• Familiarity with the development process for Mixed-Signal IP, SoC, or ASIC development programs.
• Understanding of quality management system (QMS) processes and procedures.
• Excellent organizational, time-management, and prioritization skills, with the ability to manage multiple concurrent projects.

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The Customer Experience (CX) Organization at CoreWeave is dedicated to ensuring every client running AI workloads at scale has a seamless, reliable, and high-performance experience. This team supports the infrastructure that powers the AI revolution,working across data centers, hardware systems, and customer workloads to maintain the integrity of our cloud platform.

As a Technical Support Engineer, you will be responsible for supporting, operating, and maintaining CoreWeave’s extensive GPU fleet across our growing data centers in the U.S., Europe, and beyond. You will work closely with customers, data center technicians, and engineering teams to ensure the reliability, performance, and scalability of our infrastructure.

Responsibilities:

• Provide high-level support for customers utilizing bare-metal GPU fleets on CoreWeave Cloud.
• Diagnose, triage, and investigate reported customer issues and high-priority incidents, identifying root causes and escalating when necessary.
• Develop a deep understanding of customer workloads and use cases to provide tailored technical support.
• Coordinate remote troubleshooting and hardware interventions with Data Center Technicians.
• Create and maintain internal documentation, including troubleshooting guides, best practices, and knowledge base articles.
• Participate in an on-call rotation to support production clusters and ensure operational reliability.
• Collaborate with engineering teams to improve hardware reliability, software stability, and system performance.
• Implement automation and scripting to streamline support workflows and reduce manual interventions.
• Perform in-depth log analysis and debugging across multiple layers of the stack (firmware, drivers, hardware).
• Provide feedback to internal teams on common support issues to drive continuous improvements.
• Work with networking teams to troubleshoot connectivity issues affecting customer workloads.
• Support supercomputing infrastructure running GPU workloads at scale.
• Drive operational excellence by refining internal processes and support methodologies.

Requirements:

• Experience in data centers, GPU clusters, server deployments, system administration, or hardware troubleshooting.
• Demonstrated experience driving resolutions and continuous improvements across cross-functional environments and teams within a data center environment.
• Intermediate knowledge of Linux (Ubuntu, CentOS, or similar), including command-line proficiency.
• Experience with NVIDIA GPUs, SuperMicro systems, Dell systems, high-performance computing (HPC), and large-scale data center environments.
• Experience in networking fundamentals (TCP/IP, VLANs, DNS, DHCP) and troubleshooting tools.
• Hands-on experience with firmware updates, BIOS configurations, and driver management.
• Experience analyzing system logs and debugging issues across firmware, drivers, and hardware layers.
• Experience working with Jira, Confluence, Notion, or other issue-tracking and documentation platforms.
• Experience in scripting and automation (Python, Bash, Ansible, or similar).

Nice to Have:

• Curiosity about Kubernetes, Docker, and containerized infrastructure.
• Strong problem-solving skills with a proactive and analytical mindset.
• Excellent communication skills and a demonstrated ability to work collaboratively in a fast-paced environment.

What We Offer:

• Base salary range: $99,000 to $132,000.
• Comprehensive benefits program, including medical, dental, and vision insurance, company-paid Life Insurance, short and long-term disability insurance, flexible spending account, health savings account, tuition reimbursement, employee stock purchase program, mental wellness benefits, family-forming support, paid parental leave, flexible childcare support, 401(k) with a generous employer match, flexible PTO, catered lunch, and a casual work environment.

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As a Principal Solution Specialist for Infrastructure, you design the frameworks that govern how CoreWeave structures large infrastructure commitments, negotiate the commercial terms that create durable value for both sides, and build the playbooks and processes the field team relies on to win.

Responsibilities:

• Own the end-to-end commercial and operational lifecycle of CoreWeave's most complex infrastructure deals globally, from initial deal architecture through term negotiation, contract execution, and account expansion.
• Structure and close large-scale infrastructure commitments, from long-term compute and networking agreements to fully integrated AI platform deals, in close coordination with sales, legal, finance, and product teams across CoreWeave.
• Design deal frameworks, pricing models, and term structures that reflect what AI companies actually need to build at scale, balancing customer requirements around resource access, cost predictability, and operational flexibility with CoreWeave's commercial objectives.
• Own the deal desk function for infrastructure commitments, providing real-time deal guidance, commercial structuring support, and pricing alignment to the field team across active opportunities globally.
• Enable the sales and solutions architecture organizations with infrastructure deal playbooks, term negotiation frameworks, TCO models, and competitive positioning materials that accelerate large infrastructure closings.
• Engage directly with customer procurement, legal, and executive leadership as CoreWeave's primary commercial voice in complex, multi-stakeholder infrastructure negotiations.
• Partner with product specialists across Core Services, AI Runtime, AI Developer Services, and Data Services to build integrated deal proposals that reflect the full value of CoreWeave's infrastructure platform.
• Serve as the field's primary intelligence source on how AI companies across industries and company stages think about and consume infrastructure, translating customer conversations into direct input for CoreWeave's product, engineering, capacity planning, finance, and marketing teams.
• Drive operational improvements in how CoreWeave manages large infrastructure deal cycles, including pipeline visibility, deal review cadences, escalation paths, and post-signature execution handoffs, to support a growing global field organization.

Requirements:

• 10+ years of experience in enterprise infrastructure sales, deal structuring, or commercial operations at a cloud provider, hyperscaler, data center operator, or large-scale technology vendor, with a track record of closing large, complex deals.
• 5+ years owning or shaping the commercial structure of large infrastructure commitments, including cloud compute agreements, GPU infrastructure contracts, data center agreements, or equivalent, spanning term negotiation, pricing strategy, and contract execution in a customer-facing capacity.
• Deep understanding of how AI companies, from startups building their first production systems to enterprises scaling global AI deployments, evaluate, procure, and operationalize infrastructure, including the technical, financial, and organizational dynamics that drive those decisions across industries.
• Fluency across CoreWeave's infrastructure portfolio, GPU compute, high-performance networking, storage, and Kubernetes platform, and strong working knowledge of how these components combine into integrated infrastructure commitments for AI customers.

Benefits:

• Medical, dental, and vision insurance
• 100% paid for by CoreWeave
• Company-paid Life Insurance
• Voluntary supplemental life insurance
• Short and long-term disability insurance
• Flexible Spending Account
• Health Savings Account
• Tuition Reimbursement
• Ability to Participate in Employee Stock Purchase Program (ESPP)
• Mental Wellness Benefits through Spring Health
• Family-Forming support provided by Carrot
• Paid Parental Leave
• Flexible, full-service childcare support with Kinside
• 401(k) with a generous employer match
• Flexible PTO
• Catered lunch each day in our office and data center locations
• A casual work environment
• A work culture focused on innovative disruption

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You will help customers integrate UCIe IP throughout the SoC flow and support silicon and system bring-up. Some travel is required.

Responsibilities:

• Understand IIP applications within customer-specific SoCs and systems, and provide expert guidance to configure, integrate, and resolve challenges across simulation, synthesis, floor planning, STA, DFT, silicon bring-up, and system integration
• Lead customer integration reviews, support major SoC milestones, and drive root-cause analysis and resolution for complex technical issues
• Partner with R&D teams to develop application notes, improve deployment methodologies, and participate in design reviews that align future development with customer needs and deployment learnings
• Build trusted relationships with customer engineering teams and influence technical implementation decisions

The Impact You Will Have:

• Drive successful integration and deployment of Synopsys UCIe IP across complex ASIC and SoC programs while helping customers accelerate adoption and overcome critical integration challenges
• Build trust with customer engineering teams through technical leadership, consistent execution, and strong methodology guidance
• Influence product quality, usability, and long-term customer success through actionable feedback from customer deployments

Requirements:

• BSEE, BSCE, BSCS or MSEE, MSCE, MSCS degree plus 8 years of experience in design, verification, implementation, validation, applications engineering, or a related field, along with hands-on experience in ASIC Front-End or Back-End development
• Demonstrated ability to independently lead customer technical discussions and engagements, with domain knowledge in die-to-die and PCIe/CXL protocol
• Silicon, FPGA, or hardware debug and troubleshooting experience, plus knowledge of advanced EDA tools and expertise in place-and-route, physical verification, signal integrity, or power integrity
• Experience with mixed-signal IP or circuit design; experience with advanced technology nodes such as 10nm, 7nm, 5nm, or 3nm is a plus

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As an Applications Engineering, Staff Engineer, you will lead technical engagements throughout the sales cycle, working directly with semiconductor and electronics packaging engineers to understand their design problems and configure simulation solutions using Ansys tools.

Your responsibilities will include:

• Leading technical engagements throughout the sales cycle, from discovery calls to live demos
• Working directly with semiconductor and electronics packaging engineers to understand their design problems
• Configuring, scripting, and deploying simulation solutions using Ansys tools
• Building Python-based automation scripts and custom workflows using Ansys APIs
• Collaborating with Ansys product teams to translate customer feedback into feature requests
• Delivering consulting services and training sessions to help customers get value from day one
• Supporting field marketing efforts by authoring technical content and presenting at industry conferences

You will have the opportunity to make a significant impact, including:

• Helping customers close design cycles faster with simulation workflows that work in their environment
• Enabling sales teams to win competitive opportunities with solutions that address specific customer failure modes
• Influencing product teams to build features that matter through customer requirements and testing
• Increasing trust in simulation among engineers at semiconductor and electronics companies
• Expanding Synopsys' footprint in electronics packaging and semiconductor reliability

To succeed in this role, you will need:

• A BS in Mechanical Engineering or related field with 5+ years in an engineering software environment, or MS with 3+ years, or PhD with industry exposure to structural, thermal, or reliability simulation
• Deep subject matter expertise in structural mechanics applied to electronics or semiconductor domains
• Hands-on experience with Ansys software or other commercial CAE tools
• Strong Python scripting skills with demonstrated experience building automation workflows
• Ability to diagnose complex simulation problems and communicate technical tradeoffs clearly
• Willingness to travel domestically up to 25% of the time for customer meetings and industry events

In return, we offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

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Your expertise lies in turning ambiguity into action, knowing the difference between a program that runs itself and one that needs constant rescue. You excel at creating mechanisms that let others do their best work, such as reviewing decisions, tracking progress, and aligning leaders.

Key responsibilities include:

• Owning the full lifecycle of strategic programs across IPG and SSG
• Running the operating rhythm of the Executive Office, including reviews, meetings, and business updates
• Building and maintaining dashboards, status reports, and executive summaries
• Preparing leadership for reviews and planning cycles
• Driving cross-functional action items to closure
• Improving office operations and mentoring junior program managers

In this role, you will have a significant impact by:

• Enabling leadership decisions with timely and accurate information
• Ensuring cross-organizational commitments are met
• Providing consistent and accurate reporting
• Mentoring junior program managers and coordinators

Requirements include:

• Bachelor's degree or equivalent practical experience
• 5+ years in program management, project management, or business operations
• Strong written communication skills and sound judgment
• Proficiency with Microsoft 365 and program management tools

Preferred qualifications include:

• 8+ years of program management or operations experience
• Experience supporting an executive staff in a large engineering or technology organization
• Hands-on use of program management tools like Jira, Smartsheet, Asana, or MS Project
• Semiconductor, EDA, or silicon IP background

We offer a comprehensive range of health, wellness, and financial benefits.

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You have spent years in the trenches of physical design, not just running tools but understanding why a clock tree converges or falls apart, why congestion shows up in one corner and not another, and what it actually takes to close timing at 3nm when the margin for error is measured in picoseconds.

Responsibilities

• Support pre-sales and post-sales engagements with semiconductor customers, demonstrating Synopsys physical design tools including Fusion Compiler and ICC2 in live technical sessions
• Debug complex physical design issues across the RTL-to-GDSII flow, working directly with customer design teams to resolve placement, routing, timing closure, and congestion challenges at advanced nodes
• Develop and deliver technical methodologies for clock tree synthesis, AI-driven optimization, macro placement, and timing closure that customers can adopt in production flows
• Build proof-of-concept designs and benchmarks that show measurable PPA improvements using Synopsys tools compared to customer baseline flows
• Collaborate with product engineering teams to translate customer pain points into feature requests, tool enhancements, and methodology improvements
• Train customer engineers on advanced Synopsys tool capabilities, from multi-scenario optimization to noise-aware routing techniques
• Travel to customer sites to provide hands-on technical support during critical project phases, including tape-out preparation and bring-up

The Impact You Will Have

• Accelerate customer adoption of Synopsys tools, directly contributing to revenue growth and competitive wins in key accounts
• Help customers achieve measurable improvements in PPA (power, performance, area) and reduce their time to tape-out by weeks or months through better methodologies
• Influence the product roadmap by surfacing real-world customer challenges that shape the next generation of Fusion Compiler and ICC2 capabilities
• Build long-term technical relationships with leading semiconductor companies, becoming the trusted expert they call when a design is stuck
• Enable customers to successfully adopt advanced node technologies (5nm, 3nm, and beyond) where traditional methodologies break down
• Expand Synopsys footprint within accounts by demonstrating value across multiple design teams and product lines
• Contribute to the technical reputation of Synopsys in the industry through customer success stories, white papers, and conference presentations

Requirements

• Bachelor's degree in Electrical Engineering or equivalent with 9+ years of hands-on ASIC physical design experience, or Master's degree with 7+ years
• Deep expertise in RTL-to-GDSII flows using industry-standard tools, with direct experience in placement, optimization, clock tree synthesis, and routing
• Hands-on proficiency with Synopsys backend tools including Fusion Compiler, ICC2, Design Compiler, and PrimeTime
• Strong understanding of advanced node design challenges (7nm and below), including FinFET effects, multi-patterning constraints, and electromigration
• Experience with timing closure techniques, multi-scenario optimization, and noise analysis in complex SoC designs
• Knowledge of clock tree synthesis methodologies including H-Tree and multi-source CTS is a strong plus
• Willingness to travel up to 30% to customer sites for technical engagements and on-site support

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You will support Interface IP customers with integration across the SoC design flow, provide technical guidance to resolve integration, implementation, and debug challenges, and assist with technical reviews at key milestones.

Your responsibilities will include:

• Supporting Interface IP customers with integration across the SoC design flow
• Providing technical guidance to help resolve integration, implementation, and debug challenges
• Assisting with technical reviews at key milestones and helping customers work through issues efficiently
• Supporting silicon and system bring-up, including hands-on debug of critical issues
• Partnering with R&D, product teams, and field teams to deliver solutions aligned to customer requirements
• Staying current on evolving industry standards, protocol requirements, and application trends across key market segments
• Supporting customer engagements through occasional travel, including on-site technical collaboration and bring-up activities

The impact you will have includes:

• Helping customers successfully integrate Synopsys Interface IP into complex SoC designs
• Reducing technical obstacles by providing practical support across important design and bring-up stages
• Strengthening customer confidence through responsive technical partnership and effective problem-solving
• Contributing to successful product deployment across next-generation designs using advanced interface IP
• Supporting Synopsys’ reputation as a trusted partner in engineering solutions from silicon to systems

To qualify, you will need:

• BSEE/BSCE or MSEE/MSCE with 10+ years of experience, or equivalent experience with a focus on VLSI design
• Experience in design, verification, or application engineering
• Proficiency in RTL coding using Verilog and/or VHDL
• Experience with high-speed protocols such as Ethernet, DDR, and PCIe
• Hands-on experience with simulation, synthesis, and static timing analysis
• Familiarity with UNIX environments and ASIC/SoC tape-out processes
• Knowledge of CDC, RDC, lint, DFT, STA, and LEC is a plus

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

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You will be supporting Interface IP customers with integration across the SoC design flow, providing technical guidance to help resolve integration, implementation, and debug challenges.

Responsibilities:

• Supporting Interface IP customers with integration across the SoC design flow
• Providing technical guidance to help resolve integration, implementation, and debug challenges
• Assisting with technical reviews at key milestones and helping customers work through issues efficiently
• Supporting silicon and system bring-up, including hands-on debug of critical issues
• Partnering with R&D, product teams, and field teams to deliver solutions aligned to customer requirements
• Staying current on evolving industry standards, protocol requirements, and application trends across key market segments
• Supporting customer engagements through occasional travel, including on-site technical collaboration and bring-up activities

The Impact You Will Have:

• Helping customers successfully integrate Synopsys Interface IP into complex SoC designs
• Reducing technical obstacles by providing practical support across important design and bring-up stages
• Strengthening customer confidence through responsive technical partnership and effective problem-solving
• Contributing to successful product deployment across next-generation designs using advanced interface IP
• Supporting Synopsys’ reputation as a trusted partner in engineering solutions from silicon to systems

Requirements:

• BSEE/BSCE or MSEE/MSCE with 6+ years of experience, or equivalent experience with a focus on VLSI design
• Experience in design, verification, or application engineering
• Proficiency in RTL coding using Verilog and/or VHDL
• Experience with high-speed protocols such as Ethernet, DDR, and PCIe
• Hands-on experience with simulation, synthesis, and static timing analysis
• Familiarity with UNIX environments and ASIC/SoC tape-out processes
• Knowledge of CDC, RDC, lint, DFT, STA, and LEC is a plus

Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

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You have spent years verifying silicon that cannot afford to fail in production, and you understand that catching the corner case at RTL saves months of pain downstream. The difference between a testbench that looks good in review and one that finds bugs is something you feel in your gut after running thousands of simulations and debugging failures that made no sense until they suddenly did.

Responsibilities

• Define and track verification test plans for DDR PHY and memory subsystem IP blocks, translating architecture specs into executable verification strategies
• Design and write constrained-random System Verilog testbenches using UVM, building reusable verification components that scale across product families
• Write System Verilog assertions and functional coverage models to close coverage gaps and catch protocol violations
• Debug RTL and gate-level simulation failures, working with design engineers to root-cause issues in complex memory interface logic
• Perform code coverage analysis and drive coverage closure, identifying untested paths and corner cases that matter
• Mentor verification engineers earlier in their careers, reviewing test benches, debugging strategies, and verification plans
• Integrate AI-assisted verification tools and workflows into the team's methodology

The Impact You Will Have

• Your test plans and coverage models will directly determine whether critical bugs are caught before tape out or discovered in silicon
• The UVM environments you build will be reused across multiple product generations, shaping how the team verifies memory IP for years
• Your debugging work will uncover RTL issues that would have caused customer re-spins, saving months of schedule and millions in mask costs
• The assertions and coverage you write will become the safety net that catches regressions as the design evolves
• Your mentorship will accelerate how quickly new engineers become productive contributors
• The verification strategies you define will influence how Synopsys memory IP is validated across the product portfolio

Requirements

• Bachelor’s degree in electrical engineering or computer engineering with 8+ years of hands-on ASIC verification experience
• Deep proficiency in UVM methodology and System Verilog, you have built test benches that found bugs
• Understanding of DDR memory architecture and DDR PHY design, including timing, training, and calibration flows
• Knowledge of DFI protocol, memory controllers, or memory subsystem integration, preferred
• Solid scripting ability in Perl or Python for automation, result parsing, and flow development
• Proven debugging skills across RTL and gate-level simulations
• Experience with AI-assisted verification tools and workflows is a plus

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Responsibilities:

• Developing and maintaining SerDes system models for PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.
• Running comprehensive system simulations to verify and sign-off design performance across multiple protocols and channels.
• Designing and proposing advanced algorithms to calibrate and adapt transceivers for optimal performance.
• Correlating simulated performance with silicon measurements to ensure accuracy and reliability.
• Providing expert assistance to customers for system-level performance issues and troubleshooting.
• Collaborating with cross-functional teams of analog, digital, and hardware engineers throughout all stages of development and post-silicon.
• Contributing to lab testing and analysis for high-speed serial links, ensuring robust design validation.

Requirements:

• M.Sc. or Ph.D. in Electrical or Computer Engineering with 13+ years of relevant experience.
• Strong experience modeling circuits and systems in MATLAB/Simulink.
• Solid understanding of DSP and communications theory, including equalization, encoding, and noise/crosstalk filtering.
• Proficiency in analyzing link budgets for PAM4 high-speed serial links.
• Experience with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).
• Experience with circuit topologies used in high-speed SerDes Tx/Rx and Tx/Rx equalization techniques.
• Hands-on lab testing for high-speed serial links and proficiency in C/Verilog-A/system Verilog. Programming in Python is a plus.

Benefits:

• Comprehensive medical and healthcare plans that work for you and your family.
• Time away programs, including ETO and FTO.
• Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
• ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
• Retirement plans that vary by region and country.
• Competitive salaries.

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You will size addressable markets, track competitive share, and surface the account- and buyer-level signals that tell sales and marketing exactly where to focus.

Key Responsibilities

• Design, implement, and analyze results from brand, audience, and customer research programs, translating findings into actionable insights.
• Develop research and measurement frameworks for new / emerging audience and platform discovery channels, including Generative AI / LLMs.
• Develop and drive ongoing maintenance and validation of the Total Addressable Market (TAM), Serviceable Addressable Market (SAM), aligned with CoreWeave's target segments.
• Track market share against key competitors to inform competitive positioning, market prioritization, and go-to-market strategy.
• Identify buyer groups by use case , the personas with the greatest purchase influence over AI workload spend , and translate market-level insight into actionable targeting criteria.
• Partner with Brand, Product Marketing, and Product Engineering to scale competitive insights across the organization.
• Disseminate actionable segment / account signals to DG, Field Mktg, and Sales.
• Deliver periodic segment and TAM updates via dashboards, and push account targeting signals into marketing automation and CRM platforms.
• Drive adoption of ongoing market intelligence across campaign teams to inform GTM strategy and decision-making.

Qualifications & Skills

Must-have:

• Marketing strategy and GTM strategy experience in a B2B environment.
• Executive-level narrative development with synthesis of insights and recommendations.
• Market intelligence and competitive intelligence expertise.
• Survey-based and hypothesis-based research methodologies.
• Econometric modeling, planning, and forecasting experience.
• Vendor management across the research/intel portfolio.

Nice to have:

• Dashboard visualization design, prototyping, and development.

How Success Is Measured

You will be an integral driver of growth for CoreWeave’s growth by:

• Enhancing CoreWeave brand awareness and consideration vs. competitors.
• Driving revenue growth by prioritizing segments for sales and marketing focus.
• Accelerating targeting by identifying accounts and prospects that are ready to buy.
• Enabling decision making through adoption of actionable insights from qualitative and quantitative surveys and research.

The base salary range for this role is $161,000 to $215,000.

What We Offer

In addition to base salary, our total rewards package includes a discretionary bonus, equity awards, and a comprehensive benefits program.

Benefits include:

• Medical, dental, and vision insurance - 100% paid for by CoreWeave
• Company-paid Life Insurance
• Voluntary supplemental life insurance
• Short and long-term disability insurance
• Flexible Spending Account
• Health Savings Account
• Tuition Reimbursement
• Ability to Participate in Employee Stock Purchase Program (ESPP)
• Mental Wellness Benefits through Spring Health
• Family-Forming support provided by Carrot
• Paid Parental Leave
• Flexible, full-service childcare support with Kinside
• 401(k) with a generous employer match
• Flexible PTO
• Catered lunch each day in our office and data center locations
• A casual work environment
• A work culture focused on innovative disruption

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Your expertise in physical design will help customers achieve PPA targets on advanced node designs. You will debug complex physical design issues, develop methodology recommendations, and collaborate with R&D, product management, and field teams to drive product adoption.

Key responsibilities include:

• Supporting customer engagements on Synopsys physical design tools
• Debugging complex physical design issues across the RTL-to-GDS flow
• Developing and delivering methodology recommendations tailored to customer design constraints
• Running benchmarks and proof-of-concept flows to demonstrate tool capabilities
• Collaborating with R&D, product management, and field teams to translate customer pain points into product requirements
• Presenting technical content to customer engineering teams and management
• Traveling to customer sites as needed to provide onsite support, training, and design reviews

The impact you will have includes:

• Accelerating customer tapeout schedules through targeted methodology improvements and tool optimization strategies
• Enabling successful adoption of Synopsys tools at key accounts
• Shaping product roadmaps by surfacing real-world customer challenges and advanced node requirements
• Building deep technical relationships with leading semiconductor companies
• Reducing customer support escalations by proactively addressing methodology gaps
• Contributing to the success of chips that will ship in millions of devices

Requirements:

• Bachelor's degree in Electrical Engineering or equivalent with 7+ years of hands-on ASIC physical design experience, or Master's degree with 5+ years
• Deep experience with RTL-to-GDS flows using industry-standard tools
• Strong working knowledge of Synopsys backend tools, specifically Fusion Compiler or ICC2
• Proficiency with static timing analysis tools, particularly PrimeTime
• Solid understanding of advanced node design challenges at 7nm and below
• Experience with logical and physical synthesis flows and AI-driven methodologies for optimization
• Excellent communication skills with the ability to present technical concepts clearly

Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

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As a Senior Staff Network Engineer, you will apply your expertise to a global network infrastructure that supports semiconductor innovation and AI-driven workloads across a 30,000-person organisation.

Responsibilities

• Design and architect enterprise network solutions across LAN, WAN, data center, wireless, and security infrastructure that support a global workforce and AI-driven workloads
• Deploy, configure, and troubleshoot production network infrastructure using Cisco, Aruba, Versa, Palo Alto Networks, and Zscaler platforms in multi-site environments
• Build and maintain automation workflows using Python, Ansible, Terraform, and REST APIs to standardise configurations, reduce manual intervention, and improve deployment speed
• Lead the implementation of SD-WAN, EVPN/VXLAN, and DMVPN architectures to optimise connectivity and scalability across distributed sites
• Monitor network performance and security posture, analyse packet captures to diagnose latency, packet loss, and application-layer issues, and drive resolution
• Develop and maintain network documentation including architecture diagrams, configuration standards, security policies, and operational runbooks
• Mentor network engineers and cross-functional IT teams, sharing knowledge on complex protocols, troubleshooting techniques, and automation best practices

The Impact You Will Have

• Enable seamless global connectivity and secure access for 30,000 employees, ensuring the network infrastructure scales with business growth and AI infrastructure demands
• Reduce network incidents and mean time to resolution by implementing proactive monitoring, automation-driven deployments, and standardised configurations
• Accelerate deployment cycles by building reusable automation frameworks that eliminate manual configuration errors and improve consistency across environments
• Strengthen security posture by designing and enforcing network segmentation, zero-trust access policies, and firewall rules that protect critical IP and customer data
• Improve network observability and troubleshooting speed by implementing AI-driven analytics and telemetry tools that surface issues before they impact users
• Drive a culture of continuous learning and technical excellence within the network team, raising the bar for how problems are solved and knowledge is shared
• Align network strategy with business objectives, ensuring infrastructure investments support product development velocity and operational resilience

Requirements

• Bachelor's degree in Computer Science, Information Technology, Engineering, or equivalent practical experience
• 8+ years of hands-on network engineering experience, with several years in a senior or architecture-focused role designing and supporting large-scale enterprise networks
• Expert-level knowledge of routing and switching protocols including BGP, OSPF, EIGRP, EVPN/VXLAN, SD-WAN, and MPLS in multi-vendor environments
• Deep experience with network security technologies and protocols including IPSec, IKE, GRE, TACACS, RADIUS, 802.1x, NAC, and EAP-TLS
• Proficiency with network automation and configuration management tools such as Python, Ansible, Terraform, OpenStack, and REST APIs
• Extensive hands-on experience deploying and troubleshooting Cisco routing/switching, Aruba wireless, Palo Alto firewalls, and Zscaler secure access platforms
• Strong packet analysis skills using tools like Wireshark or tcpdump to diagnose root causes of performance degradation, latency, or connectivity failures
• Understanding of AI and machine learning concepts as they apply to network operations, including familiarity with AI-driven anomaly detection, predictive analytics for capacity planning, and how large language models can assist with configuration generation and troubleshooting workflows
• Certifications such as PCNSE, ZIA/ZPA, CCNP, CCIE, CISSP, or equivalent work experience are a strong plus

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You will define and maintain enterprise architecture blueprints for GenAI, Agentic AI, and Infrastructure solutions.

Key responsibilities include:

• Architecting large-scale GenAI and agentic AI platforms to ensure scalability, reliability, security, and extensibility.
• Evaluating and guiding the adoption of emerging AI, infrastructure, and platform technologies.
• Driving architectural alignment across business units to minimize fragmentation and technical debt.
• Collaborating closely with product and business teams to translate requirements into technical architectures.
• Providing architectural oversight for critical programs, high-risk initiatives, and flagship customer deployments.
• Establishing and reviewing security, compliance, and governance architectures for AI and infrastructure platforms.
• Partnering with external vendors and hyperscalers to shape joint technical roadmaps and integrations.
• Authoring and reviewing architecture decision records and technical strategy documents that guide long-term execution.
• Mentoring and elevating senior and principal architects, fostering a culture of technical excellence.

The impact you will have includes:

• Enabling scalable and repeatable AI platform adoption across the enterprise.
• Reducing technical risk and architectural fragmentation through clear standards and governance.
• Accelerating time-to-market via reusable, well-architected infrastructure and AI foundations.
• Improving platform reliability, security, and performance for mission-critical AI workloads.
• Enhancing developer productivity and innovation velocity through strong architectural enablement.
• Strengthening customer confidence by ensuring robust, enterprise-grade AI solutions.
• Influencing strategic technology investments with long-term architectural foresight.
• Elevating overall engineering quality by mentoring senior technical talent.
• Supporting revenue growth by enabling AI-driven products and differentiated capabilities.
• Positioning Synopsys as a technical leader in agentic AI and infrastructure architectures.

Requirements:

• Recognized expertise in AI and agentic platforms, infrastructure-native architecture, and distributed systems.
• Deep knowledge of GenAI, LLMs, agentic AI patterns, and AI system design.
• Proven ability to design and influence enterprise-scale architectures across multiple teams or business units.
• Strong understanding of security, compliance, and governance in infrastructure and AI systems.
• Exceptional communication skills, with the ability to explain complex technical concepts to executive audiences.
• Demonstrated thought leadership through architecture reviews, technical publications, or patents.
• Experience working with hyperscalers, AI vendors, and strategic partners.
• Strong systems thinking and long-term architectural mindset.
• Track record of mentoring senior engineers and architects.
• Typically, 15+ years of experience in software engineering, architecture, or platform development.
• 8+ years designing and delivering large-scale infrastructure-native systems.
• Significant hands-on experience with AI/ML platforms and GenAI systems.
• Prior experience as a Principal Architect, Senior Architect, or equivalent technical leadership role.
• Demonstrated ownership of enterprise-critical platforms or architectures.
• Experience supporting both internal platforms and external/customer-facing systems.
• History of influencing cross-functional and multi-organization technical initiatives.
• Experience operating in complex, highly regulated, or high-availability environments.
• Exposure to multi-infrastructure or hybrid architectures.
• Consistent record of delivering long-term technical impact beyond individual projects.

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What You'll Do

As a Senior Specialist Field Engineer - SaaS, you will work closely with Sales, Support, Product, and Engineering to ensure customers get lasting value out of the CoreWeave SaaS platform. Your responsibilities will include:

• Teaching the field team about the platform through workshops, playbooks, and demo guides.
• Designing and running hands-on workshops for customers, focusing on architecture reviews and feature adoption.
• Building reusable accelerators such as reference architectures, sample code, and demo environments.
• Providing technical expertise during high-priority customer engagements.
• Contributing to the product through examples, integrations, and bug fixes.
• Helping customers design, test, and troubleshoot integrations with the SaaS platform.

Who You Are

• 3+ years of experience in a similar customer-facing technical role.
• Proficient in Python and comfortable with coding in front of customers.
• Hands-on experience with Docker, Kubernetes, and Infrastructure-as-Code tools like Terraform.
• Solid experience with at least one major cloud platform (AWS, GCP, or Azure).
• Strong communication skills, able to explain technical ideas clearly to both engineers and customer executives.

Benefits

• Base salary range: $182,000 to $242,000.
• Comprehensive benefits package including medical, dental, and vision insurance, company-paid Life Insurance, short and long-term disability insurance, and more.
• Flexible PTO, catered lunch, and a casual work environment.

Why Us?

We work hard, have fun, and move fast. We're in an exciting stage of hyper-growth with opportunities for professional development and innovation.

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You bring extensive ASIC digital design experience with a track record of delivering production RTL for complex semiconductor IP. Your expertise encompasses timing closure, power optimization, and design quality across advanced process nodes.

You will:

• Design RTL modules for LPDDR PHY IP from microarchitecture through synthesis-ready implementation
• Optimize designs to meet timing, power, and area targets across multiple process nodes
• Develop Perl automation for design generation and flow integration
• Collaborate with cross-functional teams to resolve timing and power challenges
• Contribute to design reviews and methodology development

Your designs will enable LPDDR PHY IP deployed in high-volume mobile, automotive, and AI products. You will contribute to a major revenue-generating product line for Synopsys. Your work will define performance characteristics for customer systems-on-chip. Your automation will improve design efficiency across the engineering team. Your expertise will influence architectural decisions for future products.

Requirements:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• 8+ years of ASIC digital design experience with RTL ownership in production silicon
• Expert Verilog proficiency for timing-critical designs
• Strong Perl scripting skills for design automation
• Deep knowledge of synthesis, timing analysis, and power optimization
• Experience with PHY IP or high-speed interfaces is preferred

Benefits include comprehensive health, wellness, and financial benefits, such as medical and healthcare plans, time away, family support, ESPP, retirement plans, and competitive salaries.

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Responsibilities:

• Review and approve sales contracts before execution to ensure compliance with ASC 606, identify potential accounting issues, and provide guidance to the Sales team on deal structures.
• Partner with Deal Desk, Sales, Legal, FP&A, Product Management, Business Systems, and GL Accounting teams to assess complexities or custom terms in contracts and develop solutions.
• Develop and maintain revenue policies and procedures to ensure accurate and consistent accounting treatment.
• Thoroughly review and document executed sales contracts from a technical revenue perspective and provide clear accounting guidance to the Revenue Accounting team to ensure compliance and accurate revenue recognition.
• Prepare position papers when necessary to clearly communicate new policies or address complex topics as they arise.
• Assist in the creation and execution of SOX internal controls over our revenue accounting processes.
• Assist with external and internal audits, providing necessary documentation and technical accounting memos.
• Monitor industry trends and emerging accounting guidance to assess the impact on our revenue recognition policies.
• Support automation and system improvements to enhance the Commercial Accounting team's efficiency and accuracy.
• Propose and see through to completion AI-powered process improvements.
• Provide technical training and guidance to internal teams on revenue recognition matters.

Requirements:

• CPA required (or equivalent international certification).
• 5+ years of relevant experience, with a mix of Big 4 public accounting and industry experience preferred.
• Strong expertise in ASC 606, revenue recognition principles, and US GAAP.
• Experience in cloud infrastructure, SaaS, or software industries.
• Exceptional analytical skills and the ability to interpret complex contracts.
• Strong communication skills and the ability to work cross-functionally in a fast-paced environment.
• Detail-oriented with the ability to manage multiple priorities and meet deadlines.
• Proven ability to handle intricate technical analyses and create clear, actionable reports or position papers.

What We Offer:

• Competitive salary ($127,000 to $168,000 per year).
• Comprehensive benefits program, including medical, dental, and vision insurance, 100% paid for by CoreWeave.
• Company-paid Life Insurance.
• Voluntary supplemental life insurance.
• Short and long-term disability insurance.
• Flexible Spending Account.
• Health Savings Account.
• Tuition Reimbursement.
• Ability to Participate in Employee Stock Purchase Program (ESPP).
• Mental Wellness Benefits through Spring Health.
• Family-Forming support provided by Carrot.
• Paid Parental Leave.
• Flexible, full-service childcare support with Kinside.
• 401(k) with a generous employer match.
• Flexible PTO.
• Catered lunch each day in our office and data center locations.
• A casual work environment.
• A work culture focused on innovative disruption.

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As the Director of Applications Engineering, this role leads a team of Application Engineers who partner with Synopsys’ customers to successfully integrate leading-edge Interface IP (IIP) into ASIC SoCs/systems for next-generation products utilizing our PCIe/SERDES IPs.

You will be accountable for team execution, technical quality, customer success, and cross-functional alignment,hiring and developing talent, setting priorities, driving best practices, and owning escalations to ensure predictable, high-quality outcomes across multiple customer programs.

Responsibilities:

• Lead and develop a team of Application Engineers (hiring, onboarding, coaching, and performance management) to deliver excellent customer outcomes.
• Set priorities, allocate resources, and manage execution across multiple customer engagements and internal deliverables; establish operating rhythms and clear accountability.
• Own customer escalations for Interface IP integration, driving structured debug and resolution plans in partnership with R&D, Product, and Program teams.
• Define and standardize best practices for pre-silicon integration reviews, signoff checklists, and milestone-based customer engagement to improve predictability and quality.
• Lead AI initiatives to define and implement an AI-empowered flow that accelerates pre-silicon IP integration, debug, and customer engagement processes.
• Drive strong cross-functional collaboration and feedback loops to improve product quality, documentation, collateral, and enablement based on field learnings.
• Track and report on key metrics (e.g., milestone health, issue trends, response times, customer satisfaction) and continuously improving team processes.
• Stay current on relevant standards and market trends (e.g., PCIe, SERDES and related ecosystem requirements) and translate them into team readiness and customer guidance.
• Travel occasionally to support strategic customer engagements, executive reviews, and critical milestones.

The Impact You Will Have:

• Enhancing the usability and adoption of Synopsys' Interface IP products by providing expert technical support.
• Facilitating successful integration of IP into customer designs, contributing to their product development timelines.
• Improving customer satisfaction by resolving technical issues efficiently and effectively.
• Driving innovation by working with cutting-edge technologies and industry specifications.
• Strengthening Synopsys' market position through successful customer engagements and support.
• Contributing to the development of next-generation products that leverage high-speed protocols and advanced IP.

Requirements:

• Bachelor’s or Master’s degree in electrical engineering, Computer Engineering, or related field.
• 20+ years of experience in SoC/ASIC development, applications engineering, design, verification, or silicon/IP bring-up; with a track record of customer-facing technical leadership.
• Strong project/program management skills with a focus on execution and problem-solving: build and drive plans, manage risks/dependencies, lead escalations, and communicate clearly with internal and external executives.
• Proven people leadership: set team vision and operating rhythm; hire, coach, and develop an inclusive, high-performing team; drive execution across multiple customer programs.
• Experience with high-speed protocols such as PCIe, Ethernet; Experience with High-Speed SerDes development or support is a plus.
• Technical depth in at least one domain: Front-End (RTL/SystemVerilog, CDC/RDC, lint, verification) and/or Back-End (synthesis, STA, place & route, signoff), or Analog/Mixed-Signal design and integration.
• Strong understanding of SoC tape-out flows and milestones (integration, verification signoff, timing closure, and handoff), and experience supporting customers through critical tape-out schedules.

Who You Are:

• Creative and results-oriented, capable of managing multiple tasks concurrently.
• Strong verbal and written communication skills in English.
• Ability to work collaboratively across teams to deliver solutions to customers.
• Strong analytical, reasoning, and problem-solving skills.
• Willingness to travel occasionally to support customer engagements.

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We are seeking a Senior Engineering Manager to lead the Identity and Integrations Products team within Security Products at CoreWeave. This team is responsible for building and operating foundational capabilities for integrations connecting CoreWeave to various security infrastructures, enterprise identity providers, and directory services.

Responsibilities

• Lead, mentor, and grow a high-performing Identity and Integrations Products engineering team.
• Set the team's technical vision, roadmap, priorities, and execution strategy in partnership with Product Managers and Security Products leadership.
• Own service reliability and operational excellence, including availability, latency, incident response, and capacity planning.
• Establish engineering practices for secure development, architecture reviews, and sustainable delivery.
• Drive effective cross-functional collaboration across security, infrastructure, and customer-facing engineering teams.
• Partner with Product Managers and customers to understand integration requirements and resolve complex integration issues.
• Communicate technical decisions, tradeoffs, risks, and progress clearly to stakeholders.

Requirements

• 5+ years of experience managing complex functions or multiple related teams.
• Experience running engineering operations for high-scale services with 99.95%+ availability.
• Demonstrated ability to make sound technical decisions in ambiguous environments.
• Excellent written and verbal communication skills.
• A track record of delivering through ambiguity and aligning stakeholders.
• Willingness to work on-site in Sunnyvale, California.

Preferred Qualifications

• Experience building security products or platforms for enterprise customers.
• Experience with identity, key management, encryption, or security integrations.
• Experience partnering with external customers or technology partners.
• Experience leading greenfield products from early architecture through production adoption.

Success Metrics

In your first year, you will:

• Build trust with the Identity and Integrations Products team and key partner organizations.
• Establish a clear technical and execution roadmap aligned with Security Products and CoreWeave priorities.
• Improve the reliability, observability, and operational maturity of the team's most critical services.
• Raise the quality and consistency of architecture, security, and operational reviews.
• Hire and develop exceptional engineers while creating a healthy team culture.

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Responsibilities

The Chief of Staff serves as a strategic and operational force multiplier, enabling the leadership team to operate at maximum effectiveness across a fast-moving AI Cloud organization. This role blends strategic planning, operational rigor, and cross-functional coordination to drive alignment, execution, and accountability across product, engineering, and partner teams.

Key Responsibilities:

• Build and manage the executive's agendas for staff meetings, operating reviews, product and engineering forums, and leadership offsites.
• Identify, frame, and prioritize key topics and decisions to ensure meetings are outcome-oriented and aligned with strategic goals.
• Anticipate upcoming decisions and proactively surface risks, tradeoffs, and dependencies.
• Design, maintain, and continuously improve business and operating cadences across product and engineering.
• Coordinate inputs, pre-reads, and outputs across teams to ensure consistent, high-quality execution of these cadences.
• Own executive-level OKR reporting, ensuring clarity, accuracy, and narrative around progress, risks, and mitigation plans.
• Drive accountability by following up on underperforming or at-risk initiatives and facilitating course correction.
• Capture key decisions and action items from executive and leadership meetings.
• Ensure clear ownership, deadlines, and visibility for all critical action items.
• Track execution and proactively intervene to remove blockers or escalate issues when needed.
• Lead or support high-priority, cross-functional initiatives on behalf of the executive office.

Requirements

• Bachelor's degree in a relevant field (e.g., Engineering, Computer Science, Business, or a related discipline); advanced degree (MBA or equivalent) is a plus.
• 6+ years of experience in roles such as Chief of Staff, program management, product operations, engineering operations, management consulting, or equivalent.
• Strong familiarity with product and engineering organizations, ideally within cloud infrastructure, AI/ML platforms, or high-growth technology companies.
• Demonstrated experience building and managing operating cadences, executive agendas, and cross-functional coordination.
• Proven ability to track, report, and drive execution against OKRs or similar performance frameworks.
• Exceptional organizational skills with a track record of capturing decisions, managing action items, and ensuring follow-through.
• Excellent written and verbal communication skills, with the ability to synthesize complex technical and business topics for executive audiences.
• High degree of discretion, judgment, and professionalism when working with senior leaders and sensitive information.
• Comfortable operating in ambiguity and fast-paced environments, with a bias toward action and results.

Benefits

• Medical, dental, and vision insurance (100% paid for by CoreWeave)
• Company-paid Life Insurance
• Voluntary supplemental life insurance
• Short and long-term disability insurance
• Flexible Spending Account
• Health Savings Account
• Tuition Reimbursement
• Ability to Participate in Employee Stock Purchase Program (ESPP)
• Mental Wellness Benefits through Spring Health
• Family-Forming support provided by Carrot
• Paid Parental Leave
• Flexible, full-service childcare support with Kinside
• 401(k) with a generous employer match
• Flexible PTO
• Catered lunch each day in office and data center locations
• Casual work environment

Salary

The base salary range for this role is $149,000 to $198,000. The starting salary will be determined based on job-related knowledge, skills, experience, and market location.

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We are seeking a Senior Software Engineer to design, build, and operate scalable, reliable web services in a distributed-systems environment. You will work on foundational security products and services that protect customer data, enforce access decisions, and provide trustworthy building blocks for the CoreWeave platform.

Responsibilities

• Design and implement scalable, reliable backend services using REST and/or gRPC APIs.
• Define clear API contracts, service boundaries, data models, and integration patterns.
• Own services through their full lifecycle: architecture, implementation, testing, deployment, observability, on-call support, and continuous improvement.
• Improve service reliability through effective error handling, retries, timeouts, idempotency, back-pressure, capacity planning, and graceful degradation.
• Establish and use service observability, including metrics, logs, traces, dashboards, and actionable alerts to understand system health and customer impact.
• Participate in design reviews, code reviews, incident response, and post-incident improvements.
• Collaborate with Product, Security Engineering, Infrastructure, and partner teams to deliver secure and usable platform capabilities.
• Design and support integrations with customers' on-premises and cloud environments and with their security products, such as identity providers, key-management services, HSMs, SIEMs, and policy or access-control systems.
• Work with customers and internal stakeholders to understand integration constraints, define reliable contracts, and guide secure adoption across heterogeneous environments.
• Make pragmatic trade-offs between near-term delivery, long-term maintainability, performance, and operational risk.
• Mentor engineers and contribute to a culture of technical excellence, ownership, and continuous learning.

Requirements

• Strong professional experience building and operating production backend services and improving their reliability, performance, and maintainability.
• Experience designing and implementing RESTful and/or gRPC APIs.
• Deep understanding of distributed-systems principles, including consistency, concurrency, fault tolerance, networking, and service-to-service communication.
• Fluency in Go, Java, C++ or Python; willingness to work primarily in Go.
• Experience with relational or distributed data stores, asynchronous processing, and service integration patterns.
• Strong testing practices, including unit, integration, contract, load, and failure-mode testing as appropriate.
• Ability to communicate technical decisions clearly in design documents, reviews, and cross-functional discussions.
• Sound judgment when working with sensitive data, trust boundaries, authorization decisions, and security-sensitive failure modes.

Preferred Qualifications

• Experience in one or more of the following areas is helpful but not required:
• Designing or building authorization systems at scale, including policy evaluation, permissions, tenant isolation, or least-privilege access.
• Encryption, key management systems, cloud key management services, HSMs, or KMIP.
• OAuth 2.0, OpenID Connect, workload identity, federation, or related identity protocols.
• SCIM, enterprise identity integrations, SSO, or lifecycle management.
• SRE and reliability practices, including incident response, error budgets, capacity planning, and operational readiness.
• Service observability using metrics, structured logging, distributed tracing, and production diagnostics.
• Load testing, performance analysis, capacity modeling, and scaling strategy.
• Kubernetes, cloud infrastructure, infrastructure as code, or platform engineering.
• Building security products for enterprise, regulated, or otherwise security-sensitive customers.
• Integrating SaaS or cloud services with customer-managed on-premises infrastructure, private clouds, public clouds, and enterprise security products.

What Success Looks Like

In your first three months, you will develop a deep understanding of the team's systems and customers, and contribute to production services. You will take ownership of meaningful technical problems and improve the clarity, reliability, and operational readiness of the services you support. Over time, you will deliver secure and dependable capabilities, influence architecture beyond your immediate area, improve API and service reliability, and help the team scale its engineering practices as the Security Products portfolio grows.

Benefits

• Medical, dental, and vision insurance - 100% paid for by CoreWeave
• Company-paid Life Insurance
• Voluntary supplemental life insurance
• Short and long-term disability insurance
• Flexible Spending Account
• Health Savings Account
• Tuition Reimbursement
• Ability to Participate in Employee Stock Purchase Program (ESPP)
• Mental Wellness Benefits through Spring Health
• Family-Forming support provided by Carrot
• Paid Parental Leave
• Flexible, full-service childcare support with Kinside
• 401(k) with a generous employer match
• Flexible PTO
• Catered lunch each day in our office and data center locations
• A casual work environment
• A work culture focused on innovative disruption

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We are seeking a talented and experienced Senior Software Engineer to join our Network Datapath Team. As a Senior Software Engineer, you will play a critical role in designing, developing, and maintaining the networking software/hardware that underpins our GPU cloud services. As a Datapath Monitoring/Observability Engineer, you will focus on developing solutions and systems to provide high fidelity visibility into our services performance and fault detection through real time network telemetry and data analytic pipelines.

Responsibilities:

• Design, develop, and maintain the network datapath monitoring and observability infrastructure for our GPU cloud services, including host networking, smart NICs, and overlay/underlay networks.
• Collaborate with cross-functional teams, including DevOps, Production and Data Platform Engineers, to ensure seamless integration of network datapath solutions.
• Participate in an on-call rotation, troubleshoot and resolve network-related issues, and provide timely support to the operations team.
• Stay up-to-date with the latest network telemetry and monitoring technologies, industry trends, and best practices to continually improve our networking infrastructure.
• Participate in code reviews, design discussions, and architecture decisions to ensure high-quality software development practices.

Requirements:

• Bachelor's or Master's degree in Computer Science, Computer Engineering, or a related field.
• Proven experience (5+ years) as a Software Engineer, with a focus on networking and network observability.
• Expertise in network protocols, routing, and security (TCP/IP, BGP, kernel networking, etc.) with a preference on cloud solutions.
• Proficiency in programming languages such as Golang or Python for automation and scripting.
• Experience with software-defined networking (SDN) and network virtualization technologies.
• Experience in troubleshooting k8s networking and cloud infrastructure.
• Excellent problem-solving skills and a proactive attitude towards troubleshooting and issue resolution.
• Strong communication skills and the ability to collaborate effectively with cross-functional teams.
• A passion for staying updated on emerging technologies and a commitment to continuous learning.

Preferred Qualifications:

• Experience with k8s operators and controllers.

What We Offer:

• The base salary range for this role is $153,000 to $204,000.
• A comprehensive benefits program, including medical, dental, and vision insurance, company-paid Life Insurance, short and long-term disability insurance, flexible spending account, health savings account, tuition reimbursement, and employee stock purchase program.
• Flexible PTO, catered lunch each day in our office and data center locations, a casual work environment, and a work culture focused on innovative disruption.

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What You'll Do

CoreWeave's Engaged Accounts team manages and grows a book of active, billing customers across infrastructure and software. The team is built to deepen existing customer relationships, protect revenue, and expand consumption through a portfolio model supported by technical and cross-functional specialists.

About the Role

The Account Manager owns a portfolio of 15-30 active customer accounts spanning CoreWeave infrastructure and Weights & Biases software. This role is responsible for the day-to-day health, retention, renewal, and expansion of those accounts.

This is a customer-facing role for someone who can manage a book of business while driving commercial execution across infrastructure and software motions. The right candidate will build durable, multi-threaded relationships, manage renewals and expansions, and coordinate internal resources to keep customers successful and growing.

In this role, you will:

• Own and grow a portfolio of 15-30 billing customers across CoreWeave infrastructure and Weights & Biases software.
• Drive expansion and retention across your book, protecting and growing recurring revenue.
• Identify, shape, negotiate, and close expansion opportunities within existing accounts.
• Build and maintain multi-threaded relationships across technical and business stakeholders within each customer.
• Monitor account health, usage, and consumption trends, and drive adoption to reduce churn risk.
• Orchestrate CoreWeave resources , Solutions Architects, Technical Solutions Managers, support, and product specialists , to resolve issues and unlock growth across your portfolio.
• Lead commercial conversations and negotiations for renewals and expansions across infrastructure and software.
• Forecast and report on portfolio revenue, renewals, and expansion pipeline against your targets.
• Partner cross-functionally with Technical, Business Development, Professional Services, and Partners to deliver customer outcomes.

Who You Are

• 6+ years of sales, account management, or customer-facing commercial experience in cloud, infrastructure, SaaS, AI platform, or related technology markets.
• Experience managing a book or portfolio of multiple active customer accounts simultaneously.
• Demonstrated track record of driving retention, renewals, and expansion revenue.
• Experience negotiating and closing commercial deals, including renewals and upsell/expansion.
• Comfortable working across both infrastructure and SaaS/software motions.
• Experience consistently meeting or exceeding revenue and retention goals.
• Bachelor's degree or equivalent practical experience.

Preferred

• Experience with cloud platforms, hyperscalers, AI infrastructure, or adjacent software platforms.
• Experience managing both infrastructure and SaaS customers within the same book of business.
• Familiarity with consumption- or usage-based revenue models.
• Familiarity with large-scale compute, bare metal, inference, or AI platform offerings.

Wondering if You're a Good Fit?

You may be a strong fit if:

• You naturally look around corners to find new ways to engage and support customers.
• You are energized by using technology to solve meaningful business problems with customer impact.
• You can balance commercial rigor with strong relationship management across a high-volume book.
• You are comfortable operating with ownership, ambiguity, and a high bar for customer outcomes.

The base salary range for this role is $165,000 to $205,000. The starting salary will be determined based on job-related knowledge, skills, experience, and market location. We strive for both market alignment and internal equity when determining compensation. In addition to base salary, our total rewards package includes a discretionary bonus, equity awards, and a comprehensive benefits program (all based on eligibility).

What We Offer

In addition to a competitive salary, we offer a variety of benefits to support your needs. These include:

• Medical, dental, and vision insurance - 100% paid for by CoreWeave
• Company-paid Life Insurance
• Voluntary supplemental life insurance
• Short and long-term disability insurance
• Flexible Spending Account
• Health Savings Account
• Tuition Reimbursement
• Ability to Participate in Employee Stock Purchase Program (ESPP)
• Mental Wellness Benefits through Spring Health
• Family-Forming support provided by Carrot
• Paid Parental Leave
• Flexible, full-service childcare support with Kinside
• 401(k) with a generous employer match
• Flexible PTO
• Catered lunch each day in our office and data center locations
• A casual work environment
• A work culture focused on innovative disruption

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As a Silicon IP Customer Success Manager, you will serve as the primary point of contact for customers throughout IP program delivery, from kickoff through post-silicon support. Your responsibilities include:

• Owning statement of work (SOW), program schedules, milestones, and deliverables across analog IP, digital IP, and SoC integration efforts
• Coordinating cross-functional global teams including design, verification, applications, and sales
• Identifying technical, resource, and schedule risks early and driving mitigation plans
• Reporting program health and blockers to internal leadership and customers in a way that drives action

The impact you will have includes:

• Accelerating customer product launches by keeping IP delivery on schedule and reducing integration friction
• Reducing delivery risk across high-stakes programs where timing, quality, and customer trust are non-negotiable
• Strengthening Synopsys' reputation as a reliable IP partner by consistently delivering what was promised
• Driving broader adoption of Synopsys IP by ensuring customers have a smooth experience
• Shaping program management standards across the IP organisation

To succeed in this role, you will need:

• A BSEE or equivalent, with 10+ years of semiconductor industry experience
• Proven technical program management experience in SoC design, analog IP, or digital IP development
• Direct experience managing customer-facing programs where you owned schedules, deliverables, and stakeholder communication
• Strong understanding of semiconductor design flows, IP integration challenges, and what it takes to get a chip to tape out
• Ability to lead and influence cross-functional teams without direct authority, across geographies and disciplines

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As a Senior Software Engineer - AI Infrastructure Performance Insights & Observability, you will play a critical role in developing and maintaining the performance insights and observability capabilities of CoreWeave's AI infrastructure.

The base salary range for this role is $182,000 to $242,000. The starting salary will be determined based on job-related knowledge, skills, experience, and market location.

Responsibilities:

• Design, develop, test, and maintain software components for performance insights and observability
• Collaborate with cross-functional teams to identify and prioritize project requirements
• Analyse and optimize system performance, identifying bottlenecks and areas for improvement
• Develop and implement monitoring and logging solutions to ensure system reliability and uptime

Requirements:

• Strong programming skills in languages such as Python, Java, or C++
• Experience with containerization (e.g., Docker), orchestration (e.g., Kubernetes), and cloud computing platforms (e.g., AWS, GCP, Azure)
• Knowledge of monitoring and logging tools such as Prometheus, Grafana, and ELK Stack
• Excellent problem-solving skills and attention to detail

Benefits:

• Medical, dental, and vision insurance, 100% paid for by CoreWeave
• Company-paid Life Insurance
• Voluntary supplemental life insurance
• Short and long-term disability insurance
• Flexible Spending Account
• Health Savings Account
• Tuition Reimbursement
• Ability to Participate in Employee Stock Purchase Program (ESPP)
• Mental Wellness Benefits through Spring Health
• Family-Forming support provided by Carrot
• Paid Parental Leave
• Flexible, full-service childcare support with Kinside
• 401(k) with a generous employer match
• Flexible PTO
• Catered lunch each day in our office and data center locations
• A casual work environment

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This role will own the end-to-end SOX compliance framework, with particular emphasis on scalable controls. This leader will partner closely with Finance, Accounting, Engineering, Operations, and external auditors to build a best-in-class compliance program that enables growth while maintaining a strong and efficient control environment.

Responsibilities:

• SOX Program Leadership & Optimization:
• Lead the end-to-end SOX compliance program, driving continuous improvement and maturation
• Assess and enhance our scoping methodology to ensure appropriate coverage of in-scope systems, processes, and controls
• Refine process narratives, risk-control matrices, and control documentation for clarity and completeness
• Execute risk assessments to validate and prioritize key financial, operational, and IT controls
• Ensure compliance with Section 404(b) of SOX and PCAOB audit standards
• Identify and implement efficiency opportunities while maintaining control effectiveness

• Education & Organizational Development:
• Develop and deliver SOX training programs for employees at all levels, from executives to process owners
• Create educational materials, playbooks, and resources to build SOX literacy across the organization
• Serve as the go-to SOX subject matter expert, providing guidance and answering complex technical questions
• Build a culture of controls awareness and compliance accountability

• Testing & Remediation:
• Design and execute comprehensive control testing programs (design and operating effectiveness)
• Identify control deficiencies, assess severity, and drive timely remediation with process owners
• Document testing results, deficiencies, and management responses with precision and clarity
• Track remediation efforts and validate effectiveness of corrective actions
• Ensure lessons learned inform ongoing improvements

• Governance & Reporting:
• Report regularly to the Head of SOX, CAO, and SteerCo on SOX program status, risks, and deficiencies
• Prepare management's assessment of ICFR effectiveness for SEC filings
• Develop executive-level dashboards and metrics to provide transparency into compliance status
• Build confidence with leadership and the Audit Committee through clear, proactive communication

• External Audit Management:
• Serve as primary liaison with external auditors for SOX-related matters
• Coordinate audit planning, walkthroughs, testing, and issue resolution
• Provide timely, complete documentation and responses to auditor requests
• Manage audit timelines and deliverables to ensure efficient, successful audits
• Build strong, collaborative relationships with audit partners

• Continuous Improvement & Automation:
• Identify opportunities to streamline controls, reduce manual effort, and improve efficiency
• Leverage technology solutions (GRC platforms, automation tools, monitoring capabilities) to enhance the control environment
• Assess impact of system changes, implementations, and business transformations on controls
• Drive process improvements that strengthen controls while enabling business agility

• Team Leadership:
• Lead, mentor, and develop a team of 3 SOX professionals, providing clear direction and support
• Foster a culture of excellence, continuous learning, and proactive problem-solving
• Provide career development opportunities and technical training for team members
• Build team capability and confidence

Requirements:

• Bachelor's degree in Accounting, Finance, Information Systems, or related field
• CPA, CISA, or CIA certification required (CPA strongly preferred)
• 15+ years of progressive, hands-on SOX compliance experience, with significant time spent in technical SOX roles
• Deep expertise in ITGCs and ITACs, including the ability to evaluate technical control design and testing methodologies at a granular level
• Proven track record of strengthening and maturing SOX programs within complex technology environments
• Comprehensive knowledge of SOX regulations, COSO framework, PCAOB standards, and US GAAP
• Strong executive presence with ability to educate and influence stakeholders at all levels
• Exceptional analytical, problem-solving, and communication skills

Preferred Qualifications:

• Big Four public accounting firm experience with focus on SOX advisory
• Experience with public companies, particularly in technology or SaaS environments
• Experience with modern ERP systems (NetSuite and SAP) and financial close/consolidation tools
• Familiarity with GRC platforms (AuditBoard, etc.)
• Experience in high-growth technology companies
• Experience coaching and developing SOX teams

What We Offer:

• Base salary range: $182,000 to $242,000
• Discretionary bonus
• Equity awards
• Comprehensive benefits program, including medical, dental, and vision insurance, 100% paid for by CoreWeave
• Company-paid Life Insurance
• Voluntary supplemental life insurance
• Short and long-term disability insurance
• Flexible Spending Account
• Health Savings Account
• Tuition Reimbursement
• Ability to Participate in Employee Stock Purchase Program (ESPP)
• Mental Wellness Benefits through Spring Health
• Family-Forming support provided by Carrot
• Paid Parental Leave
• Flexible, full-service childcare support with Kinside
• 401(k) with a generous employer match
• Flexible PTO
• Catered lunch each day in our office and data center locations
• A casual work environment
• A work culture focused on innovative disruption

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You'll own and drive core people processes, balancing executional rigor with speed. You'll identify patterns early, surface insights quickly, and help leaders course-correct before people challenges impact delivery.

The focus of this role is reducing friction, increasing clarity, and amplifying leadership impact as the organization scales.

Responsibilities:

• Strategic Partnership: Serve as an influential thought partner to P&E leaders, helping translate business goals into people decisions that improve execution, support growth, and strengthen organizational effectiveness.
• Execute with Impact: Consistently deliver high-quality outcomes across complex, often ambiguous workstreams.
• Pattern Recognition & Insights: Leverage data, observations, and deep domain expertise to identify recurring patterns across P&E.
• Enable Change at Speed: Lead organizational change in a dynamic, fast-paced environment.
• Talent Management: Drive workforce planning, talent calibration, and performance management activities across P&E.
• People Risk & Workplace Advisory: Independently manage complex people matters.
• Cross-functional Delivery: Lead effective collaboration with People Team COEs and other stakeholders.

Requirements:

• Be Curious at Your Core: Genuine curiosity about the business and the evolving world of AI.
• Act Like an Owner: Take full accountability for outcomes.
• Empower Employees: Believe in enabling others to succeed.
• Deliver Best-in-Class Client Experiences: Measure success by the effectiveness of leaders and teams.
• Achieve More Together: Thrive in collaboration.

Benefits:

• Medical, dental, and vision insurance (100% paid for by CoreWeave)
• Company-paid Life Insurance
• Voluntary supplemental life insurance
• Short and long-term disability insurance
• Flexible Spending Account
• Health Savings Account
• Tuition Reimbursement
• Ability to Participate in Employee Stock Purchase Program (ESPP)
• Mental Wellness Benefits through Spring Health
• Family-Forming support provided by Carrot
• Paid Parental Leave
• Flexible, full-service childcare support with Kinside
• 401(k) with a generous employer match
• Flexible PTO
• Catered lunch each day in office and data center locations

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You will define and execute product and go-to-market strategy for Synopsys' industry-leading AI portfolio.

Key responsibilities include:

• Defining and executing product and go-to-market strategy for Synopsys' industry-leading AI portfolio.
• Assimilating customer requirements, technology trends, and competitive intelligence to shape product roadmaps.
• Driving integrated marketing strategies encompassing thought leadership, demand generation, and customer-focused campaigns.
• Developing and executing innovative go-to-market plans, including packaging, pricing, and new business models.
• Engaging directly with customers to understand requirements, anticipate market shifts, and identify future design trends.
• Building business cases for future development, negotiating product line priorities, and guiding technology roadmaps.
• Exploring inorganic growth opportunities such as M&A and partnerships and supporting technology due diligence.
• Collaborating with cross-functional stakeholders to foster ecosystem partnerships and drive product life cycle management.
• Owning messaging and positioning for digital implementation optimization and signoff timing analysis domains.
• Training, motivating, and guiding the sales force to advance the AI portfolio's market presence.
• Developing and tracking the sales pipeline to meet financial targets and strategic objectives.
• Performing financial analysis and revenue forecasting to align business strategy and inform executive decisions.
• Serving as a recognized expert and role model in the field, representing Synopsys internally and externally.

The Impact You Will Have:

• Shape the future of AI-driven design automation and semiconductor innovation on a global scale.
• Drive the evolution and success of Synopsys' AI portfolio, influencing industry standards and best practices.
• Accelerate customer outcomes by delivering cutting-edge products that address real-world challenges.
• Enhance Synopsys' market share and financial performance through strategic product leadership.
• Foster a culture of collaboration, innovation, and continuous improvement across multi-disciplinary teams.
• Establish Synopsys as a thought leader in AI for EDA and semiconductor industries.
• Enable rapid adoption of new AI technologies through compelling go-to-market strategies.
• Expand the company's reach via strategic partnerships, acquisitions, and ecosystem development.
• Mentor and develop future leaders in product management and AI technology.
• Elevate customer satisfaction through tailored solutions and proactive engagement.

What You'll Need:

• 15+ years of relevant experience in product management, ideally within EDA or semiconductor industries.
• Bachelor's degree in electrical engineering (BS EE) or equivalent technical discipline.
• Expertise in Generative AI technologies, including frameworks, foundation models, training, and inferencing methodologies.
• Proven experience in one or more domains: Digital Design/Implementation, Verification, Signoff, Analog Design.
• Demonstrated ability to negotiate, influence, and lead in a matrixed organization.
• Successful track record in launching, managing, and growing technology products.
• Exceptional verbal and written communication and public speaking skills.
• Experience with financial analysis, revenue forecasting, and strategic planning.
• Understanding of go-to-market planning, packaging, pricing, and product lifecycle management.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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This is a hands-on, customer-facing engineering role,ideal for someone who thrives in high-impact environments, enjoys solving open-ended technical problems, and wants to shape how the world’s leading organizations build with AI.

Responsibilities:

• Embed inside customer AI engineering teams to design, prototype, and productionize AI agents using W&B Weave.
• Act as a trusted technical advisor, helping customers make architectural decisions and best practices for agentic workflows.
• Develop reference implementations, demos, and example projects that showcase effective use of W&B Weave.
• Gather and relay feedback from the field to influence the W&B Weave product roadmap and improve the AI developer experience.
• Conduct technical workshops, deep dives, and enablement sessions to accelerate customer adoption.
• Troubleshoot and resolve technical challenges in customer environments.

Qualifications:

• Strong engineering background with experience in Python and modern ML/AI systems frameworks (e.g., PyTorch, TensorFlow, Hugging Face, LangChain, LlamaIndex, etc.).
• A minimum of a bachelor's degree (or international equivalent), in Computer Science or related field, is required.
• Hands-on experience with LLMs, AI agents, or orchestration frameworks.
• Ability to work directly with customers in technical consulting or solution engineering roles.
• Excellent communication skills: able to explain complex technical concepts clearly to both technical and business stakeholders.
• Comfortable working in fast-paced, ambiguous environments where creativity and problem-solving are key.
• Experience in one or more of the following is a plus: building production ML/AI systems, working with vector databases, retrieval-augmented generation, or reinforcement learning, prior forward deployed / field engineering / solutions architect roles.

The base salary range for this role is $182,000 to $242,000. The starting salary will be determined based on job-related knowledge, skills, experience, and market location.

Benefits:

• Medical, dental, and vision insurance - 100% paid for by CoreWeave
• Company-paid Life Insurance
• Voluntary supplemental life insurance
• Short and long-term disability insurance
• Flexible Spending Account
• Health Savings Account
• Tuition Reimbursement
• Ability to Participate in Employee Stock Purchase Program (ESPP)
• Mental Wellness Benefits through Spring Health
• Family-Forming support provided by Carrot
• Paid Parental Leave
• Flexible, full-service childcare support with Kinside
• 401(k) with a generous employer match
• Flexible PTO
• Catered lunch each day in our office and data center locations
• A casual work environment
• A work culture focused on innovative disruption

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You will serve as the primary point of contact for customers throughout IP program delivery, from kickoff through post-silicon support. You will own statement of work (SOW), program schedules, milestones, and deliverables across analog IP, digital IP, and SoC integration efforts.

Key responsibilities include:

• Coordinating cross-functional global teams including design, verification, applications, and sales
• Identifying technical, resource, and schedule risks early and driving mitigation plans
• Reporting program health and blockers to internal leadership and customers in a way that drives action

The impact you will have:

• Accelerate customer product launches by keeping IP delivery on schedule and reducing integration friction
• Reduce delivery risk across high-stakes programs where timing, quality, and customer trust are non-negotiable
• Strengthen Synopsys' reputation as a reliable IP partner by consistently delivering what was promised

Requirements:

• BSEE or equivalent, with 10+ years of semiconductor industry experience
• Proven technical program management experience in SoC design, analog IP, or digital IP development
• Direct experience managing customer-facing programs where you owned schedules, deliverables, and stakeholder communication
• Strong understanding of semiconductor design flows, IP integration challenges, and what it takes to get a chip to tape out

We offer a base salary range of $189,000-$283,000.

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The Technical Deployment Lead will support the expansion of CoreWeave's Data Centers across the U.S and Canada, ensuring overall availability and reliability to meet or exceed defined service levels.

Responsibilities:

• Nationwide travel to data centers to build and deploy new and ongoing sites
• Implementation and documentation of a global data center standard
• Troubleshoot hardware and networks
• Root cause analysis of hardware and software failures
• Train internal teams
• Perform on-site audits through the set QA/QC process
• Provide technical support to global data center teams
• Develop tools and scripts to update server and networking hardware
• Perform maintenance of test and tools equipment
• Follow-up project support

Requirements:

• Hands-on experience troubleshooting and assembling computer hardware
• Proficiency with the Linux operating system
• Comprehensive knowledge of data center cut sheets and technical documentation
• Strong understanding of best practices for cable management and hardware orientation
• Effective communication and collaboration skills
• Excellent time management and project ownership skills
• Flexibility to travel and work in a 24/7 operational environment
• Ability to lift up to 50 lbs and work in elevated locations

Benefits:

• Medical, dental, and vision insurance, 100% paid for by CoreWeave
• Company-paid Life Insurance
• Voluntary supplemental life insurance
• Short and long-term disability insurance
• Flexible Spending Account
• Health Savings Account
• Tuition Reimbursement
• Ability to Participate in Employee Stock Purchase Program (ESPP)
• Mental Wellness Benefits through Spring Health
• Family-Forming support provided by Carrot
• Paid Parental Leave
• Flexible, full-service childcare support with Kinside
• 401(k) with a generous employer match
• Flexible PTO
• Catered lunch each day in office and data center locations
• Casual work environment

Salary: $90,000 to $102,000 per year

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Responsibilities:

• Partner Relationship Management:
• Serve as primary field liaison for strategic partners, including NVIDIA, AWS, Google Cloud, Microsoft Azure, and select technology ecosystem partners.
• Build and maintain executive-level relationships at partner organizations.
• Develop and manage joint business plans, including co-sell targets and enablement milestones.
• Represent CoreWeave at partner QBRs, field events, and executive briefings.

• Go-to-Market Execution:
• Drive co-sell and influence pipeline with CoreWeave's field sales team and partner managers.
• Identify, track, and accelerate joint opportunities.
• Develop territory-level partner plans aligned to regional sales priorities and quotas.
• Work with partner field teams to embed CoreWeave in their customer conversations and solution architectures.

• Partner Enablement:
• Lead enablement sessions, workshops, and technical briefings for partner sales and technical teams.
• Develop joint solution plays and reference architectures with Solutions Engineering and Product Marketing.
• Maintain a deep understanding of CoreWeave's product portfolio and competitive differentiation.

• Ecosystem Development:
• Collaborate with the Business Development team to evaluate new partnership opportunities.
• Contribute to CoreWeave's partner program development, including tier frameworks, incentives, and co-marketing structures.

• Measurement & Reporting:
• Track and report on partner-influenced and partner-sourced pipeline, revenue, and engagement metrics.
• Provide field-level feedback to central Business Development and product teams.
• Maintain accurate records of partner activity and pipeline in Salesforce.

Requirements:

• 6+ years of experience in partner management, alliances, business development, or a related field-facing role at a cloud, infrastructure, or enterprise software company.
• Demonstrated experience managing strategic partnerships with hyperscalers or major technology ecosystem partners.
• Proven track record of driving partner-influenced revenue and executing co-sell motions in a field environment.
• Strong executive presence and ability to build trusted relationships at senior levels.
• Exceptional written and verbal communication skills.
• Experience working cross-functionally with sales, marketing, product, and engineering teams.
• Highly organized and self-directed.

Nice to Have:

• Prior experience at or with NVIDIA, AWS, Google Cloud, or MSFT Azure in a partner or alliances capacity.
• Background in GPU computing, AI/ML infrastructure, Model Ecosystem, MLOps.
• Familiarity with cloud co-sell programs.

Location:

• This is a field-based role. Candidates must be located in or willing to relocate to one of the following: San Francisco, Sunnyvale, or New York.
• Travel of approximately 30–40% is expected.

Compensation:

• The base salary range for this role is $149,000 to $198,000.

Benefits:

• Medical, dental, and vision insurance - 100% paid for by CoreWeave.
• Company-paid Life Insurance.
• Voluntary supplemental life insurance.
• Short and long-term disability insurance.
• Flexible Spending Account.
• Health Savings Account.
• Tuition Reimbursement.
• Ability to Participate in Employee Stock Purchase Program (ESPP).
• Mental Wellness Benefits through Spring Health.
• Family-Forming support provided by Carrot.
• Paid Parental Leave.
• Flexible, full-service childcare support with Kinside.
• 401(k) with a generous employer match.
• Flexible PTO.
• Catered lunch each day in our office and data center locations.
• A casual work environment.
• A work culture focused on innovative disruption.

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The Observability Engineering organization at CoreWeave is responsible for the platforms and practices that help engineers understand, operate, and improve production systems at scale. This team owns and evolves the foundations for metrics, logs, traces, telemetry pipelines, and observability reliability, enabling teams to detect issues quickly, troubleshoot complex distributed systems, and operate AI infrastructure with confidence.

As CoreWeave continues to scale, observability plays a critical role in delivering reliable platform experiences, improving engineering velocity, and maintaining operational excellence across a rapidly growing cloud environment.

Responsibilities:

• Define strategy and roadmap for observability engineering
• Drive platform reliability and performance improvements
• Guide architectural decisions across observability infrastructure
• Partner with infrastructure, platform, security, and application engineering teams to improve instrumentation and production visibility
• Lead a team of senior engineers and technical leads

Requirements:

• 5+ years of software engineering experience with production systems at scale
• 2+ years of engineering management experience leading senior engineers and technical leads
• Experience building and operating observability platforms across logs, metrics, traces, or alerting in distributed systems
• Knowledge of reliability engineering concepts including SLOs, SLIs, incident management, error budgets, and fault-tolerant design
• Experience scaling telemetry systems including storage backends, and query layers
• Experience with distributed systems, performance engineering, and trade-offs involving scale, resilience, and cost

Preferred Qualifications:

• Experience with OpenTelemetry, Grafana, Prometheus-compatible systems, log aggregation, and distributed tracing tools
• Experience operating cloud-native infrastructure, including Kubernetes environments
• Experience supporting large-scale cloud, developer platforms, or AI/ML infrastructure
• Familiarity with capacity planning for high-ingest telemetry systems
• Experience scaling platforms in high-growth environments

What We Offer:

• Base salary range: $182,000 to $242,000
• Discretionary bonus
• Equity awards
• Comprehensive benefits program
• Medical, dental, and vision insurance
• 100% paid for by CoreWeave
• Company-paid Life Insurance
• Voluntary supplemental life insurance
• Short and long-term disability insurance
• Flexible Spending Account
• Health Savings Account
• Tuition Reimbursement
• Ability to Participate in Employee Stock Purchase Program (ESPP)
• Mental Wellness Benefits through Spring Health
• Family-Forming support provided by Carrot
• Paid Parental Leave
• Flexible, full-service childcare support with Kinside
• 401(k) with a generous employer match
• Flexible PTO
• Catered lunch each day in our office and data center locations
• A casual work environment

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Responsibilities

• Author, profile, and optimize CUDA kernels for large-scale model serving
• Optimize kernels for hardware, exploiting tensor cores and tuning occupancy, memory coalescing, and shared-memory/register usage
• Use kernel-authoring DSLs and compilers to prototype and ship kernels quickly without sacrificing performance
• Benchmark rigorously, building reproducible microbenchmarks and roofline analyses to validate kernel-level wins
• Implement and maintain benchmarking workflows for end-to-end MLPerf Inference and Training runs
• Lead design reviews and drive architecture within the team
• Mentor junior engineers and review cross-team designs

Requirements

• 5+ years of experience in high-performance computing, GPU/accelerator software, or performance-critical systems
• Hands-on CUDA experience, with a deep understanding of GPU architecture and performance
• Strong coding skills in C++ and Python
• Familiarity with model-serving stacks and kernels that dominate their inference cost
• Strong communication and collaboration skills

Preferred Skills

• Triton or Mojo for authoring custom GPU kernels
• CuTe DSL for Python-based kernel authoring on NVIDIA GPUs
• JAX and its Pallas kernel language for authoring kernels on GPU/TPU
• HIP / ROCm and AMD GPU experience
• Experience with Kubernetes at production scale
• Experience running MLPerf submissions or similar large-scale audited benchmarks

Benefits

• Competitive salary ($182,000 to $242,000)
• Comprehensive benefits program, including medical, dental, and vision insurance
• Flexible PTO and catered lunch in office and data center locations
• Opportunities for professional growth and development

Culture

• Collaborative and innovative work environment
• Emphasis on curiosity, ownership, empowerment, and client satisfaction
• Flexible work arrangements and supportive team

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About the role

This is an opportunity to help shape one of the most critical layers of the AI cloud: ensuring workloads run seamlessly, reliably, and efficiently across massive GPU clusters. By building the systems that eliminate infrastructure bottlenecks and create new orchestration capabilities, you will directly empower customers to innovate faster and push the boundaries of what’s possible with AI.

What You’ll Do

As a Staff Engineer (IC5), you will be a technical leader shaping the long-term strategy for CoreWeave’s orchestration platform. You’ll define architectural direction, own critical parts of the orchestration platform and other managed services, and drive cross-org initiatives in scheduling, quota enforcement, and scaling at hyperscale. You’ll mentor senior engineers, establish org-wide best practices in reliability and observability, and ensure CoreWeave’s orchestration layer evolves to meet the demands of next-generation AI workloads.

Who You Are

• 8–12 years of professional software engineering experience.
• Proven track record designing and operating large-scale distributed systems in production.
• Deep expertise in Slurm/Kubernetes internals and cloud-native development.
• Advanced proficiency in Go and distributed systems design.
• Experience setting technical direction and influencing cross-team architecture.
• Ability to mentor senior engineers and elevate organizational standards.

Preferred

• Familiarity with orchestration and workflow technologies such as Ray, Kubeflow, Kueue, Istio, Knative, or Argo Workflows
• Experience with distributed workloads, GPU-based applications, or ML pipelines.
• Knowledge of scheduling concepts like quota enforcement, pre-emption, and scaling strategies.
• Exposure to reliability practices including SLOs, alarms, and post-incident reviews.
• Experience with AI infrastructure and workloads (ML training, inference, or HPC).

Wondering if you’re a good fit?

• You love defining long-term architecture for systems at global scale.
• You’re curious about orchestration beyond SUNK and how to evolve it for next-generation AI.
• You’re an expert at mentorship, architecture, and operational excellence across teams.
• You thrive on solving problems that balance cost, performance, and reliability in high-demand environments.

The base salary range for this role is $207,000 to $275,000. The starting salary will be determined based on job-related knowledge, skills, experience, and market location.

What We Offer

In addition to a competitive salary, we offer a variety of benefits to support your needs. These include:

• Medical, dental, and vision insurance - 100% paid for by CoreWeave
• Company-paid Life Insurance
• Voluntary supplemental life insurance
• Short and long-term disability insurance
• Flexible Spending Account
• Health Savings Account
• Tuition Reimbursement
• Ability to Participate in Employee Stock Purchase Program (ESPP)
• Mental Wellness Benefits through Spring Health
• Family-Forming support provided by Carrot
• Paid Parental Leave
• Flexible, full-service childcare support with Kinside
• 401(k) with a generous employer match
• Flexible PTO
• Catered lunch each day in our office and data center locations
• A casual work environment
• A work culture focused on innovative disruption

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CoreWeave is The Essential Cloud for AI. Built for pioneers by pioneers, CoreWeave delivers a platform of technology, tools, and teams that enables innovators to build and scale AI with confidence.

What You'll Do

As a Senior Software Engineer II, Applied Training, you will be an early member of a small team responsible for developing a Kubernetes-native research cluster platform or a sandbox client for agentic training and evaluation. Your goal will be to provide every CoreWeave customer with research infrastructure that currently only exists inside frontier labs.

Responsibilities

• Contribute to the roadmap for Applied Training and identify what unlocks new workloads
• Work closely with customers and other teams to build cloud-native primitives
• Design and build a complete research cluster experience, including CLI, job configuration schema, and Kubernetes operators
• Own the Python SDK for sandbox infrastructure and enable RL training runs at scale
• Write documentation for running popular OSS training frameworks on CoreWeave
• Collaborate with infrastructure teams and customers to understand their needs

Requirements

• 8–12+ years of experience building distributed systems, ML infrastructure, or developer platforms
• Real Kubernetes experience with custom controllers, operators, scheduling, and workload orchestration
• Understanding of what makes researchers productive, including code distribution and fast iteration cycles
• Familiarity with training, including distributed job scheduling and rank initialization
• Experience shipping infrastructure that others rely on daily
• Strong communication skills to work with customers and translate researcher complaints into system designs

Preferred

• Experience building internal ML platforms or research clusters
• Familiarity with agentic AI, RL training, and sandbox isolation
• Background with Slurm, Ray, or similar workload orchestration
• Experience with container runtimes, isolation, or serverless platforms
• OSS contributions to Kubernetes SIGs, Ray, PyTorch, or similar

Benefits

• Competitive salary ($182,000 - $242,000)
• Comprehensive benefits program, including medical, dental, and vision insurance
• Flexible spending account and health savings account
• Tuition reimbursement and employee stock purchase program
• Mental wellness benefits and family-forming support
• Paid parental leave and flexible PTO
• Catered lunch and casual work environment

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You will be involved with next-generation SerDes and Memory interface controllers, PHYs, and subsystems.

You are an experienced ASIC Digital Signoff Engineer with a deep passion for developing cutting-edge technology and direct hands-on experience with STA and EM/IR flows.

With over 12+ years of hands-on experience, you have honed your skills in high-speed digital IP cores and/or SOCs development.

You have a solid understanding of digital design flows and deep expertise in Static Timing Analysis (STA), Power Analysis, and EM/IR for advanced node designs.

Your technical expertise is complemented by your ability to foster cross-functional collaboration, driving innovation and effective communication across global teams.

Your analytical mind and problem-solving skills enable you to tackle complex challenges and deliver high-quality results.

You are known for your clear and concise documentation, and your familiarity with Synopsys tools and high-speed interface protocols is a significant advantage.

Responsibilities

• Develop and deploy advanced node signoff methodologies for cutting-edge IP designs targeting different foundries.
• Work with leading-edge designs and teams to drive the industry-best PPA for IP designs.
• Evaluate and exercise various aspects of the development flow which include signoff timing, power, physical verification, EM/IR analysis, and ECO’s.
• Develop and maintain best-in-class digital design methodologies, including documentation, scripts, and training materials.
• Work as a liaison between Synopsys tool and IP design teams.
• Continuously improve and refine design processes to enhance efficiency and performance.

Requirements

• BS or MS in EE with 12+ years of hands-on experience developing CAD flows for high-speed digital IP cores and/or SOCs.
• Direct hands-on experience with enabling advanced node STA/ Timing signoff flows at SoC level.
• Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions.
• Familiarity with EMIR & Thermal sign-off flows is a plus.
• Ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results.
• Good analysis, debugging, and problem-solving skills.
• Solid written and verbal communication skills and the ability to create clear and concise documentation and provide training.
• Familiarity with other Synopsys tools such as StarRC and ICV is a plus.
• Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR are a plus.

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In this role, you will be a trusted partner to the CFO, taking ownership of complex workstreams and delivering critical initiatives across CoreWeave. You will help maximize the effectiveness of the finance leadership team and drive alignment and execution of key financial and strategic objectives within the team and across the broader CoreWeave organization.

Responsibilities include:

• Serving as a strategic partner to the CFO, developing and structuring problem statements, analyzing and optimizing processes, providing actionable recommendations, and managing execution.
• Driving end-to-end project management for a portfolio of the CFO's highest-priority projects, including technology transformation and compliance requirements.
• Preparing clear and concise communications for various audiences, including the executive team, the Board of Directors, investors, and all-company forums.
• Managing the rhythm of the business and operational cadence of the finance organization, including leadership meetings, goal-setting, and performance tracking.
• Supporting implementation of technology platforms to empower the Finance organization, from AI capabilities to core tools.
• Acting as a proxy for the CFO, building trust and influence across all levels of the organization to foster collaboration and accountability.

Requirements:

• 7-10 years of experience in investment banking, private equity, corporate finance, consulting, or in-house operational experience in Strategy, Finance, Corporate Development, Business Operations, or a strategic Chief of Staff role.
• A bachelor's degree is required; an MBA or other relevant advanced degree is preferred.
• Broad background and literacy across financial roles, including experience with financial models, proficiency with accounting principles, and FP&A business processes.
• Demonstrated ability to seamlessly shift between rolling up your sleeves to solve tactical problems and partnering with C-level executives on high-level strategic planning.
• Proven ability to build trust and influence across all levels of an organization, fostering collaboration and accountability without direct ownership.
• Exceptional verbal and written communication skills.
• Advanced proficiency with the Microsoft Office Suite, particularly Excel and PowerPoint.
• A strong understanding of cloud services, software businesses, digital infrastructure, or data centers is preferred.

The base salary range for this role is $165,000 to $242,000. The starting salary will be determined based on job-related knowledge, skills, experience, and market location. In addition to base salary, our total rewards package includes a discretionary bonus, equity awards, and a comprehensive benefits program.

Benefits include:

• Medical, dental, and vision insurance, 100% paid for by CoreWeave
• Company-paid Life Insurance
• Voluntary supplemental life insurance
• Short and long-term disability insurance
• Flexible Spending Account
• Health Savings Account
• Tuition Reimbursement
• Ability to Participate in Employee Stock Purchase Program (ESPP)
• Mental Wellness Benefits through Spring Health
• Family-Forming support provided by Carrot
• Paid Parental Leave
• Flexible, full-service childcare support with Kinside
• 401(k) with a generous employer match
• Flexible PTO
• Catered lunch each day in our office and data center locations
• A casual work environment

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Join CoreWeave, The Essential Cloud for AI, as a Software Engineer on the Inference team. You'll work on shipping production features to improve latency, reliability, and cost for model serving on our GPU platform.

Responsibilities

• Implement features and fixes in Python/Go/C++ for model-serving services like Triton, vLLM, TensorRT-LLM, and Ray Serve.
• Write tests, code comments, and design documents, and participate in code reviews.
• Develop basic metrics and dashboards, and assist with alarms and runbooks.
• Follow on-call runbooks and learn incident response in a guided rotation.
• Contribute to performance experiments, such as request batching, concurrency, and caching.

Requirements

• BS/MS in Computer Science, Electrical Engineering, or a related field, or equivalent practical experience.
• Strong foundations in data structures, algorithms, and networked services.
• Experience with Python or Go, and Linux fundamentals; Git/CI basics.
• Exposure to containers and Kubernetes.
• Curiosity about GPU inference concepts.

Preferred Qualifications

• Internship or project experience deploying a microservice or ML inference demo.
• Coursework or research with PyTorch or TensorFlow; simple CUDA projects a plus.
• Familiarity with Grafana/Prometheus/OpenTelemetry or similar tooling.

What We Offer

• Competitive salary: $92,000 to $135,000 per year.
• Comprehensive benefits package, including medical, dental, and vision insurance, company-paid life insurance, and flexible spending accounts.
• Opportunities for professional growth and development in a rapidly growing company.

Our Culture

• We prioritize a hybrid work environment, with remote work options available.
• We're committed to fostering an inclusive and supportive workplace.

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We're looking for a Senior Manager, People Business Partner to own the strategic partnership with Operations senior leadership while also working closely with a team of PBPs to ensure consistent, high-quality people support across the Ops organization.

Your Impact Will Be Felt Across Various Dimensions

• Strategic Partnership: Serve as the senior HR partner to Operations leadership, embedded in strategic planning, workforce decisions, and org design as we scale globally.
• Expansion: Lead the PBP workstream on expansion in partnership with internal People teams.
• Workforce Planning: Translate growth into headcount planning in close partnership with Talent Acquisition and other internal People teams.
• Senior Leadership Development: Partner with Operations leaders on executive development, coaching, and succession planning for the senior leadership population.
• Talent Calibration: Drive talent mapping and calibration for Ops leadership, holding the bar on job architecture and leveling.
• Org Design: Advise Operations leaders on org structure, spans and layers, and headcount decisions as our team structures evolve across new geographies and facilities.
• People Risk & Workplace Advisory: Consult on complex people matters, balancing risk, speed, and business practicality.

What We Look for

• Be Curious at Your Core: You ask thoughtful questions, seek to understand root causes, and apply learnings to improve outcomes.
• Act Like an Owner: You take responsibility for your cases and follow through with care and attention to detail.
• Empower Employees: You champion an equitable employee experience by coaching leaders and ensuring employees feel heard, supported, and treated fairly.
• Deliver Best-in-Class Client Experiences: You approach managers, employees, and cross-functional partners with professionalism, empathy, and consistency, ensuring they feel supported in even the most challenging moments.
• Achieve More Together: You collaborate seamlessly with People Business Partners, and other People teams, recognizing that the best solutions come from working as one team with shared goals.

Compensation The base salary range for this role is $149,000 to $198,000. The starting salary will be determined based on job-related knowledge, skills, experience, and market location.

Benefits

• Medical, dental, and vision insurance - 100% paid for by CoreWeave
• Company-paid Life Insurance
• Voluntary supplemental life insurance
• Short and long-term disability insurance
• Flexible Spending Account
• Health Savings Account
• Tuition Reimbursement
• Ability to Participate in Employee Stock Purchase Program (ESPP)
• Mental Wellness Benefits through Spring Health
• Family-Forming support provided by Carrot
• Paid Parental Leave
• Flexible, full-service childcare support with Kinside
• 401(k) with a generous employer match
• Flexible PTO
• Catered lunch each day in our office and data center locations
• A casual work environment
• A work culture focused on innovative disruption

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What You'll Do

The Business Systems team at CoreWeave partners across Infrastructure, Data Center Operations, Supply Chain, and Finance to build and scale the systems that power our global data center footprint. We are seeking a Staff Business Systems Engineer to own and evolve the systems supporting Data Center infrastructure operations.

Responsibilities:

• Own the end-to-end business systems and solution architecture supporting the Data Center asset lifecycle across ERP, DCIM, CMDB, EAM, and related platforms
• Define and evolve asset lifecycle processes from capacity planning through deployment and retirement
• Design and optimize workflows supporting asset readiness, staging, configuration tracking, deployment status, and in-service visibility
• Define and manage data models ensuring accurate asset identity, hierarchy, and system-of-record alignment
• Build and maintain integrations and APIs across Supply Chain, Data Center, and Finance systems to enable automation and real-time visibility
• Partner with Infrastructure, DC Ops, Finance, and Supply Chain to translate business requirements into scalable system solutions
• Drive system standardization and consolidation to support high-volume deployment environments
• Define and manage the Data Center systems roadmap with a focus on scalability, reliability, and data integrity
• Ensure systems support auditability, compliance, and traceability in partnership with Security and Compliance teams
• Act as the technical owner for cross-system issues impacting asset data integrity and lifecycle flows

Who You Are

• 8–12+ years of experience in Business Systems, Enterprise Applications, Systems Engineering, or Solutions Architecture
• Hands-on experience with ERP systems (e.g., NetSuite, SAP, Oracle)
• Experience with enterprise operational platforms such as DCIM (e.g., Sunbird), CMDB (e.g., ServiceNow), or similar systems
• Proven experience designing and implementing systems that support full asset lifecycle management (procure → build → deploy → maintain → retire)
• Experience building and maintaining integrations across ERP, inventory, logistics, and infrastructure platforms
• Strong understanding of asset hierarchy modeling, infrastructure topology, and system-of-record design
• Experience supporting high-scale infrastructure environments, including hardware manufacturing, assembly, or data center operations
• Ability to define scalable system architectures and data models in complex, distributed environments
• Experience supporting global or multi-site data center environments
• Demonstrated ability to ensure auditability, compliance, and traceability of infrastructure assets

Benefits

• Medical, dental, and vision insurance - 100% paid for by CoreWeave
• Company-paid Life Insurance
• Voluntary supplemental life insurance
• Short and long-term disability insurance
• Flexible Spending Account
• Health Savings Account
• Tuition Reimbursement
• Ability to Participate in Employee Stock Purchase Program (ESPP)
• Mental Wellness Benefits through Spring Health
• Family-Forming support provided by Carrot
• Paid Parental Leave
• Flexible, full-service childcare support with Kinside
• 401(k) with a generous employer match
• Flexible PTO
• Catered lunch each day in our office and data center locations
• A casual work environment
• A work culture focused on innovative disruption

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Responsibilities:

• Own multiple services within the orchestration platform
• Lead design/code reviews, decompose projects into milestones, and drive measurable improvements in reliability and performance
• Define SLIs/SLOs for services, strengthen operational practices, and mentor junior engineers
• Ensure customers see consistent improvements in throughput, latency, and system resilience

Requirements:

• 3-5 years of professional software engineering experience building distributed systems or cloud services
• Strong coding in Go (Python or C++ a plus) with solid CS fundamentals
• Hands-on experience running Kubernetes at production scale
• Familiarity with observability stacks (Prometheus, Grafana, OpenTelemetry)
• Proven ability to improve service reliability and performance using metrics

Preferred Qualifications:

• Familiarity with orchestration and workflow technologies such as Ray, Kubeflow, Kueue, Istio, Knative, or Argo Workflows
• Experience with distributed workloads, GPU-based applications, or ML pipelines
• Knowledge of scheduling concepts like quota enforcement, pre-emption, and scaling strategies
• Exposure to reliability practices including SLOs, alarms, and post-incident reviews

Benefits:

• Competitive salary ($139,000 to $204,000)
• Discretionary bonus, equity awards, and comprehensive benefits program
• Medical, dental, and vision insurance (100% paid)
• Flexible Spending Account, Health Savings Account, Tuition Reimbursement, and more

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You will be a key member of CoreWeave's Revenue Accounting function, driving significant process improvements, ensuring accurate financial reporting, and developing future team members.

Responsibilities

• Lead the month-end close process for Revenue and Commissions
• Prepare and review financial close journal entries, reconciliations, and analyses
• Present revenue and commissions information to executives
• Collaborate with Technical Revenue, Accounts Receivable, and other teams
• Identify opportunities for process improvements and implement solutions
• Develop other members of the Revenue Accounting team
• Assist in the revenue forecast process with FP&A
• Design, implement, and perform SOX controls
• Evaluate new product introductions or upstream process changes for impacts to Revenue Accounting

Requirements

• 6+ years of progressive experience in public accounting or global high-tech organizations
• Strong knowledge of ASC 606
• Experience with Netsuite ARM
• Experience improving revenue accounting processes and system enhancements
• Strong analytical and problem-resolution skills
• Excellent organizational and communication skills

Benefits

• Competitive salary ($127,000 to $168,000)
• Discretionary bonus and equity awards
• Comprehensive benefits program, including medical, dental, and vision insurance
• Flexible PTO and catered lunch in office locations
• 401(k) with employer match
• Mental wellness benefits and family-forming support

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The Inference team builds and operates CoreWeave's Kubernetes-native inference platform, powering low-latency, high-throughput AI workloads at massive scale. You will work deeply in distributed systems and Kubernetes-based infrastructure, focusing on areas like scheduling, batching, and memory optimization.

Responsibilities:

• Lead cross-team design initiatives and optimize inference performance
• Improve system reliability at scale and work deeply in distributed systems and Kubernetes-based infrastructure
• Focus on areas like scheduling, batching, and memory optimization

Requirements:

• 8–12+ years of experience building and operating large-scale distributed systems or cloud platforms
• Proven experience leading cross-team technical initiatives impacting multiple services or organizations
• Strong programming skills in Go, Python, or C++
• Deep expertise in Kubernetes at production scale, including orchestration, scheduling, and service design
• Strong understanding of distributed systems, networking, and performance optimization

Preferred Qualifications:

• Experience with inference frameworks such as vLLM, Triton, TensorRT-LLM, Ray Serve, or TorchServe
• Experience with GPU systems and performance optimization (CUDA, NCCL, RDMA, NUMA, GPU interconnects)
• Experience leading multi-team or org-level technical initiatives
• Exposure to large-scale AI/ML infrastructure or hyperscale cloud environments

Benefits:

• Medical, dental, and vision insurance - 100% paid for by CoreWeave
• Company-paid Life Insurance
• Voluntary supplemental life insurance
• Short and long-term disability insurance
• Flexible Spending Account
• Health Savings Account
• Tuition Reimbursement
• Ability to Participate in Employee Stock Purchase Program (ESPP)
• Mental Wellness Benefits through Spring Health
• Family-Forming support provided by Carrot
• Paid Parental Leave
• Flexible, full-service childcare support with Kinside
• 401(k) with a generous employer match
• Flexible PTO
• Catered lunch each day in our office and data center locations
• A casual work environment
• A work culture focused on innovative disruption

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Your primary responsibility will be to define the company's overall medium/long-term ambitions and strategy through the annual corporate strategic planning process. This includes analysing the industry landscape and trends, competitive dynamics, assessing the company's business portfolio, and identifying business performance improvement opportunities.

You will also collaborate with the Corporate Development team in defining proactive, strategy-driven M&A plans and strategic partnerships. You will drive due diligence on strategic acquisitions and support cross-functional integration planning.

Additionally, you will lead C-suite level projects to address specific strategic questions/issues/opportunities across businesses and functions. You will own the end-to-end work process, from framing the question/issue to developing hypotheses, conducting analyses, and articulating actionable recommendations.

You will partner with the Business Units for the development of their respective business strategies, identifying priority initiatives and investments across product/engineering, go-to-market, and operations.

You will work cross-functionally to drive the operationalization of critical cross-unit strategic initiatives from set-up to impact. You will establish strategic KPIs and a program management structure.

You will support the CEO, CSO, and other senior executives on strategy-related communications.

The successful candidate will have experience in management consulting, private equity, or investment banking. They will have strong Excel modeling skills, with due diligence experience being highly valued. They will also have strong project management capabilities across multiple concurrent workstreams.

Knowledge of the semiconductor or software industry is valued, but not a prerequisite. An MBA degree is also valued, but not a prerequisite.

The ideal candidate will have a growth mindset, be eager to be stretched and learn, and be committed to excellence and attention to detail. They will be motivated to be part of a small, highly dynamic team working on C-Suite level topics in a fast-paced environment.

They will have excellent analytical/problem-solving and communication skills to generate insights and articulate an independent point of view backed by data/facts. They will be comfortable working with senior leaders and able to develop trust-based relationships and drive alignment of different stakeholder groups.

They will have intellectual curiosity and creativity combined with hands-on action/results orientation. They will be passionate for technology and the transformative potential of AI.

The successful candidate will approach strategic questions methodically and develop well-supported recommendations. They will establish credibility with senior leaders through rigorous work and candid perspectives. They will communicate complex findings clearly to an executive audience. They will thrive in a high-performing team where contributions directly impact outcomes.

The team you will be part of is the Corporate Strategy team, which drives medium/long-term company strategic plan, high-impact strategic initiatives, due diligence on strategic acquisitions, and investment assessment of new businesses. The Corporate Strategy team is a part of the Chief Strategy Officer's organization (Strategy and Corporate Development), which also includes Corporate Development/M&A, Market & Competitive Intelligence, Partnerships, Technology Innovation, and Government Affairs.

Rewards and benefits include a comprehensive range of health, wellness, and financial benefits to cater to your needs. Total rewards include both monetary and non-monetary offerings.

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You will be an owner who leads designs, raises engineering standards, and delivers measurable improvements to latency, throughput, and reliability across multiple services. You'll partner with product, orchestration, and hardware teams to evolve our Kubernetes-native platform and meet strict P99 SLAs at scale.

Key responsibilities include:

• Developing and enhancing Kubernetes-native benchmarking services that measure latency, throughput, jitter, and cost-per-request across CoreWeave's compute stack.
• Contributing to implementing and maintaining benchmarking workflows for end-to-end MLPerf Training and Inference runs, including workload setup, cluster configuration, and result validation.
• Participating in design discussions and contributing to architecture decisions within the team.
• Breaking down engineering tasks into clear milestones and delivering reliable, high-quality code.
• Collaborating with teammates to maintain reproducible, well-documented benchmarking processes.
• Providing constructive code reviews and sharing best practices with peers.
• Mentoring junior engineers; reviewing cross-team designs and elevating coding/testing standards.

Requirements include:

• 3–5 years of experience building distributed systems, high-performance computing components, or cloud services.
• Strong programming skills in Python or Go (C++ a plus) with understanding of networked systems and performance fundamentals.
• Hands-on experience with Kubernetes in production environments plus familiarity with CI/CD and observability tools (e.g., Prometheus, Grafana, OpenTelemetry).
• Exposure to performance-critical GPU systems (CUDA, NCCL, NVLink/PCIe, memory bandwidth) or model-serving stacks (llm-d, vLLM, TensorRT-LLM, Megatron-LM).
• Effective communicator comfortable working cross-functionally.

Nice to have:

• Experience with time-series databases, LSM-based storage engines, or custom data pipelines.
• Familiarity with MLPerf or other large-scale benchmarking frameworks.
• Contributions to OSS projects such as llm-d, vLLM or PyTorch.
• Exposure to benchmarking GPU clusters or multi-region environments.
• Background working with CUDA kernels, NCCL/SHARP, RDMA/NUMA, or GPU interconnect topologies.

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As a Memory Compiler Architect, you will be responsible for designing, developing, and evaluating physical IP,Memory compilers (SRAM/RF/ROM/TCAM etc.). You will apply expertise in circuit design, memory architecture optimization for best-in-class PPA and industry-standard verification tools to optimize workflows and enhance design efficiency.

Collaborate with cross-functional teams to align project deliverables with business objectives. Contribute to the technical direction and problem-solving efforts within the engineering group. Share knowledge and support the professional growth of team members through technical mentorship.

Advance our product portfolio with innovative solutions addressing market demands. Improve the efficiency and effectiveness of engineering development workflows. Solve complex engineering challenges, contributing to successful project outcomes. Support the growth and technical development of colleagues through guidance and collaboration.

Key responsibilities include:

• Designing, developing, and evaluating physical IP,Memory compilers (SRAM/RF/ROM/TCAM etc.)
• Applying expertise in circuit design, memory architecture optimization for best-in-class PPA and industry-standard verification tools to optimize workflows and enhance design efficiency
• Collaborating with cross-functional teams to align project deliverables with business objectives
• Contributing to the technical direction and problem-solving efforts within the engineering group
• Sharing knowledge and supporting the professional growth of team members through technical mentorship

Requirements include:

• Bachelor's or master's degree in Electrical Engineering, Computer Science, or a related field
• 15+ years of experience in embedded memory design (SRAM/RF/ROM/TCAM), including functional verification with industry-standard tools
• Significant experience in memory compiler flow
• Proficiency in Python and Hspice/XA
• Familiarity with industry-standard verification tools for design and signoff flows
• Strong problem-solving and technical skills
• Ability to work collaboratively and communicate effectively within and across teams

The ideal candidate will be an effective communicator who engages and influences stakeholders. A strategic thinker with a passion for innovation. A collaborative professional who thrives in a dynamic, fast-paced environment. A mentor willing to share expertise and support the technical growth of peers. A problem-solver with keen attention to detail.

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You will define and evolve the architecture for how AI workloads are admitted, scheduled, and governed across large GPU clusters using frameworks such as Kueue, Volcano, and Ray. This platform serves as a strategic complement to SUNK (Slurm on Kubernetes) and underpins both training and inference workloads across the CoreWeave cloud.

This role requires strong systems thinking, cross-team influence, and a long-term view of platform scalability, reliability, and developer experience.

You will own the technical vision and architecture for major portions of the AI Workload Orchestration Platform, design scalable, reliable orchestration primitives for AI workloads across multiple schedulers and runtimes, lead cross-team architecture reviews and drive alignment across infrastructure, CKS, and managed inference teams, define platform standards for reliability, observability, capacity management, and operational excellence, identify and resolve systemic performance, scalability, and fairness issues across large GPU clusters, mentor senior engineers and grow technical leadership within the organization, and represent the platform in technical reviews and influence broader CoreWeave platform strategy.

You will be responsible for leading technical initiatives across teams without direct authority, owning mission-critical systems at scale, and having a strong operational mindset. You will also have the opportunity to mentor senior engineers and grow technical leadership within the organization.

If you're a strong systems thinker with a passion for AI and cloud computing, this could be the perfect opportunity for you to join a team of innovators and help shape the future of AI workload orchestration.

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We are on the search for a remarkable Senior Manager of Technical Solutions Management (TSM) who shares our passion and has an understanding of GPU infrastructure and AI Applications to join the team.

This critical leadership role will oversee the TSM function, which is responsible for managing technical relationships with strategic customers, defining and delivering on technical requirements, and driving the execution of complex programs from concept to successful completion.

In this role, you will:

• Lead the TSM function within CoreWeave by building, leading, and focusing on hiring top talent and fostering their growth to ensure they excel as the primary technical advocates for CoreWeave's most strategic customers

• Collaborate across functions, working closely with leaders in Solutions Architecture, Support, Sales, and Product Engineering to elevate and enhance the CoreWeave customer experience

• Directly engage and collaborate with key customers to understand their AI workloads, pain points, and future requirements to continuously improve our service offerings

• Define and monitor key performance indicators (KPIs) to evaluate program success and effectiveness through leveraging multiple insights

You will identify and eliminate inefficiencies, accelerate operational speed, and deliver exceptional results that reinforce CoreWeave's position as a market leader.

The base salary range for this role is $207,000 to $275,000.

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You will also be an integral part of achieving industry-leading end-to-end performance benchmarking publications: If MLPerf (Training & Inference), Working closely with NVIDIA (Megatron-LM, TensorRT-LLM & DGX cloud) and the open-source community (llm-d, vLLM and all popular ML frameworks) speak to you, come help us demonstrate CoreWeave's performance reliability leadership in the field.

Responsibilities

• Strategy & Leadership - Define the multi-year benchmarking strategy and roadmap; prioritize models/workloads (LLMs, diffusion, vision, speech) and hardware tiers. Build, lead, and mentor a high-performing team of performance engineers and data analysts. Establish governance for claims: documented methodologies, versioning, reproducibility, and audit trails.

• Perf Ownership - Lead end-to-end MLPerf Inference and Training submissions: workload selection, cluster planning, runbooks, audits, and result publication. Coordinate optimization tracks with NVIDIA (CUDA, cuDNN, TensorRT/TensorRT-LLM, Triton, NCCL) to hit competitive results; drive upstream fixes where needed.

• Internal Latency & Throughput Benchmarks - Design a Kubernetes-native, repeatable benchmarking service that exercises CoreWeave stacks across SUNK (Slurm on Kubernetes), Kueue, and Kubeflow pipelines. Measure and report p50/p95/p99 latency, jitter, tokens/s, time-to-first-token, cold-start/warm-start, and cost-per-token/request across models, precisions (BF16/FP8/FP4), batch sizes, and GPU types. Maintain a corpus of representative scenarios (streaming, batch, multi-tenant) and data sets; automate comparisons across software releases and hardware generations.

• Tooling & Automation - Build CI/CD pipelines and K8s controllers/operators to schedule benchmarks at scale; integrate with observability stacks (Prometheus, Grafana, OpenTelemetry) and results warehouses. Implement supply-chain integrity for benchmark artifacts (SBOMs, Cosign signatures).

• Cross-functional & Community - Partner with NVIDIA, key ISVs, and OSS projects (vLLM, Triton, KServe, PyTorch/DeepSpeed, ONNX Runtime) to co-develop optimizations and upstream improvements. Support Sales/SEs with authoritative numbers for RFPs and competitive evaluations; brief analysts and press with rigorous, defensible data.

Requirements

• 10+ years building distributed systems or HPC/cloud services, with deep expertise on large-scale ML training or similar high-performance workloads.

• Proven track record of architecting or building planet-scale data systems (e.g., telemetry platforms, observability stacks, cloud data warehouses, large-scale OLAP engines).

• Deep understanding of GPU performance (CUDA, NCCL, RDMA, NVLink/PCIe, memory bandwidth), model-server stacks (Triton, vLLM, TensorRT-LLM, TorchServe), and distributed training frameworks (PyTorch FSDP/DeepSpeed/Megatron-LM).

• Proficient with Kubernetes and ML control planes; familiarity with SUNK, Kueue, and Kubeflow in production environments.

• Excellent communicator able to interface with executives, customers, auditors, and OSS communities.

Nice to have

• Experience with time-series databases, log-structured merge trees (LSM), or custom storage engine development.

• Experience running MLPerf submissions (Inference and/or Training) or equivalent audited benchmarks at scale.

• Contributions to MLPerf, Triton, vLLM, PyTorch, KServe, or similar OSS projects.

• Experience benchmarking multi-region fleets and large clusters (thousands of GPUs).

• Publications/talks on ML performance, latency engineering, or large-scale benchmarking methodology.

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Key responsibilities include:

• Leading design reviews and driving architecture within the team
• Defining and owning SLIs/SLOs and ensuring post-incident actions land and reliability improves release-over-release
• Implementing advanced optimizations such as micro-batch schedulers, speculative decoding, and KV-cache reuse
• Strengthening incident posture through capacity planning, autoscaling policy, and rollback/traffic-shift strategies
• Mentoring IC1/IC2 engineers and reviewing cross-team designs to elevate coding/testing standards

We're looking for someone with strong coding skills in Python or Go, deep familiarity with networked systems and performance, and hands-on experience with Kubernetes at production scale. If you have experience with inference internals, batching, caching, mixed precision, and streaming token delivery, that's a plus.

In addition to a competitive salary, we offer a range of benefits including medical, dental, and vision insurance, company-paid life insurance, and flexible PTO. We're committed to creating a work environment that's inclusive, diverse, and supportive of our employees' well-being.

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