You have spent 8+ years building and operating compute infrastructure that powers engineering teams doing work that cannot afford downtime or performance degradation. You understand that reliability at scale is a function of architecture, automation, and the decisions you make about job scheduling, storage, and cloud integration long before anyone notices a problem.

At Synopsys, you will manage the compute environments that enable the design of the chips powering AI, automotive, and next-generation systems. The infrastructure you build directly impacts product timelines and engineering productivity across the company.

Responsibilities

• Enable engineering teams across Synopsys IPG to use on-premises and cloud compute environments for design, verification, and simulation workloads
• Translate requirements from business, engineering, cybersecurity, and data governance stakeholders into a technical roadmap and execute on it
• Manage and optimize job scheduler environments including LSF, UGE, or Slurm across large-scale HPC systems
• Support and troubleshoot Linux/UNIX systems in production, ensuring uptime and performance for engineering workflows
• Build and maintain DevOps automation using Python and other scripting languages to improve reliability and reduce manual toil
• Coordinate with IT, R&D, and infrastructure teams to align compute strategy, resolve issues, and deliver on engineering needs
• Manage cloud compute operations across GCP, AWS, or Azure, including cost optimization, security compliance, and hybrid cloud integration

The Impact You Will Have

• Engineering teams will have reliable, performant compute environments that let them focus on their work instead of fighting infrastructure
• The roadmap you build will shape how Synopsys scales compute capacity for next-generation IP and EDA development
• Your automation and scripting will reduce manual operations overhead and improve system reliability across the HPC environment
• R&D teams will be able to burst to cloud when needed without waiting weeks for approvals or configurations
• Your coordination across IT, security, and engineering will prevent bottlenecks and misaligned priorities before they slow down product timelines
• The job scheduler optimizations you implement will improve throughput and reduce queue wait times for critical engineering runs
• Your deep technical knowledge will make you the go-to resource when something breaks and needs to be fixed fast

Requirements

• Deep hands-on experience with Linux/UNIX system administration in production environments
• Proven experience managing and optimizing job schedulers such as LSF, UGE, or Slurm in large-scale HPC or engineering compute environments
• Strong scripting and automation skills, particularly in Python
• Experience supporting engineering teams using cloud platforms like GCP, AWS, or Azure
• Background in DevOps practices, tooling, and workflows
• Ability to translate technical, business, and security requirements into actionable roadmaps and coordinate across multiple stakeholder groups
• Experience managing HPC systems in large compute data centers is a strong plus

Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• Time away: company holidays, ETO and FTO Programs
• Family support: maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Retirement plans: save for your future with our retirement plans that vary by region and country
• Competitive salaries

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You are an analog design engineer with a passion for creating cutting-edge technology. With a strong foundation in electrical engineering, you possess extensive experience in analog design simulation and analysis. You are adept at using various EDA tools for schematic entry, physical layout, and design verification, including SPICE notation and tools like Synopsys Custom Compiler or Cadence Virtuoso.

The Analog Integration Team (AIT) exists to coordinate and accelerate methodology adoption across analog and adjacent engineering domains. In this role, you will:

• Provide clear ownership for analog and adjacent-domain methodology areas.
• Act as the focal point for customer-driven methodology requirements and integration challenges.
• Be accountable for prioritization, adoption, stakeholder engagement, and execution.
• Improve coordination across product teams and adjacent engineering organizations, including engagement with customers and foundries.
• Support methodology for application-optimized IP and the special-purpose silicon customers are building for specific workloads and system architectures.

The Impact You Will Have:

• Establish sustainable ownership for analog and adjacent-domain methodologies.
• Improve responsiveness to customer methodology requirements.
• Reduce ambiguity on methodology ownership and escalation paths.
• Improve alignment between methodology strategy and execution.
• Accelerate methodology adoption for strategic initiatives and customers, including application-optimized IP for special-purpose silicon.
• Provide measurable accountability for methodology development, deployment, and customer engagement.

What You’ll Need:

• Bachelor’s degree in electrical engineering and a minimum of 5 years of related experience or a Master’s degree in electrical engineering and a minimum of 3 years of related experience.
• Analog design skills and experience with designing for optimal PPA (power, performance, and area).
• Proficiency in simulation using various analog design tools.
• Experience with EDA tools for schematic entry, physical layout, and design verification.
• Knowledge of analog layout parasitics, especially for low nm technologies (FinFET, GAA).

Benefits:

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

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Responsibilities

• Provide system-level technical leadership for assigned platforms and high-speed communication solutions
• Connect system architecture, technical execution, and signoff readiness to drive stronger technical outcomes
• Guide discussions on technical tradeoffs, platform behavior, assumptions, constraints, and risks
• Contribute system- and signoff-informed insight to architecture reviews and key platform decisions
• Strengthen technical ownership, execution predictability, and cross-functional alignment across the product-development flow

Requirements

• M.Sc. or Ph.D. degree in Electrical Engineering or a related field
• Strong experience in SerDes, PHY development, or closely related high-speed communication domains
• Strong system-level technical understanding and the ability to connect detailed engineering work to broader platform behavior
• Experience solving complex technical problems across multiple stakeholders and competing constraints
• Strong ability to assess tradeoffs, identify risks, and guide technical decisions with clarity
• Excellent analytical, problem-solving, and technical communication skills
• Programming or analysis experience in MATLAB, Python, or similar tools is an advantage
• Experience in PHY analog design or strong technical exposure to analog-design-driven PHY development is highly valued

Benefits

• Comprehensive medical and healthcare plans
• Time away programs, including ETO and FTO
• Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance
• ESPP: purchase Synopsys common stock at a 15% discount
• Retirement plans that vary by region and country
• Competitive salaries

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Responsibilities:

• Provide system-level technical leadership for assigned platforms and high-speed communication solutions
• Connect system architecture, technical execution, and signoff readiness to drive stronger technical outcomes
• Guide discussions on technical tradeoffs, platform behavior, assumptions, constraints, and risks
• Contribute system- and signoff-informed insight to architecture reviews and key platform decisions
• Strengthen technical ownership, execution predictability, and cross-functional alignment across the product-development flow

Requirements:

• M.Sc. or Ph.D. degree in Electrical Engineering or a related field
• Strong experience in SerDes, PHY development, or closely related high-speed communication domains
• Strong system-level technical understanding and the ability to connect detailed engineering work to broader platform behavior
• Experience solving complex technical problems across multiple stakeholders and competing constraints
• Strong ability to assess tradeoffs, identify risks, and guide technical decisions with clarity
• Excellent analytical, problem-solving, and technical communication skills
• Programming or analysis experience in MATLAB, Python, or similar tools is an advantage
• Experience in PHY analog design or strong technical exposure to analog-design-driven PHY development is highly valued

Benefits:

• Comprehensive medical and healthcare plans
• Time away programs, including ETO and FTO
• Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance
• ESPP, allowing purchase of Synopsys common stock at a 15% discount
• Retirement plans that vary by region and country
• Competitive salaries

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You are an experienced analog design engineer passionate about developing high-performance integrated circuits that power today’s most advanced technologies. Your deep expertise in CMOS analog design, coupled with your ability to lead and mentor junior colleagues, enables you to tackle complex technical challenges and deliver innovative solutions. You thrive in multicultural, cross-functional environments, collaborating with global teams to bring cutting-edge SerDes products to life. Your analytical mindset, strong organizational skills, and commitment to continuous learning make you a valuable contributor, dedicated to ensuring the reliability and excellence of every design.

What You’ll Be Doing:

• Driving the design and development of medium to large complexity analog circuits for high-speed SerDes products supporting Ethernet and PCIe standards.
• Guiding analog designers to ensure designs meet electrical specifications and reliability constraints.
• Defining methods and procedures for project execution, including planning analog design activities and associated milestones.
• Conducting and preparing design reviews, following up on improvements, and ensuring high quality outcomes.
• Evaluating and minimizing parasitic effects related to layout implementations, collaborating with layout teams to optimize performance, power, and area.
• Ensuring silicon correlation with simulation results, validating design accuracy and robustness.
• Mentoring and training less experienced analog designers, fostering skill development within the team.
• Engaging with a global, multi-cultural, and cross-functional R&D team, contributing to a collaborative and innovative work environment.

The Impact You Will Have:

• Drive the development of industry-leading SerDes products used in diverse markets such as mobile, automotive, AI, HPC, IoT, 5G, and storage.
• Enhance product reliability and performance through rigorous design reviews and optimization practices.
• Drive innovation by implementing advanced FinFET/GAA process nodes in analog integrated circuits.
• Strengthen cross-functional collaboration, enabling seamless integration of analog and mixed signal designs.
• Contribute to Synopsys’ reputation as the provider of high-quality, silicon-proven IP solutions.
• Mentor and develop junior engineers strengthening the team’s capability and talent pipeline for future challenges.

What You’ll Need:

• M.Sc. in Electrical Engineering with 8+ years of experience, or Ph.D. in Electrical Engineering with 6+ years of experience.
• Proven track record in CMOS analog design, preferably including hands-on experience with ADC, DAC, PLL, Rx, Tx, References, etc.
• Experience coordinating design activities across teams and managing medium complexity designs.
• Familiarity with industry-standard IC design packages and EDA tools.
• Experience working in UNIX operating systems.
• System-level knowledge of SerDes architecture is a plus.
• Strong written and verbal communication skills in English.

Rewards and Benefits:

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

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At Synopsys, you will create and review PI models for the SerDes IP developed, support the analog design team in assessing PI performance of IP designs, and handle customer cases related to PI.

Your responsibilities will impact the development of industry-leading SerDes IP used in diverse markets such as mobile, automotive, AI, HPC, IoT, 5G, and storage.

Requirements:

• M.Sc. in Electrical Engineering.
• 8+ years of experience in mixed-signal PCB design for high-density systems.
• Experience in power integrity and EMC/EMI analysis from schematic through layout, simulation, and bench validation.
• Experience leading board bring-up, including PI and signal quality validation.
• Experience with circuit design simulator software (HSPICE, PSPICE or equivalent simulation tools).
• Experience working in UNIX environments.
• Strong written and verbal communication skills in English.

Preferred qualifications include experience working with MATLAB and Ansys Totem.

The team you will join is Synopsys' fast-growing analog and mixed-signal R&D team, dedicated to developing the highest data rate SerDes IP in advanced process nodes.

Rewards and benefits include comprehensive medical and healthcare plans, time away programs, family support, ESPP, retirement plans, and competitive salaries.

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You will review documented specifications, pilot results, known limitations, and lessons learned; converting them into production requirements, implementation plans, acceptance criteria, and operating models.

You will design and validate scalable architectures that support hundreds of concurrent or distributed users while maintaining appropriate performance, availability, and cost efficiency.

You will partner with Synopsys IT, security, legal, data-governance, and tool owners to ensure application compliance.

You will establish deployment, testing, monitoring, logging, incident-management, backup, recovery, change-control, and support processes for live environments.

You will integrate tools with approved enterprise platforms, identity and access-management services, data sources, and existing Analog Design workflows.

You will communicate delivery status, risks, dependencies, compliance findings, and operational metrics to Operations leadership and Analog Design stakeholders.

The Impact You Will Have:

• Empowering analog design teams to maximize productivity, resource utilization, and project delivery success
• Driving continuous improvement and streamlined operations, ensuring industry-leading efficiency and quality
• Contributing to the acceleration of organizational change and the successful adoption of new tools and best practices

What You’ll Need:

• Bachelor’s degree or higher in Information Technology, Computer Science, Software Engineering,
• At least 10 years of experience in a technology-related industry, including substantial responsibility for deploying, scaling, securing, and operating automation, AI, or enterprise software solutions in production environments
• Strong knowledge of scalable application and service architectures, cloud or on-premises deployment models, systems integration, APIs, databases, and identity and access management
• Hands-on experience with performance and load testing, monitoring and observability, reliability engineering, incident response, change management, and production support
• Practical understanding of enterprise data security, privacy, secure software development, AI governance and guardrails, and controls required to protect confidential or NDA-restricted information
• Strong analytical, troubleshooting, project-delivery, stakeholder-management, and written and verbal communication skills

Benefits:

• Comprehensive medical and healthcare plans
• Time away programs
• Family support
• ESPP
• Retirement plans
• Competitive salaries

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You are a passionate and detail-oriented engineer with a strong foundation in electronics engineering or computer science. With over three years of hands-on experience in ASIC digital design, you thrive in fast-paced, collaborative environments where innovation and precision are paramount. Your expertise in IC design flows and methodologies, coupled with your familiarity with both digital and analog design principles, enables you to tackle complex engineering challenges with confidence and creativity.

What You'll Be Doing:

• Designing and implementing advanced ASIC digital circuits for high-performance semiconductor solutions.
• Applying deep knowledge of IC design flows and methodologies to optimize design processes and outcomes.
• Collaborating with cross-functional teams to integrate digital and analog design principles in complex projects.
• Utilizing industry-standard design tools and environments to ensure design integrity and functionality.
• Developing, optimizing, and maintaining embedded software to support ASIC projects and deliverables.
• Preparing and presenting comprehensive technical reports and project documentation to stakeholders.
• Coordinating and managing multiple technical deliverables to meet project timelines and quality benchmarks.

The Impact You Will Have:

• Accelerate the delivery of innovative semiconductor designs that power next-generation technologies.
• Enhance the quality and reliability of Synopsys' ASIC solutions through rigorous design and verification.
• Drive process improvements that increase engineering efficiency and reduce time-to-market.
• Facilitate knowledge sharing and technical excellence within the engineering team.
• Support customer success by delivering robust, well-documented solutions tailored to market needs.
• Strengthen Synopsys' leadership in high-performance silicon design through technical expertise and leadership.

What You'll Need:

• University degree in electronics engineering or computer science (or equivalent experience).
• At least 3 years' experience in ASIC digital design or a closely related field.
• Expertise in IC design flows, methodologies, and industry-standard EDA tools.
• Solid understanding of both digital and analog design principles.
• Proficiency in developing, optimizing, and maintaining embedded software.
• Experience with design tools and environments (e.g., RTL, Verilog/VHDL).
• Strong technical reporting and documentation skills.
• Project management experience, with the ability to coordinate multiple deliverables.

Benefits:

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

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You will play a critical role in supporting a high-growth, transformation-driven business by managing complex HR cases, driving key people initiatives, and ensuring consistency in HR practices across the region.

Responsibilities

People Support and Operational Effectiveness

• Provide clear and practical guidance to managers and employees on People policies, processes, and sensitive cases
• Support complex People operations issues and help improve service delivery, consistency, and employee experience across the region
• Contribute to more scalable and effective ways of working across teams and countries

Compliance, Labor Relations and Risk Support

• Support employee and manager matters related to performance, promotion, compensation, sick leave, and other policy topics, with a strong focus on consistency and compliance
• Support legal entity requirements, like state audits
• Partner with Employee Relations, Legal, and People Partners on disciplinary matters, involuntary terminations, and other higher-risk employee relations topics
• Support processes such as reduction in force, labor law and policy updates, and works council or trade union coordination
• Maintain assigned country or regional policies and knowledge-based content so information remains current, compliant, and useful

Manager Support, Data, and Change

• Support managers through organizational changes, team transitions, and implementation of People processes
• Help translate employee feedback and engagement insights into practical local or team-level actions
• Support integration and change activities, including leader transitions, new country setup or shutdown activity, and post-acquisition support
• Support Mergers and Acquisitions-related employment changes in partnership with relevant stakeholders

Performance and Employee Experience

• Support performance management processes across the region and coach managers on performance conversations and improvement planning within role scope
• Contribute to retention and employee experience efforts by identifying themes, supporting practical actions, and helping ensure People support is clear and credible
• Partner on manager capability-building and People process enablement as needed

Requirements

• Bachelor's degree in human resources, Business Administration, or a related field, or equivalent experience
• Solid human resources experience, ideally in a complex, multi-country environment
• Strong understanding of employment law, compliance, and human resources practices across multiple EMEA countries
• Demonstrated experience supporting employee relations, manager guidance, and operational People processes including performance management, terminations, and policy application
• Proficiency with human resources technology and using data to inform decisions
• Additional European language skills are valued, particularly German, French, or Spanish

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Over the past decade, you have developed deep expertise in diagnosing complex issues that span analog signal integrity, digital protocol implementation, and system-level interoperability, often working with incomplete information and demanding schedules.

Your knowledge of PCIe link training at 64 GT/s extends beyond theory into practical application.

You understand where PAM4 encoding can obscure margining issues, where FLIT mode negotiation may encounter difficulties, and how subtle impedance discontinuities can compromise bring-up success.

Your experience debugging customer systems has given you the ability to identify power delivery issues from oscilloscope measurements and recognize when firmware assumptions conflict with hardware implementation.

Leading technical discussions with customer architects and internal design teams is a natural extension of your work because you have established credibility through consistent results and deep technical knowledge.

You operate effectively without requiring exhaustive documentation, developing test plans, executing them, adapting as needed, and documenting findings to benefit future engineers.

Traveling approximately twice annually to customer sites or internal laboratories is an expected aspect of the role, and you recognize that on-site presence often accelerates resolution significantly.

At Synopsys, you will work with the most advanced SerDes IP in the industry, and your contributions will directly influence what our customers bring to market.

Responsibilities

• Provide senior-level technical support to customers during silicon bring-up and production phases for PCIe 6.0, PCIe 7.0, including on-site engagement when critical issues require direct technical presence
• Lead comprehensive root cause analysis for complex signal integrity, protocol compliance, and interoperability challenges across analog, digital, and system integration layers
• Utilize advanced laboratory instrumentation including high-bandwidth oscilloscopes, real-time spectrum analyzers, bit error rate testers, vector network analyzers, and protocol analyzers to perform precision measurements and isolate failure mechanisms at 64 GT/s and higher data rates
• Analyze and simulate Verilog/SystemVerilog RTL, collaborating with digital design and firmware teams to resolve issues involving PAM4 encoding, FLIT mode operation, and link training state machine behavior
• Drive technical engagements with customer engineering teams and system architects, translating technical findings into clear recommendations and design guidance
• Develop and refine test methodologies, debug procedures, and technical best practices for next-generation SerDes validation and customer deployment
• Travel approximately twice per year to customer locations or internal development sites for critical bring-up support and technical collaboration

The Impact You Will Have

• Enable customer tape-outs and production ramps by resolving technical blockers that would otherwise delay significant development programs
• Establish Synopsys as a recognized technical authority in PCIe 6.0/7.0 through substantive customer partnerships and effective technical problem resolution
• Provide real-world silicon and system-level insights to IP design, validation, and product development teams, improving quality and reducing time-to-market for future releases
• Reduce costly silicon re-spins by identifying and resolving subtle issues during initial bring-up phases that would otherwise manifest in volume production
• Develop the technical capabilities of applications and validation engineers across the organization through knowledge transfer and mentorship
• Contribute to the technical roadmap for SerDes applications engineering by identifying opportunities to improve tooling, processes, and support infrastructure
• Build enduring customer relationships that result in design wins and expanded IP adoption across next-generation semiconductor platforms

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related discipline with 10+ years of hands-on experience in post-silicon validation, applications engineering, or SerDes bring-up
• Extensive expertise with PCIe 6.0 or newer standards, including PAM4 signaling, FLIT mode operation, link training protocols, and compliance testing at 64 GT/s and above
• Demonstrated proficiency using advanced laboratory equipment including high-bandwidth oscilloscopes, real-time spectrum analyzers, bit error rate testers, vector network analyzers, and protocol analyzers for signal integrity and protocol debug
• Experience analyzing and simulating Verilog or SystemVerilog RTL to diagnose digital design issues affecting silicon behavior
• Solid understanding of high-speed printed circuit board design, signal integrity principles, power delivery architectures, and system-level integration is highly valuable
• Willingness to travel approximately twice per year for on-site customer support and internal technical collaboration

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Responsibilities

• Drive the design and development of medium to large complexity analog circuits for high-speed SerDes products supporting Ethernet and PCIe standards.
• Guide analog designers to ensure designs meet electrical specifications and reliability constraints.
• Define methods and procedures for project execution, including planning analog design activities and associated milestones.
• Conduct and prepare design reviews, follow up on improvements, and ensure high quality outcomes.
• Evaluate and minimize parasitic effects related to layout implementations, collaborate with layout teams to optimize performance, power, and area.
• Ensure silicon correlation with simulation results, validate design accuracy and robustness.
• Mentor and train less experienced analog designers, foster skill development within the team.
• Engage with a global, multi-cultural, and cross-functional R&D team, contribute to a collaborative and innovative work environment.

The Impact You Will Have

• Drive the development of industry-leading SerDes products used in diverse markets such as mobile, automotive, AI, HPC, IoT, 5G, and storage.
• Enhance product reliability and performance through rigorous design reviews and optimization practices.
• Drive innovation by implementing advanced FinFET/GAA process nodes in analog integrated circuits.
• Strengthen cross-functional collaboration, enabling seamless integration of analog and mixed signal designs.
• Contribute to Synopsys’ reputation as the provider of high-quality, silicon-proven IP solutions.
• Mentor and develop junior engineers, strengthening the team’s capability and talent pipeline for future challenges.

Requirements

• M.Sc. in Electrical Engineering with 8+ years of experience, or Ph.D. in Electrical Engineering with 6+ years of experience.
• Proven track record in CMOS analog design, preferably including hands-on experience with ADC, DAC, PLL, Rx, Tx, References, etc.
• Experience coordinating design activities across teams and managing medium complexity designs.
• Familiarity with industry-standard IC design packages and EDA tools.
• Experience working in UNIX operating systems.
• System-level knowledge of SerDes architecture is a plus.
• Strong written and verbal communication skills in English.

Benefits

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

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As an experienced analog design engineer, you will be responsible for driving the design and development of medium to large complexity analog circuits for high-speed SerDes products supporting Ethernet and PCIe standards. You will guide analog designers to ensure designs meet electrical specifications and reliability constraints. You will also define methods and procedures for project execution, including planning analog design activities and associated milestones.

You will conduct and prepare design reviews, following up on improvements, and ensuring high quality outcomes. You will evaluate and minimize parasitic effects related to layout implementations, collaborating with layout teams to optimize performance, power, and area. You will ensure silicon correlation with simulation results, validating design accuracy and robustness.

You will mentor and train less experienced analog designers, fostering skill development within the team. You will engage with a global, multi-cultural, and cross-functional R&D team, contributing to a collaborative and innovative work environment.

The successful candidate will have a proven track record in CMOS analog design, preferably including hands-on experience with ADC, DAC, PLL, Rx, Tx, References, etc. They will have experience coordinating design activities across teams and managing medium complexity designs. They will be familiar with industry-standard IC design packages and EDA tools.

The ideal candidate will be a collaborative team player who thrives in multicultural, global environments. They will be an analytical thinker with strong problem-solving and organizational skills. They will be an effective communicator, able to lead reviews and share knowledge clearly.

The team you will be a part of is Synopsys' fast-growing analog and mixed-signal R&D team, dedicated to developing the highest data rate SerDes IP in advanced FinFET/GAA process nodes. The team is global, dynamic, and cross-functional, working collaboratively to deliver world-class products that power innovations across multiple industries.

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