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problem-solving"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5e9e8dd2-316"},"title":"Staff Engineer, Design Verification - High-Speed Interface IP","description":"<p>You are an experienced Digital Verification engineer who enjoys solving complex verification challenges in high-speed digital designs.</p>\n<p>You will develop and execute verification strategies for complex ASIC and digital IP designs.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Develop and execute verification strategies for complex ASIC and digital IP designs.</li>\n<li>Build, enhance, and maintain verification environments for high-speed digital interfaces.</li>\n<li>Develop test plans, test cases, stimulus, checkers, and coverage models to achieve verification objectives.</li>\n<li>Verify functionality of designs involving high-speed protocols, particularly PCI/PCIe and USB.</li>\n<li>Debug simulation failures and collaborate with RTL design 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You are passionate about deepening your expertise and excited by the opportunity to work on advanced DDR/HBM/PCIe/UCIe/Ethernet/UALink IP integration deployed in the most innovative SoCs.</p>\n<p><strong>What You&#39;ll Be Doing:</strong></p>\n<ul>\n<li>Technically leading and driving ownership of critical areas of verification alongside a team of talented verification engineers.</li>\n<li>Defining, implementing, and tracking comprehensive verification test plans to ensure robust coverage and quality.</li>\n<li>Specifying, building, enhancing, and maintaining state-of-the-art Subsystem top-level UVM-based System Verilog testbenches, integrating RTL and behavioral models.</li>\n<li>Coding and debugging test cases, including the creation of complex checkers and assertions using System Verilog/UVM.</li>\n<li>Extracting and reviewing functional coverage (FC) and code coverage metrics to ensure quality metric goals are met.</li>\n<li>Managing regressions and contributing to the continuous improvement of verification strategies and test environments.</li>\n<li>Debugging and resolving simulation failures, ensuring root-cause analysis and timely solutions.</li>\n<li>Working closely with RTL designers and architects to ensure functional correctness.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Drive quality that powers AI, automotive, cloud, and mobile applications at massive scale.</li>\n<li>Advance the state-of-the-art in AI-assisted verification methodologies, influencing future verification flows and processes.</li>\n<li>Contribute to the early detection and resolution of critical design issues, reducing time-to-market and silicon re-spins.</li>\n<li>Collaborate with a global team of experienced verification engineers, fostering knowledge sharing and professional growth.</li>\n<li>Bolster Synopsys&#39; leadership in chip design by ensuring our IP verification methodologies set industry standards.</li>\n</ul>\n<p><strong>What You&#39;ll Need:</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in electronics/electrical engineering or related field, with 8+ years’ experience in ASIC/FPGA Verification.</li>\n<li>Ability to debug and define robust verification strategies; experience mentoring is a plus for senior candidates.</li>\n<li>Demonstrated experience in technically leading a team, record of successful collaboration and stakeholder management.</li>\n<li>Proven expertise in developing System Verilog/UVM-based test environments for complex ASIC designs.</li>\n<li>Advanced skills in developing and implementing rigorous test plans, checkers, assertions, and coding complex tests.</li>\n<li>Strong proficiency in extracting and analyzing verification metrics such as functional coverage and code coverage.</li>\n<li>Experience with interface protocols and IP design/verification processes; knowledge of DDR/HBM/PCIe/UCIe/Ethernet/UALink is highly desirable.</li>\n<li>Hands-on experience in owning end-to-end verification deliverables for IPs, including planning, execution, DV metrics closure, and review/signoff.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Analytical and detail-oriented, with strong problem-solving and debugging skills.</li>\n<li>Initiative-taking and driven to deliver high-quality results in a fast-paced environment.</li>\n<li>Seeking feedback, sharing knowledge, and mentoring others when possible.</li>\n<li>Collaborative leader who inspires and mentors team members to achieve their best.</li>\n<li>Analytical thinker with strong critical thinking skills and a commitment to quality.</li>\n<li>Exceptional communicator, able to bridge technical and non-technical stakeholders.</li>\n<li>Self-motivated and proactive, with a passion for continuous learning and professional development.</li>\n<li>Adaptable and resilient in the face of complex challenges and changing priorities.</li>\n</ul>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_38152456-4ad","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/asic-digital-design-sr-staff-engineer/44408/101910955696?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC/FPGA Verification","System Verilog/UVM","RTL design","Verification methodologies"],"x-skills-preferred":["DDR/HBM/PCIe/UCIe/Ethernet/UALink","Mentoring","Team leadership"],"datePosted":"2026-10-14T07:07:34.629Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida, Uttar Pradesh"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC/FPGA Verification, System Verilog/UVM, RTL design, Verification methodologies, DDR/HBM/PCIe/UCIe/Ethernet/UALink, Mentoring, Team leadership"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_a9651295-968"},"title":"R&D Engineering, Staff Engineer","description":"<p>Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing.</p>\n<p>You are someone who has spent the last couple of years getting your hands dirty with embedded memory design and you are ready to go deeper. You have worked with SRAM, ROM, or Register Files enough to know that the details matter, that a small circuit decision ripples through characterization, layout, and eventually into silicon.</p>\n<p><strong>What You&#39;ll Be Doing</strong></p>\n<ul>\n<li>Design and simulate embedded memory circuits including SRAM, ROM, and Register Files using Cadence Virtuoso and related tools</li>\n<li>Support layout activities by working with layout engineers to ensure design intent translates cleanly into physical implementation</li>\n<li>Run bitcell characterization and basic reliability analysis to validate performance across process, voltage, and temperature corners</li>\n<li>Debug circuit-level issues by analyzing simulation results, identifying root causes, and proposing fixes with guidance from senior engineers</li>\n<li>Collaborate with CAD, verification, and frontend teams to align on design requirements, timing constraints, and integration needs</li>\n<li>Write and maintain technical documentation including design notes, simulation reports, and analysis summaries</li>\n<li>Use scripting in C-Shell, Perl, or Python to automate repetitive tasks and improve design flow efficiency</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Deliver memory IP blocks that meet performance, power, and area targets for high-volume semiconductor products</li>\n<li>Reduce design iteration cycles by catching issues early through thorough simulation and analysis</li>\n<li>Improve design quality and reliability by contributing to characterization and validation efforts</li>\n<li>Enable faster time-to-market for Synopsys customers by supporting robust and well-documented memory solutions</li>\n<li>Build reusable design methodologies and scripts that make future projects more efficient</li>\n<li>Strengthen cross-functional collaboration by clearly communicating design decisions and technical tradeoffs</li>\n<li>Grow into a more senior role by mastering the fundamentals of memory circuit design in a production environment</li>\n</ul>\n<p><strong>What You&#39;ll Need</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering, Electronics Engineering, or a related technical field</li>\n<li>5+ years of hands-on experience in CMOS circuit design, specifically with embedded memory such as SRAM, ROM, or Register Files</li>\n<li>Working knowledge of memory architectures, bitcell design, and circuit fundamentals including read/write operations and sense amplifier behavior</li>\n<li>Experience using Cadence Virtuoso or similar tools for schematic capture, simulation, and layout interaction</li>\n<li>Exposure to scripting languages like C-Shell, Perl, or Python is a plus and will help you automate workflows and analyze data more effectively</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_a9651295-968","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/r-and-d-engineering-staff-engineer/44408/101703888528?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["Cadence Virtuoso","CMOS circuit design","embedded memory design","SRAM","ROM","Register Files","C-Shell","Perl","Python"],"x-skills-preferred":[],"datePosted":"2026-10-09T06:36:03.686Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida, Uttar Pradesh"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"Cadence Virtuoso, CMOS circuit design, embedded memory design, SRAM, ROM, Register Files, C-Shell, Perl, Python"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_820ea548-9ed"},"title":"R&D Engineering, Sr Manager","description":"<p>Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.</p>\n<p>You have spent a decade building embedded memory IP that actually ships in production silicon, not just test chips that look good in papers. Managing teams through the full arc of SRAM, register file, and TCAM development has taught you that the hardest decisions happen early, at the architecture and bit cell level, and you have learned to guide engineers toward choices that hold up through tapeout and beyond.</p>\n<p>At Synopsys, you will lead memory IP development that powers the most advanced semiconductor designs in the world.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Lead a cross-functional team through the complete embedded memory development cycle, from bit cell analysis and architecture definition through circuit design, layout, verification, characterization, and model generation</li>\n<li>Drive SRAM, register file, TCAM, and ROM compiler development, balancing performance, power, area, and yield across advanced FinFET technology nodes</li>\n<li>Own schematic entry, transistor-level simulation, layout planning, and interface with CAD teams for full physical verification and timing model delivery</li>\n<li>Design and implement low-power, area-efficient memory circuits and architectures optimized for deep submicron and FinFET process variations</li>\n<li>Coordinate daily activities across your engineering team, prioritize workloads across multiple concurrent projects, and proactively address issues impacting schedule or quality</li>\n<li>Collaborate with internal teams and external customers to resolve technical challenges, align on solutions, and ensure memory IP meets functional and performance requirements</li>\n<li>Ramp quickly on existing flows, identify gaps or inefficiencies, and produce actionable work plans that drive projects to completion on aggressive timelines</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Your team will deliver production-ready memory compilers that enable customers to build complex SoCs at the most advanced process nodes</li>\n<li>Architectural and circuit decisions you guide will directly affect power, performance, and area outcomes in chips used across AI, mobile, automotive, and data center applications</li>\n<li>Memory IP you ship will be integrated into designs at scale, affecting yield, time-to-market, and product success for Synopsys customers globally</li>\n<li>Process improvements and automation you implement will increase team productivity and reduce development cycle time across future memory platforms</li>\n<li>Engineers you mentor will grow their skills in advanced circuit design, FinFET technology, and memory compiler automation, strengthening the team&#39;s long-term capability</li>\n<li>Technical solutions you drive will resolve cross-discipline challenges spanning circuit design, physical implementation, characterization, and modeling</li>\n<li>Your ability to deliver on schedule will enable downstream teams in verification, integration, and customer engagement to execute without delay</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>10+ years of hands-on experience in embedded memory design, covering architecture, circuit design, physical implementation, compiler automation, characterization, and model generation</li>\n<li>BE/B.Tech/ME/M.Tech/MS in Electrical and Electronics Engineering</li>\n<li>Deep expertise in SRAM and register file architectures, including custom circuit techniques for sense amplifiers, write drivers, decoders, and bit cells</li>\n<li>Direct experience designing memory IP in advanced FinFET technology nodes, with strong understanding of variation-aware design, leakage management, and yield optimization</li>\n<li>Proficiency in scripting using Perl and Python for automation of design flows, characterization, and model generation</li>\n<li>Solid grounding in CMOS fundamentals, RC circuit analysis, digital design, and analog circuit basics, with practical application in memory design contexts</li>\n<li>Proven ability to lead engineering teams, manage multiple projects simultaneously, and deliver complex IP on schedule in a cross-site, multi-discipline environment</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family</li>\n<li>Time away: company holidays, ETO and FTO Programs</li>\n<li>Family support: maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back</li>\n<li>Retirement plans: save for your future with our retirement plans that vary by region and country</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_820ea548-9ed","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/r-and-d-engineering-sr-manager/44408/101661090688?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["embedded memory design","SRAM","register file architectures","FinFET technology","Perl","Python","CMOS fundamentals","RC circuit analysis","digital design","analog circuit basics"],"x-skills-preferred":[],"datePosted":"2026-10-08T05:16:02.334Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida, Uttar Pradesh"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"embedded memory design, SRAM, register file architectures, FinFET technology, Perl, Python, CMOS fundamentals, RC circuit analysis, digital design, analog circuit basics"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_0b6ff65e-335"},"title":"Technical/Product Publications, Sr Engineer","description":"<p>We are seeking a Senior Technical Writer to join our team at Synopsys, a leading provider of engineering solutions from silicon to systems. As a Technical/Product Publications, Sr Engineer, you will play a critical role in creating and maintaining customer documentation for products that power semiconductor development worldwide.</p>\n<p>You will work on customer-facing documentation, using DITA XML in Adobe FrameMaker or Oxygen XML, structuring content for reuse, modularity, and multi-format publishing. Your responsibilities will include:</p>\n<ul>\n<li>Creating and maintaining customer documentation using DITA XML</li>\n<li>Working directly with developers, product managers, QA engineers, and SMEs to collect technical information and validate accuracy</li>\n<li>Analyzing product functionality and translating it into task-based, user-focused documentation</li>\n<li>Reviewing and editing documentation for technical accuracy, grammar, terminology consistency, and adherence to Synopsys style guidelines</li>\n<li>Managing documentation updates aligned with product release schedules</li>\n<li>Creating and maintaining supporting content such as screenshots, diagrams, workflows, tables, and illustrations</li>\n</ul>\n<p>The impact you will have includes:</p>\n<ul>\n<li>Enabling customers to adopt and use Synopsys EDA and IP products more effectively through clear, accurate documentation</li>\n<li>Reducing support escalations by ensuring engineers can find answers in the documentation</li>\n<li>Improving documentation consistency and reusability across product lines</li>\n<li>Accelerating product launches by delivering documentation that meets release milestones</li>\n<li>Strengthening the quality bar for technical content across the organization</li>\n</ul>\n<p>To be successful in this role, you will need:</p>\n<ul>\n<li>2 to 4 years of professional experience in technical writing, ideally for software or technology products</li>\n<li>A Bachelor&#39;s degree in Computer Science, Information Technology, Engineering, or equivalent discipline</li>\n<li>Hands-on experience with DITA XML concepts, including topics, maps, content reuse, conditional content, and cross-references</li>\n<li>Proficiency in Adobe FrameMaker or Oxygen XML for structured authoring and publishing</li>\n<li>Strong command of technical communication fundamentals like task-based writing, information architecture, and content structuring</li>\n<li>Familiarity with version control systems such as Git or Perforce</li>\n<li>Experience with MS Visio for creating technical diagrams and process flows is a plus</li>\n</ul>\n<p>In return, we offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_0b6ff65e-335","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/technical-product-publications-sr-engineer/44408/101403651104?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["DITA XML","Adobe FrameMaker","Oxygen XML","technical writing","content structuring","information architecture","task-based writing","Git","Perforce","MS Visio"],"x-skills-preferred":["AI tools for content drafting, summarization, or quality improvement"],"datePosted":"2026-10-02T02:06:48.962Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida, Uttar Pradesh"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"DITA XML, Adobe FrameMaker, Oxygen XML, technical writing, content structuring, information architecture, task-based writing, Git, Perforce, MS Visio, AI tools for content drafting, summarization, or quality improvement"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_ea47c380-e8d"},"title":"Layout Design, Staff Engineer","description":"<p><strong>Overview</strong></p>\n<p>We&#39;re looking for a Layout Design, Staff Engineer at Synopsys, a leading provider of engineering solutions from silicon to systems.</p>\n<p><strong>Job Description</strong></p>\n<p>As a Layout Design, Staff Engineer, you will design and develop cutting-edge semiconductor solutions, focusing on custom memory layout, particularly for SRAM, Register Files, ROM, and related memory compiler IP blocks.</p>\n<p><strong>Key Responsibilities</strong></p>\n<ul>\n<li>Design and own custom layouts for SRAM, Register Files, ROM, and related memory compiler IP blocks from floorplan through final signoff</li>\n<li>Execute and close DRC, LVS, ERC, antenna, density, and reliability checks using Virtuoso and physical verification tools</li>\n<li>Drive technology node migrations for memory compilers, resolving layout and verification issues that emerge with new process rules</li>\n<li>Collaborate directly with circuit designers to ensure schematic-layout correlation, device matching, symmetry, and design intent are preserved</li>\n<li>Develop and refine layout methodologies, automation scripts in Tcl, Perl, or Python, and best practices that improve team efficiency and design quality</li>\n<li>Review layouts created by junior engineers, provide technical guidance, and mentor on complex layout challenges</li>\n<li>Support customer-specific memory customization projects, working through optimization requests and delivering production-ready IP</li>\n</ul>\n<p><strong>What You&#39;ll Need</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electronics, VLSI, Microelectronics, or a related technical field</li>\n<li>8 to 10 years of hands-on experience in custom memory layout design, specifically SRAM, Register Files, ROM, or memory compiler development</li>\n<li>Strong proficiency with custom layout tools such as Cadence Virtuoso or equivalent platforms</li>\n<li>Demonstrated expertise in DRC/LVS closure, device matching and symmetry, and analog/custom layout techniques</li>\n<li>Deep understanding of CMOS layout fundamentals, memory architecture, and FinFET technology nodes</li>\n<li>Experience with parasitic extraction and physical verification flows, and the ability to interpret and act on results</li>\n<li>Familiarity with scripting in Tcl, Perl, or Python for layout automation is a strong plus</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs, including:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans</li>\n<li>Time away programs</li>\n<li>Family support, including maternity and paternity leave</li>\n<li>ESPP (Employee Stock Purchase Plan)</li>\n<li>Retirement plans</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_ea47c380-e8d","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/layout-design-staff-engineer/44408/101119414160?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["custom memory layout design","Cadence Virtuoso","DRC/LVS closure","device matching and symmetry","analog/custom layout techniques","CMOS layout fundamentals","memory architecture","FinFET technology nodes","parasitic extraction","physical verification flows","Tcl","Perl","Python"],"x-skills-preferred":[],"datePosted":"2026-09-26T00:16:29.394Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida, Uttar Pradesh"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"custom memory layout design, Cadence Virtuoso, DRC/LVS closure, device matching and symmetry, analog/custom layout techniques, CMOS layout fundamentals, memory architecture, FinFET technology nodes, parasitic extraction, physical verification flows, Tcl, Perl, Python"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_51cf79c3-9c0"},"title":"Staff/ Sr Staff DFT Solutions Engineer","description":"<p>You are a seasoned DFT Solutions Engineer with expertise in digital IC design, DFT planning, and test solutions. You will deliver end-to-end DFT solutions for customer designs, from architecture planning and scan insertion through pattern generation, silicon bring-up, and diagnostics analysis.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Implement and validate test solutions including scan, MBIST, and IEEE 1687 architectures for complex SoCs with multiple IP blocks</li>\n<li>Participate in customer design reviews to understand their flows, identify gaps, and propose specific improvements that reduce test time or increase coverage</li>\n<li>Prototype and validate new DFT methodologies in collaboration with Solution Architects, proving out viability before customer deployment</li>\n<li>Provide technical support and training to customers, including hands-on problem resolution, methodology workshops, and account-level engagement</li>\n<li>Conduct product demonstrations, competitive benchmarking, and evaluations to help win new customers and expand adoption of Synopsys test solutions</li>\n<li>Analyze silicon test data, diagnose failures, and present findings to both internal teams and customer stakeholders with clear recommendations</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Enable first-time silicon success for customers by delivering robust, validated DFT solutions that catch issues before tapeout</li>\n<li>Accelerate time-to-market for automotive and consumer electronics customers by optimizing their test flows and reducing pattern generation cycles</li>\n<li>Expand Synopsys&#39; footprint in next-generation test technologies by proving out new methodologies that become standard practice across accounts</li>\n<li>Build long-term customer relationships that turn one-time engagements into strategic partnerships, increasing account value and retention</li>\n<li>Raise the technical capability of customer teams through training and knowledge transfer, creating a multiplier effect beyond individual projects</li>\n<li>Shape the direction of Synopsys test products by feeding real-world customer challenges and use cases back to R&amp;D teams</li>\n<li>Contribute to measurable improvements in test coverage, pattern count reduction, and silicon yield across diverse customer programs</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Bachelor&#39;s degree with 7+ years or Master&#39;s degree with 5+ years in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field</li>\n<li>Hands-on experience with RTL coding, DFT insertion, ATPG pattern generation, and silicon bring-up for digital ICs</li>\n<li>Deep knowledge of scan architectures, fault models, test access networks, and IEEE standards including 1149.1, 1500, and 1687</li>\n<li>Proven ability to handle scan implementation and validation for large, multi-IP SoCs with complex hierarchies and multiple clock domains</li>\n<li>Experience with MBIST concepts, architecture planning, and integration in automotive or safety-critical design environments is a strong plus</li>\n<li>Familiarity with industry-standard DFT tools and flows, exposure to Synopsys TetraMAX, DFT Compiler, or MBIST Architect is valuable</li>\n<li>Strong written and verbal communication skills to translate technical concepts for both engineering teams and non-technical stakeholders</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family</li>\n<li>In addition to company holidays, we have ETO and FTO Programs</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back</li>\n<li>Save for your future with our retirement plans that vary by region and country</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_51cf79c3-9c0","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/staff-sr-staff-dft-solutions-engineer/44408/101071131408?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["DFT","digital IC design","scan architectures","fault models","test access networks","IEEE standards","RTL coding","ATPG pattern generation","silicon bring-up"],"x-skills-preferred":["MBIST","automotive design","safety-critical design","Synopsys TetraMAX","DFT Compiler","MBIST Architect"],"datePosted":"2026-09-24T23:42:23.101Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida, Uttar Pradesh"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"DFT, digital IC design, scan architectures, fault models, test access networks, IEEE standards, RTL coding, ATPG pattern generation, silicon bring-up, MBIST, automotive design, safety-critical design, Synopsys TetraMAX, DFT Compiler, MBIST Architect"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_53d71267-801"},"title":"R&D Engineering, Sr Engineer","description":"<p>Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing.</p>\n<p>You are someone who has spent the last couple of years getting your hands dirty with embedded memory design and you are ready to go deeper. You have worked with SRAM, ROM, or Register Files enough to know that the details matter, that a small circuit decision ripples through characterization, layout, and eventually into silicon.</p>\n<p><strong>What You&#39;ll Be Doing</strong></p>\n<ul>\n<li>Design and simulate embedded memory circuits including SRAM, ROM, and Register Files using Cadence Virtuoso and related tools</li>\n<li>Support layout activities by working with layout engineers to ensure design intent translates cleanly into physical implementation</li>\n<li>Run bitcell characterization and basic reliability analysis to validate performance across process, voltage, and temperature corners</li>\n<li>Debug circuit-level issues by analyzing simulation results, identifying root causes, and proposing fixes with guidance from senior engineers</li>\n<li>Collaborate with CAD, verification, and frontend teams to align on design requirements, timing constraints, and integration needs</li>\n<li>Write and maintain technical documentation including design notes, simulation reports, and analysis summaries</li>\n<li>Use scripting in C-Shell, Perl, or Python to automate repetitive tasks and improve design flow efficiency</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Deliver memory IP blocks that meet performance, power, and area targets for high-volume semiconductor products</li>\n<li>Reduce design iteration cycles by catching issues early through thorough simulation and analysis</li>\n<li>Improve design quality and reliability by contributing to characterization and validation efforts</li>\n<li>Enable faster time-to-market for Synopsys customers by supporting robust and well-documented memory solutions</li>\n<li>Build reusable design methodologies and scripts that make future projects more efficient</li>\n<li>Strengthen cross-functional collaboration by clearly communicating design decisions and technical tradeoffs</li>\n<li>Grow into a more senior role by mastering the fundamentals of memory circuit design in a production environment</li>\n</ul>\n<p><strong>What You&#39;ll Need</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering, Electronics Engineering, or a related technical field</li>\n<li>1 to 3 years of hands-on experience in CMOS circuit design, specifically with embedded memory such as SRAM, ROM, or Register Files</li>\n<li>Working knowledge of memory architectures, bitcell design, and circuit fundamentals including read/write operations and sense amplifier behavior</li>\n<li>Experience using Cadence Virtuoso or similar tools for schematic capture, simulation, and layout interaction</li>\n<li>Exposure to scripting languages like C-Shell, Perl, or Python is a plus and will help you automate workflows and analyze data more effectively</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_53d71267-801","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/r-and-d-engineering-sr-engineer/44408/101040901200?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Cadence Virtuoso","CMOS circuit design","embedded memory design","scripting languages like C-Shell, Perl, or Python"],"x-skills-preferred":[],"datePosted":"2026-09-23T22:05:33.221Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida, Uttar Pradesh"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Cadence Virtuoso, CMOS circuit design, embedded memory design, scripting languages like C-Shell, Perl, or Python"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_6de74803-71f"},"title":"Musketeer Scout","description":"<p>We&#39;re seeking a Musketeer Scout to join our team in Noida, India. As a Musketeer Scout, you will be responsible for expanding our distribution and sales force in the catering and &#39;at work&#39; channels.</p>\n<p><strong>Key Responsibilities:</strong></p>\n<ul>\n<li>Analyze customer potential and develop optimal tour planning to achieve targets and goals</li>\n<li>Acquire new customers in the catering and &#39;at work&#39; channels</li>\n<li>Present and place our product family effectively</li>\n<li>Collaborate with the National Key Account Team to ensure product presence at relevant events and objects</li>\n<li>Build relationships with key stakeholders and business partners</li>\n<li>Identify opportunities and drive sales and marketing initiatives</li>\n</ul>\n<p><strong>Requirements:</strong></p>\n<ul>\n<li>Minimum Bachelor&#39;s degree with at least 6 months of experience</li>\n<li>Experience in field sales or food retail</li>\n<li>IT savvy with a laptop, tablet, mobile phone, and related standard software</li>\n<li>Flexible and able to work independently</li>\n<li>Strong communication and sales skills</li>\n</ul>\n<p><strong>Benefits:</strong></p>\n<ul>\n<li>Opportunity to work with a global brand</li>\n<li>Flexibility and autonomy in your work</li>\n<li>Collaborative and dynamic work environment</li>\n</ul>\n<p><strong>Travel:</strong></p>\n<ul>\n<li>50-60% travel required</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_6de74803-71f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Red Bull","sameAs":"https://jobs.redbull.com","logo":"https://logos.yubhub.co/jobs.redbull.com.png"},"x-apply-url":"https://jobs.redbull.com/in-en/musketeer-ref34130y?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"entry","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["sales","marketing","communication","field sales","food retail"],"x-skills-preferred":[],"datePosted":"2026-09-21T18:07:02.597Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida, Uttar Pradesh"}},"employmentType":"FULL_TIME","occupationalCategory":"Sales","industry":"Beverages","skills":"sales, marketing, communication, field sales, food retail"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_14ae10d7-5b0"},"title":"SoC RTL Design - Sr Staff","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You have spent years building and signing off RTL that actually ships in silicon, not just passes simulation. The difference between a design that tapes out clean and one that comes back with a respin is usually a clock domain crossing someone missed or a constraint someone wrote too loosely, and you are the engineer who catches those things before they become problems.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Run RTL quality signoff using Spyglass for LINT, CDC, and RDC checks across IP blocks, subsystems, and full SoC designs</li>\n<li>Develop timing constraints in SDC for synthesis and static timing analysis, ensuring constraints accurately reflect design intent and architecture</li>\n<li>Execute preliminary synthesis runs using Design Compiler or Fusion Compiler to validate RTL synthesizability, area, and timing feasibility before handoff</li>\n<li>Perform formal equivalence checking with Formality to verify RTL-to-gate consistency across design revisions and ECOs</li>\n<li>Integrate third-party and Synopsys IP into customer SoCs and subsystems, resolving integration issues related to clocking, reset, and interface protocols</li>\n<li>Create and modify RTL design blocks to meet customer-specific requirements, working within established design guidelines and delivery timelines</li>\n<li>Collaborate with verification, implementation, and architecture teams to close signoff issues and ensure RTL quality gates are met before tapeout</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Your signoff rigor directly reduces respin risk for customers building chips in advanced nodes where a single CDC bug can cost months and millions</li>\n<li>The constraints you write become the foundation for physical implementation teams to close timing, making or breaking their ability to meet PPA targets</li>\n<li>Your synthesis validation catches architectural mismatches early, preventing costly surprises downstream in place and route</li>\n<li>The IP integrations you deliver enable startups and tier-one customers to meet aggressive tapeout schedules with confidence in design quality</li>\n<li>Your expertise in static verification tools shapes internal methodology, raising the bar for what clean RTL means across the System Solutions Group</li>\n<li>The RTL you design and integrate becomes part of production SoCs powering AI, automotive, 5G, and IoT applications in the field</li>\n<li>Your work helps Synopsys customers tape out some of the most complex and challenging semiconductor designs in the industry</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s in Electronics Engineering, Electrical Engineering, or Computer Engineering with 8+ years of hands-on experience in RTL design and verification</li>\n<li>Proven experience performing static verification using Spyglass or equivalent tools for LINT, CDC, and RDC analysis on complex digital designs</li>\n<li>Strong working knowledge of synthesis tools such as Design Compiler or Fusion Compiler, including constraint development and synthesis quality checks</li>\n<li>Hands-on experience with Formality or equivalent formal verification tools for RTL-to-gate equivalence checking</li>\n<li>Solid conceptual understanding of clock domain crossing, reset domain crossing, and common design pitfalls that lead to metastability or functional failures</li>\n<li>Experience integrating IP blocks into subsystems or SoCs, including resolving interface, clocking, and protocol issues</li>\n<li>Familiarity with scripting in Tcl, Python, or Perl to automate checks, reporting, and design flows is a strong plus</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family</li>\n<li>Time away: company holidays, ETO, and FTO Programs</li>\n<li>Family support: maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back</li>\n<li>Retirement plans: save for your future with our retirement plans that vary by region and country</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_14ae10d7-5b0","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/soc-rtl-design-sr-staff/44408/100812692192?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design","verification","Spyglass","SDC","Design Compiler","Fusion Compiler","Formality","clock domain crossing","reset domain crossing"],"x-skills-preferred":["Tcl","Python","Perl"],"datePosted":"2026-09-18T20:16:39.281Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida, Uttar Pradesh"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design, verification, Spyglass, SDC, Design Compiler, Fusion Compiler, Formality, clock domain crossing, reset domain crossing, Tcl, Python, Perl"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c4eead04-284"},"title":"DFT Staff Engineer- SoC Engineering","description":"<p><strong>Job Title: DFT Staff Engineer</strong></p>\n<p><strong>Overview</strong></p>\n<p>You will be part of the Systems Solutions Group (SSG) at Synopsys, working on designing and developing cutting-edge semiconductor solutions as a DFT Staff Engineer. You will own DFT architecture, implementation, integration, and verification for complex SoCs and subsystems from specification through tapeout.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Own DFT architecture, implementation, integration, and verification for complex SoCs and subsystems from specification through tapeout, working directly with customer and internal design teams.</li>\n<li>Define and execute test strategies across scan insertion and ATPG, memory BIST, logic BIST, and analog/PHY test considerations to meet coverage, quality, yield, and cost targets.</li>\n<li>Drive DFT signoff readiness by identifying testability risks early, proposing design changes, and ensuring closure across the RTL-to-GDS flow.</li>\n<li>Develop and institutionalize reusable DFT methodologies, checklists, and guidelines using Synopsys EDA tools to solve real customer problems on active service projects.</li>\n<li>Partner with silicon validation and test engineering teams on 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gone to production.</li>\n<li>Strong working knowledge of Synopsys DFT tools such as TetraMAX, DFT Compiler, and BIST Architect is a plus.</li>\n<li>Proven ability to work cross-functionally to resolve testability issues and drive closure under schedule constraints.</li>\n<li>Post-silicon debug experience and collaboration with test engineering teams to refine production test programs is a plus.</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.</li>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n<li>Competitive salaries.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c4eead04-284","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/dft-staff-engineer-soc-engineering/44408/98376860896?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["DFT","SoC","scan/ATPG","memory BIST","logic BIST","analog test considerations","Synopsys DFT tools"],"x-skills-preferred":["post-silicon debug","collaboration with test engineering teams"],"datePosted":"2026-09-15T18:04:23.271Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida, Uttar Pradesh"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"DFT, SoC, scan/ATPG, memory BIST, logic BIST, analog test considerations, Synopsys DFT tools, post-silicon debug, collaboration with test engineering teams"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_a1d323fb-646"},"title":"Staff Project Engineering Manager","description":"<p>You will lead SerDes PHY IP projects that power the next generation of high-speed connectivity in everything from data centers to automotive systems.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Manage end-to-end delivery of high-speed SerDes PHY IP projects from definition through tapeout and customer deployment</li>\n<li>Lead cross-functional project teams including design engineers, verification engineers, and layout specialists to execute against aggressive schedules</li>\n<li>Partner with R&amp;D and Marketing to define project roadmaps, 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for industry-standard protocols including AMBA, PCIe, USB, Ethernet, UEC, UAL, and MIPI</li>\n<li>Build comprehensive verification plans that map protocol specifications to testable scenarios, coverage goals, and corner case strategies</li>\n<li>Code sequences, test scenarios, and checkers that drive coverage-based verification across functional and code coverage dimensions</li>\n<li>Debug complex simulation failures across multi-layer protocol stacks, identifying root causes in both VIP logic and customer integration environments</li>\n<li>Enhance existing VIP products for performance, reusability, and scalability as protocols evolve and customer use cases expand</li>\n<li>Support customers during VIP integration and deployment, troubleshooting issues, answering technical questions, and ensuring successful bring-up</li>\n<li>Collaborate with Design IP teams, R&amp;D engineers, and field application teams to align VIP capabilities with product roadmaps and customer needs</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Your VIP will enable faster, more reliable verification for semiconductor companies building next-generation SoCs and AI-powered products</li>\n<li>Coverage-driven verification strategies you implement will catch critical protocol violations before they reach silicon, saving months of debug time downstream</li>\n<li>Enhancements you make to existing VIP products will improve performance and expand protocol support across the Synopsys IP portfolio</li>\n<li>Customer deployments you support will directly influence how engineers at leading semiconductor companies adopt and trust Synopsys VIP</li>\n<li>Verification plans you create will set the standard for how protocol compliance is validated across complex, multi-protocol designs</li>\n<li>Collaboration with Design IP teams will tighten the feedback loop between design and verification, improving quality across both disciplines</li>\n<li>Your work will contribute to a VIP product line used globally in semiconductor development, affecting how chips are verified at scale</li>\n</ul>\n<p><strong>What You&#39;ll Need</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electronics Engineering, Computer Science, or equivalent practical experience</li>\n<li>5+ years of hands-on experience developing Verification IP</li>\n<li>Strong proficiency in SystemVerilog and UVM methodology for building reusable, scalable verification environments</li>\n<li>Specializing in NVMe protocols (mandatory) and PCIe (desirable) or Deep working knowledge of at least two industry-standard protocols USB, Ethernet or MIPI</li>\n<li>The ideal candidate should have hands-on experience with BFM, IP, or VIP development and integration.</li>\n<li>The role requires a solid understanding of verification methodologies and protocol compliance. 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are looking for someone who brings deep expertise in analog and mixed-signal layout, along with the leadership to improve execution at scale through AI-enabled productivity, automation, and methodology innovation. At Synopsys, you will work on SerDes analog layout in advanced nodes, lead execution across complex programs, and help modernize how layout engineering gets done.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Lead delivery of SerDes analog layout programs in advanced process nodes, owning execution quality, schedule predictability, and technical risk management</li>\n<li>Drive layout methodology improvements across floorplanning, matching, shielding, ESD integration, and physical verification workflows</li>\n<li>Collaborate regularly with design engineers, ESD teams, reliability engineers, CAD teams, and program managers to align layout execution with design intent and program milestones</li>\n<li>Deploy automation, scripting, dashboards, and AI-assisted workflows to reduce manual effort, improve consistency, and scale engineering productivity</li>\n<li>Mentor layout engineers on advanced techniques, design tradeoffs, and execution rigor, raising the technical bar across the team</li>\n<li>Influence cross-functional decisions on layout planning, resource allocation, tool adoption, and process improvements</li>\n</ul>\n<p>Impact:</p>\n<ul>\n<li>Deliver high-speed analog layouts that meet performance, reliability, and manufacturability requirements in advanced nodes</li>\n<li>Reduce layout cycle time and rework through better automation, clearer handoffs, and smarter use of verification tools and AI-enabled workflows</li>\n<li>Strengthen cross-team collaboration so design, layout, ESD, and CAD work as one integrated execution engine, not siloed functions</li>\n<li>Build reusable layout methodologies and automation frameworks that scale across programs and geographies</li>\n<li>Elevate engineering capability through mentorship, technical leadership, and clear execution standards that make the team stronger over time</li>\n<li>Contribute to successful tapeouts of industry-leading SerDes IP that powers next-generation semiconductor products</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering, Electronics, or a related field</li>\n<li>12+ years experience in analog or custom layout for high-speed analog and mixed-signal designs</li>\n<li>Deep expertise in layout implementation and related methodology in advanced process nodes</li>\n<li>Proven track record working across design, layout, ESD, CAD, and program teams to deliver complex layouts on schedule</li>\n<li>Experience improving engineering productivity through automation, methodology enhancement, dashboards, or workflow optimization</li>\n<li>This role requires experience in leading teams, planning execution, mentoring engineers, owning delivery outcomes, technical leadership, deep problem-solving ability, and cross-team methodology influence; experience or strong interest in applying AI and automation to layout workflows is a plus</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_f8b32cd8-6e1","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/analog-mixed-signal-layout-manager/44408/95090864112?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["analog mixed-signal layout","SerDes analog layout","layout methodology","floorplanning","matching","shielding","ESD integration","physical verification","automation","scripting","dashboards","AI-assisted workflows","layout engineering","chip architecture","circuit design","verification","semiconductor products","advanced process nodes","layout implementation","methodology enhancement","workflow optimization"],"x-skills-preferred":[],"datePosted":"2026-05-14T23:03:24.294Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"analog mixed-signal layout, SerDes analog layout, layout methodology, floorplanning, matching, shielding, ESD integration, physical verification, automation, scripting, dashboards, AI-assisted workflows, layout engineering, chip architecture, circuit design, verification, semiconductor products, advanced process nodes, layout implementation, methodology enhancement, workflow optimization"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_1e6cf679-be9"},"title":"Staff R&D Software Engineer – RTL Restructuring & Transformation","description":"<p>You will join a dynamic R&amp;D team focused on advancing RTL analysis, restructuring, and optimization technologies within RTL Architect. This team enables early architectural exploration and QoR convergence, helping customers make informed design decisions and reduce downstream implementation risk.</p>\n<p>As a Staff R&amp;D Software Engineer, you will design and develop advanced RTL analysis, restructuring, and optimization technologies within RTL Architect. You will implement efficient algorithms and data structures to enhance quality of results (QoR) and performance of architectural exploration tools. You will collaborate with product teams to integrate new features and support customer-driven requirements.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Designing and developing advanced RTL analysis, restructuring, and optimization technologies within RTL Architect.</li>\n<li>Implementing efficient algorithms and data structures to enhance quality of results (QoR) and performance of architectural exploration tools.</li>\n<li>Collaborating with product teams to integrate new features and support customer-driven requirements.</li>\n<li>Utilizing AI productivity tools such as cursor and GitHub Copilot to accelerate development cycles and improve code quality.</li>\n<li>Conducting rigorous testing and validation of software modules to ensure reliability and scalability.</li>\n</ul>\n<p>You will work closely with cross-functional teams to achieve common goals and foster a collaborative and inclusive engineering environment that empowers team members to achieve their best.</p>\n<p>You will have the opportunity to work on challenging projects, apply analytical thinking to drive innovation, and leverage AI productivity tools to enhance your workflow. You will also have the chance to mentor and guide junior engineers, fostering a culture of innovation and technical excellence.</p>\n<p>The ideal candidate will have a strong proficiency in C/C++ and object-oriented design principles, with 4 to 10 years of experience in EDA Software development. You will have a solid understanding of data structures, graphs, and algorithms, as well as expertise in RTL design methodologies (Verilog, SystemVerilog, VHDL).</p>\n<p>You will be a self-driven individual with the ability to work independently and take initiative, a collaborative team player who enjoys mentoring others, and an excellent communicator who can convey technical concepts clearly.</p>\n<p>You will be adaptable and eager to learn new technologies and methodologies, committed to fostering an inclusive and innovative work environment, and passionate about delivering high-quality, high-performance solutions that make a tangible impact on end users.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_1e6cf679-be9","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/staff-r-and-d-software-engineer-rtl-restructuring-and-transformation/44408/93996748576?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["C/C++","object-oriented design principles","EDA Software development","RTL design methodologies","Verilog","SystemVerilog","VHDL"],"x-skills-preferred":["AI productivity tools","cursor","GitHub Copilot","data structures","graphs","algorithms"],"datePosted":"2026-04-24T14:09:49.496Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"C/C++, object-oriented design principles, EDA Software development, RTL design methodologies, Verilog, SystemVerilog, VHDL, AI productivity tools, cursor, GitHub Copilot, data structures, graphs, algorithms"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_de112d07-e65"},"title":"Analog Design, Principal Engineer","description":"<p><strong>Overview</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>15231</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>02/15/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<ul>\n<li>An experienced and passionate Analog and Mixed-Signal (A&amp;MS) Senior Circuit Design Expert with a strong background in PLL , data converters and SERDES design.</li>\n</ul>\n<ul>\n<li>You have a deep understanding of mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction.</li>\n</ul>\n<ul>\n<li>Your expertise includes circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive network and interconnect parasitic impact in advanced finfet technology nodes.</li>\n</ul>\n<ul>\n<li>You excel in developing Analog Full custom circuit macros, such as PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP, in both planar and fin-fet CMOS technology.</li>\n</ul>\n<ul>\n<li>You thrive in collaborative environments, working closely with silicon test and debug experts to advance quality through Sim2Sil correlation.</li>\n</ul>\n<ul>\n<li>You are also passionate about building and nurturing key analog design talent to grow business impact through successful project execution.</li>\n</ul>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Leading NRZ/PAM4 Serdes analog design transceiver solutions.</li>\n</ul>\n<ul>\n<li>Developing Analog Full custom circuit macros for High Speed PHY IP in advanced technology nodes.</li>\n</ul>\n<ul>\n<li>Collaborating with silicon test and debug experts for Sim2Sil correlation.</li>\n</ul>\n<ul>\n<li>Analyzing various mixed signal techniques for power reduction, performance enhancement, and area reduction.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Driving innovation in mixed-signal advanced analog serdes design.</li>\n</ul>\n<ul>\n<li>Enhancing the performance and efficiency of high-speed physical interfaces.</li>\n</ul>\n<ul>\n<li>Contributing to the development of cutting-edge technology in High Speed PHY IP.</li>\n</ul>\n<ul>\n<li>Improving quality and robustness of design through collaboration and Sim2Sil correlation.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>BE 15+ years of relevant experience or MTech 12+ years of relevant experience in mixed signal analog, clock, and datapath circuit design.</li>\n</ul>\n<ul>\n<li>Experience in designing Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits.</li>\n</ul>\n<ul>\n<li>Knowledge in Equalizers , CDR architectures , high-speed digital circuit design , timing/phase noise analysis, signal integrity .</li>\n</ul>\n<ul>\n<li>Knowledge of RF architecture and blocks such as transceivers front-end , VCOs, LNA, and up/down converters</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Strong fundamentals of CMOS, device physics, and sub-micron design methodologies.</li>\n</ul>\n<ul>\n<li>Experience with PLL designs and high-speed digital circuit design.</li>\n</ul>\n<ul>\n<li>Knowledge of control systems, band gaps, bias, op-amps, LDOs, and feedback techniques.</li>\n</ul>\n<ul>\n<li>Familiarity with digitally assisted analog circuit techniques.</li>\n</ul>\n<ul>\n<li>Capable to drive technical decision and tradeoff with customer focus</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>Join our High-Performance Computing (HPC) Enterprise analog/mixed-signal Serdes team involved in cutting-edge High Speed PHYSICAL Interface Development.</p>\n<p>You will work with experienced teams locally and with colleagues from various sites across the globe, fostering a collaborative and innovative environment.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p><strong>Get an idea of what your daily routine <strong>around the office</strong> can be like</strong></p>\n<p>\\ Explore <strong>Noida</strong></p>\n<p>View Map</p>\n<p>---</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_de112d07-e65","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/analog-design-principal-engineer/44408/91802916768?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert","PLL , data converters and SERDES design","mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction","circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive network and interconnect parasitic impact in advanced finfet technology nodes","Analog Full custom circuit macros, such as PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP, in both planar and fin-fet CMOS technology","silicon test and debug experts to advance quality through Sim2Sil correlation","Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits","Equalizers , CDR architectures , high-speed digital circuit design , timing/phase noise analysis, signal integrity ","RF architecture and blocks such as transceivers front-end , VCOs, LNA, and up/down converters"],"x-skills-preferred":[],"datePosted":"2026-03-09T11:06:28.077Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert, PLL , data converters and SERDES design, mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction, circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive network and interconnect parasitic impact in advanced finfet technology nodes, Analog Full custom circuit macros, such as PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP, in both planar and fin-fet CMOS technology, silicon test and debug experts to advance quality through Sim2Sil correlation, Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits, Equalizers , CDR architectures , high-speed digital circuit design , timing/phase noise analysis, signal integrity , RF architecture and blocks such as transceivers front-end , VCOs, LNA, and up/down converters"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_f66286eb-f5d"},"title":"Principal ASIC Design Engineer","description":"<p>We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. 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