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YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_87fc24a8-9b1"},"title":"Validation / Verification Eng, Staff Engineer","description":"<p>We are seeking a Validation / Verification Eng, Staff Engineer at Synopsys.</p>\n<p>You have built a career designing and validating hardware systems that must perform reliably in production environments. Your experience has taught you that schematic correctness is only the beginning; layout decisions determine whether signal integrity holds under real operating conditions.</p>\n<p>At Synopsys, you will validate memory interface IP where timing margins are measured in picoseconds and your board-level engineering directly determines product quality and customer success.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Design, layout, and validate printed circuit boards in Cadence Allegro for memory interface IP characterization and customer reference implementations</li>\n<li>Perform signal integrity analysis using S-parameters, eye diagrams, and crosstalk simulations to verify performance across multi-gigabit interfaces</li>\n<li>Debug hardware systems using logic analyzers, oscilloscopes, and protocol analyzers to isolate root causes across silicon, firmware, layout, and test configurations</li>\n<li>Conduct design reviews with cross-functional teams to establish best practices for routing, power distribution, and design constraint compliance</li>\n<li>Execute root cause analysis on validation failures to determine whether issues originate from silicon behavior, board design, or environmental conditions</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Your board designs will provide the validation infrastructure for Synopsys memory IP deployed in automotive, mobile, and data center customer applications</li>\n<li>Your signal integrity analysis will inform design guidelines that reduce customer design iterations and accelerate time to market</li>\n<li>Your validation findings will provide critical feedback to silicon design teams, ensuring alignment between simulated and measured performance</li>\n<li>Your technical reviews will establish quality standards for layout evaluation and early detection of design issues</li>\n<li>Your diagnostic capabilities will reduce bring-up cycle times and expedite IP delivery to customers</li>\n<li>Your reference designs will serve as integration templates for customers implementing Synopsys IP in production systems</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering, Electronics Engineering, or equivalent professional experience</li>\n<li>6-8+ years of hardware design and validation experience focused on high-speed digital and mixed-signal systems</li>\n<li>Expert-level proficiency in Cadence Allegro for schematic capture, PCB layout, and constraint-driven design</li>\n<li>Comprehensive understanding of signal integrity principles including S-parameters, impedance control, crosstalk, intersymbol interference, and return loss</li>\n<li>Demonstrated experience debugging hardware using logic analyzers, oscilloscopes, vector network analyzers, spectrum analyzers, and protocol analyzers</li>\n<li>Working knowledge of communication interfaces including JTAG, I2C, SPI, and UART, with understanding of routing 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>As a Principal Firmware Engineer at Synopsys, you will develop and optimize firmware for DDR, LPDDR, and HBM memory interface PHY training sequences. Your expertise in firmware development, hardware debugging, and memory interface behavior will enable you to profile compiled firmware at the instruction level, analyze RTL waveforms, and collaborate with firmware architecture to study JEDEC protocol specifications.</p>\n<p>Your responsibilities will include:</p>\n<ul>\n<li>Developing and optimizing firmware for DDR, LPDDR, and HBM memory interface PHY training sequences</li>\n<li>Profiling compiled firmware at the instruction level to identify runtime bottlenecks and implement optimizations that improve training performance</li>\n<li>Analyzing RTL waveforms and testchip data in the hardware lab to understand eye margin sensitivity and refine training algorithms</li>\n<li>Collaborating with firmware architecture to study JEDEC protocol specifications and propose algorithmic improvements to training workflows</li>\n<li>Debugging complex hardware-software interaction issues across firmware, RTL, and physical silicon using lab equipment and simulation tools</li>\n<li>Exploring and prototyping how emerging modeling techniques could be applied to memory training workflows</li>\n<li>Mentoring engineers on the team, sharing your knowledge of embedded firmware development, hardware debugging, and memory interface behavior</li>\n</ul>\n<p>The impact you will have includes:</p>\n<ul>\n<li>Reducing training runtime for next-generation memory PHYs, directly improving customer time-to-market and system boot performance</li>\n<li>Improving training robustness and eye margin across process, voltage, and temperature corners, resulting in higher yield and reliability for customer designs</li>\n<li>Influencing the architecture of future PHY training algorithms by bringing fresh perspectives grounded in real hardware behavior</li>\n<li>Accelerating team capability by mentoring engineers on low-level firmware optimization, RTL debugging, and protocol-level problem solving</li>\n<li>Enabling Synopsys to deliver competitive, high-performance memory IP solutions that meet the demands of AI, HPC, and data center applications</li>\n<li>Shaping the direction of firmware development practices and tooling within the IP Group through your technical leadership</li>\n<li>Contributing to the successful deployment of memory PHY IP used by leading semiconductor companies worldwide</li>\n</ul>\n<p>To be successful in this role, you will need:</p>\n<ul>\n<li>A Bachelor&#39;s degree in Engineering, Computer Science, or a related field with 12+ years of software development experience, Master&#39;s with 10+ years, or PhD with 8+ years, all in commercial or production environments</li>\n<li>Deep proficiency in C for embedded firmware development, including experience optimizing for resource-constrained processors</li>\n<li>Hands-on experience with RTL waveform analysis and debugging using tools like Verdi, DVE, or similar</li>\n<li>Demonstrated ability to work at the hardware-software boundary, understanding how firmware interacts with digital logic and physical interfaces</li>\n<li>Experience profiling and optimizing compiled code for performance-critical applications</li>\n<li>Strong debugging skills across firmware, RTL simulation, and hardware lab environments</li>\n<li>Experience with Python and Verilog is a strong plus, particularly for test automation and RTL co-development</li>\n</ul>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2c5170e2-875","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/nepean/principal-firmware-engineer/44408/102054577824?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$146000-$219000","x-skills-required":["C","embedded firmware development","RTL waveform analysis","debugging","Python","Verilog"],"x-skills-preferred":[],"datePosted":"2026-10-17T09:18:38.217Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Nepean, Ontario"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"C, embedded firmware development, RTL waveform analysis, debugging, Python, Verilog","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":146000,"maxValue":219000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_34deaf24-967"},"title":"Sr Staff Package Design Engineer","description":"<p>Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing.</p>\n<p>As a Sr Staff Package Design Engineer at Synopsys, you will lead package design for advanced IP test chips at the forefront of performance. Working with tools such as Ansys HFSS and collaborating across engineering teams, you&#39;ll help shape the technologies that enable the next generation of semiconductor products.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Lead four to six test-chip package designs per year from requirements definition through final delivery, coordinating across internal teams, customers, and external partners</li>\n<li>Define package requirements early in the design cycle, including bump maps, ball maps, and layer stack-up decisions that optimize signal integrity and power integrity performance</li>\n<li>Perform hands-on physical design and layout of advanced package substrates using industry-standard EDA tools</li>\n<li>Extract electrical models from substrate designs using 3D EM simulation tools like Ansys HFSS, and analyze them against SI and PI requirements to validate performance</li>\n<li>Guide customers through package architecture evaluations and tradeoff analysis to identify implementation options that work for Synopsys IP</li>\n<li>Resolve complex package design and integration issues by developing technically sound solutions that balance electrical performance, manufacturability, and cost</li>\n<li>Provide regular project updates to management covering progress, technical risks, dependencies, mitigation plans, and decisions that need escalation</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Enable successful tape-outs of Synopsys IP test-chips by ensuring package designs meet electrical and physical performance requirements from day one</li>\n<li>Reduce design iteration cycles and avoid costly respins by catching signal integrity and power integrity issues early through rigorous modeling and analysis</li>\n<li>Expand the range of package solutions available to Synopsys customers by evaluating new architectures and proving out their viability for high-performance IP</li>\n<li>Strengthen customer relationships by providing expert guidance on package design decisions that directly affect their product success</li>\n<li>Improve design quality and efficiency across the team by establishing best practices for substrate layout, model extraction, and SI/PI validation</li>\n<li>Accelerate time-to-market for Synopsys IP by coordinating design phases, technical reviews, and handoffs that keep projects moving without surprises</li>\n<li>Influence cross-functional business-unit projects by representing the package design perspective in technical decisions that affect multiple teams</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>10+ years of hands-on experience in semiconductor package design, package substrate layout, electrical modeling, or closely related work</li>\n<li>Advanced knowledge of circuit theory and transmission line behavior, with the ability to apply it to high-speed package interconnect design and analysis</li>\n<li>Demonstrated experience building, validating, and interpreting 3D electromagnetic models using Ansys HFSS or comparable simulation tools</li>\n<li>Strong written and verbal communication skills in English, with the ability to explain complex technical tradeoffs to customers, partners, and cross-functional teams</li>\n<li>Working knowledge of Windows and Linux environments used for engineering design and analysis workflows</li>\n<li>Bachelor&#39;s degree in electrical engineering, electronics engineering, or equivalent field</li>\n<li>Experience with advanced packaging technologies such as 2.5D interposers, fan-out wafer-level packaging, or chiplet integration is a plus</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family</li>\n<li>Time away: company holidays, ETO and FTO Programs</li>\n<li>Family support: maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back</li>\n<li>Retirement plans: save for your future with our retirement plans that vary by region and country</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_34deaf24-967","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/nepean/sr-staff-package-design-engineer/44408/101580799600?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"employee","x-salary-range":"$119000-$178000","x-skills-required":["Ansys HFSS","circuit theory","transmission line behavior","electromagnetic models","Windows","Linux","electrical engineering"],"x-skills-preferred":["advanced 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You have spent years turning design files into real boards that work, not just pass DRC, actually work when you power them up and start probing signals. You know that a clean schematic means nothing if the layout introduces crosstalk that kills your eye diagram.</p>\n<p>At Synopsys, you will validate memory interface IP where the margin between working silicon and a customer escalation is measured in picoseconds, and your board-level work is what closes that gap.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Design, layout, and validate PCBs in Cadence Allegro for memory interface IP characterization and customer reference designs</li>\n<li>Analyze high-speed signal behavior using S-parameters, eye diagrams, and crosstalk simulations to ensure signal integrity across multi-gigabit interfaces</li>\n<li>Route and validate communication interfaces including JTAG, I2C, and other low-speed control planes with attention to noise immunity and timing margins</li>\n<li>Debug board-level issues using logic analyzers, oscilloscopes, and protocol analyzers to isolate failures across silicon, firmware, layout, and test setup</li>\n<li>Review design files and layout with cross-functional teams, teaching best practices for routing, decoupling, and design rule adherence</li>\n<li>Interpret simulation waveforms from SPICE, IBIS, and channel analysis tools to validate analog and mixed-signal circuit performance</li>\n<li>Drive root cause analysis on validation failures, determining whether issues stem from silicon behavior, board design, or environmental factors</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Your board designs will serve as the validation platform for Synopsys memory IP used in customer production deployments across automotive, mobile, and data center applications</li>\n<li>The signal integrity work you do will directly inform design guidelines that prevent customer respins and reduce time to market</li>\n<li>Your debug findings will feed back into silicon design teams, closing the loop between simulated and measured performance</li>\n<li>The review practices you establish will raise the quality bar for how the team evaluates layout and catches issues before boards are fabricated</li>\n<li>Your ability to isolate failures quickly will accelerate bring-up schedules and get IP into customer hands faster</li>\n<li>The reference designs you validate will become the foundation for how customers integrate Synopsys IP into their own systems</li>\n<li>Your mentorship will build the next generation of validation engineers who understand the full stack from transistor to trace</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s in Electrical Engineering, Electronics Engineering, or equivalent hands-on experience</li>\n<li>6-8+ years of Hardware design and validation experience with a focus on high-speed digital and mixed-signal systems</li>\n<li>Expert-level proficiency in Cadence Allegro for schematic capture, PCB layout, and constraint-driven design</li>\n<li>Deep understanding of signal integrity concepts including S-parameters, impedance control, crosstalk, intersymbol interference, and return loss</li>\n<li>Strong knowledge of analog IC circuit design and the ability to analyze SPICE simulation waveforms and correlate them to measured behavior</li>\n<li>Hands-on experience debugging hardware using logic analyzers, oscilloscopes, VNAs, spectrum analyzers, protocol analyzers, and other bench instrumentation</li>\n<li>Experience with communication interfaces such as JTAG, I2C, SPI, and UART, including routing best practices and protocol-level debug</li>\n<li>Knowledge of PCB stack-up design and high-speed materials.</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family</li>\n<li>In addition to company holidays, we have ETO and FTO Programs</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back</li>\n<li>Save for your future with our retirement plans that vary by region and country</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cff087c6-adf","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/nepean/hardware-validation-engineer-sr-staff/44408/101403651232?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$120000-$180000","x-skills-required":["Cadence Allegro","signal integrity","PCB design","high-speed digital systems","mixed-signal systems","SPICE","IBIS","channel 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As a leader in engineering solutions from silicon to systems, Synopsys enables customers to rapidly innovate AI-powered products.</p>\n<p>The successful candidate will have experience in bringing silicon to life, and be comfortable in the lab with an oscilloscope in one hand and a Python script in the other. The role involves working on the first-silicon bring-up and validation for DDR6, DDR5, LPDDR6/X, LPDDR5/5X, MRDIMM, and HBM test chips and evaluation platforms.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Developing and executing validation plans covering functionality, parametric characterization, margin analysis, and reliability testing</li>\n<li>Performing electrical characterization including eye diagram analysis, jitter measurements, and signal integrity metrics</li>\n<li>Driving systematic debug and root cause analysis of silicon, firmware, board, and test infrastructure issues</li>\n<li>Building automated validation frameworks and reusable test infrastructure using Python, C/C++, and scripting tools</li>\n<li>Participating in the development of multilayer PCB designs for silicon characterization platforms</li>\n<li>Generating characterization reports and presenting silicon performance data to stakeholders and customers</li>\n</ul>\n<p>The ideal candidate will have:</p>\n<ul>\n<li>A Bachelor&#39;s or Master&#39;s degree in Electrical Engineering, Computer Engineering, Engineering Physics, or related discipline</li>\n<li>3+ years of semiconductor industry experience in silicon validation, characterization, test, or product engineering</li>\n<li>Strong understanding of DDR/LPDDR/HBM protocols, high-speed interfaces, and digital and mixed-signal semiconductor design concepts</li>\n<li>Hands-on experience with lab instrumentation including oscilloscopes, logic analyzers, and Automated Test Equipment (ATE)</li>\n<li>Experience with scripting languages such as Python, MATLAB, and C/C++</li>\n</ul>\n<p>In return, we offer a comprehensive range of health, wellness, and financial benefits, including a base salary range of $93,000 - $139,000.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a 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Ontario"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Python, C/C++, DDR/LPDDR/HBM protocols, high-speed interfaces, digital and mixed-signal semiconductor design concepts, lab instrumentation, scripting languages","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":93000,"maxValue":139000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_321104b8-077"},"title":"Validation / Verification Eng, Manager","description":"<p>We are seeking a Validation / Verification Eng, Manager to lead a lab team validating memory IP that ships in products worldwide.</p>\n<p>You will lead first silicon bring-up and validation for DDR6, DDR5, LPDDR6/X, LPDDR5/5X, MRDIMM, and HBM test chips.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Lead first silicon bring-up and validation for various memory interfaces</li>\n<li>Perform electrical characterization including eye diagrams, jitter measurements, timing margins, and signal integrity analysis</li>\n<li>Drive debug and root cause analysis of silicon, firmware, and board issues using lab instrumentation and cross-functional collaboration</li>\n<li>Build automated validation frameworks using Python and C/C++ to improve test efficiency and data collection</li>\n<li>Lead multilayer PCB design for characterization platforms and customer evaluation kits</li>\n<li>Manage team hiring, staffing, resource allocation, morale and audit preparation while growing technical capability</li>\n<li>Work alongside cross-functional teams to weigh business impacts and make critical decisions</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Ensure Synopsys memory interface IP products meet performance and reliability standards before customer deployment</li>\n<li>Implement efficiency improvements and process changes to a team of 20+ staff across 3+ labs</li>\n<li>Reduce time to market by building reusable test infrastructure that accelerates validation across IP generations</li>\n<li>Provide silicon-proven characterization data that gives customers confidence to integrate Synopsys IP</li>\n<li>Identify and resolve issues early, preventing costly re-spins and customer escalations</li>\n<li>Grow a high-performing validation team in Nepean that becomes a center of excellence for memory IP</li>\n<li>Influence design decisions by feeding back real-world silicon behavior to architecture teams</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Bachelor&#39;s degree in Electrical Engineering or equivalent technical field</li>\n<li>8+ years of hands-on silicon validation experience with memory interfaces such as DDR, LPDDR, or HBM</li>\n<li>3+ years managing engineering teams, including hiring and resource allocation</li>\n<li>Deep understanding of JEDEC specifications, jitter analysis, timing margins, and electrical characterization</li>\n<li>Proficiency in Python and C for test automation and hardware validation scripting</li>\n<li>Experience with ATE testers such as Teradyne, LTX/Credence, Advantest</li>\n<li>Board design experience including multilayer PCB development, experience with automotive qualification standards or reliability testing is a plus</li>\n<li>Experience in scheduling, event planning with vendors of all sorts</li>\n</ul>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a 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including DDR, LPDDR, and HBM</li>\n<li>Perform electrical characterisation using oscilloscopes, BERTs, and network analysers to capture time-domain signals, eye diagrams, and jitter analysis on production silicon</li>\n<li>Debug complex mixed-signal systems including PLLs, DLLs, DACs, and state machines to isolate failures across silicon, firmware, board, and test setup</li>\n<li>Validate IP against JEDEC specifications and automotive qualification standards including HTOL, ELFR, and reliability testing protocols</li>\n<li>Generate technical documentation and validation reports that translate silicon behaviour into actionable recommendations for design, firmware, and customer teams</li>\n<li>Collaborate with design and firmware teams during silicon bring-up to identify and resolve issues before production release</li>\n<li>Mentor junior validation engineers through characterisation projects, test program development, and lab equipment usage</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Your validation work will determine whether Synopsys memory IP meets timing, signal integrity, and reliability requirements before customer deployment</li>\n<li>You will catch silicon issues early in the validation cycle, reducing costly re-spins and accelerating time to market for new IP releases</li>\n<li>Your ATE programs will become the production test foundation for high-volume manufacturing, directly affecting yield and quality</li>\n<li>Your characterisation data will inform design decisions for next-generation memory interface IP</li>\n<li>Your mentorship will build validation capability in the Nepean lab, enabling the team to scale alongside the IP portfolio</li>\n<li>Your documentation will serve as the technical record that supports customer engagements, qualification processes, and internal design reviews</li>\n<li>Your ability to isolate root cause across disciplines will prevent validation bottlenecks and keep silicon programs on schedule</li>\n</ul>\n<p><strong>Requirements:</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering or equivalent technical field</li>\n<li>8+ years of hands-on experience in silicon validation, ATE programming, or mixed-signal test engineering</li>\n<li>Proven experience programming ATE platforms such as Teradyne, LTX, Advantest, Credence, or Introspect</li>\n<li>Proven experience debugging and bringing up new benchtop test equipment for IO characterisation</li>\n<li>Deep working knowledge of DDR, LPDDR, and HBM protocols and JEDEC specifications</li>\n<li>Strong analog and mixed-signal circuit knowledge with the ability to analyse verification and simulation waveforms</li>\n<li>Expertise using oscilloscopes, BERTs, network analysers, and other advanced lab equipment for electrical characterisation</li>\n<li>Expertise in reading VB code</li>\n<li>Experience with jitter analysis, timing validation, pulse-width measurements, and reliability testing including HTOL and ELFR is a strong plus</li>\n<li>Familiarity with automotive qualification standards is a strong plus</li>\n</ul>\n<p><strong>Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_4b5520bb-fbd","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/nepean/ate-test-engineer-sr-staff-engineer-18756/44408/101150985024?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$110000-$164000","x-skills-required":["ATE programming","mixed-signal test engineering","silicon validation","DDR","LPDDR","HBM","JEDEC specifications","oscilloscopes","BERTs","network analysers"],"x-skills-preferred":["jitter analysis","timing validation","pulse-width measurements","reliability testing","automotive qualification standards"],"datePosted":"2026-09-27T01:03:00.966Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Nepean, Ontario"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ATE programming, mixed-signal test engineering, silicon validation, DDR, LPDDR, HBM, JEDEC specifications, oscilloscopes, BERTs, network analysers, jitter analysis, timing validation, pulse-width measurements, reliability testing, automotive qualification standards","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":110000,"maxValue":164000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_96faca4e-f2c"},"title":"Firmware Engineering Manager","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. 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You will spend up to 20% of your time working directly with global customers to clarify requirements, resolve technical issues.</p>\n<p>Your responsibilities will include:</p>\n<ul>\n<li>Leading a team of firmware engineers</li>\n<li>Managing project lifecycles</li>\n<li>Coaching and developing engineers</li>\n<li>Driving engineering standards</li>\n<li>Debugging and resolving issues</li>\n<li>Representing the team in technical reviews</li>\n</ul>\n<p>The impact you will have:</p>\n<ul>\n<li>Enabling your team to deliver memory interface solutions that meet aggressive performance and quality targets</li>\n<li>Accelerating customer development cycles</li>\n<li>Raising the technical capability of the group</li>\n<li>Shortening project timelines</li>\n<li>Strengthening Synopsys&#39; reputation for technical excellence</li>\n</ul>\n<p>To be successful in this role, you will need:</p>\n<ul>\n<li>BSc, MS or PhD in Computer Science, Electronics Engineering, or a related field</li>\n<li>Proven experience as a Tech Lead or Engineering Manager leading embedded firmware or silicon IP development teams</li>\n<li>Strong proficiency in C for embedded firmware applications</li>\n<li>Hands-on experience with RTL waveform analysis and debugging</li>\n<li>Demonstrated ability to mentor and grow engineers</li>\n<li>Strong communication skills</li>\n</ul>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_96faca4e-f2c","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/nepean/firmware-engineering-manager/44408/100945624976?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$146000-$219000","x-skills-required":["C","embedded firmware","RTL waveform analysis","debugging","leadership","communication"],"x-skills-preferred":[],"datePosted":"2026-09-21T21:05:47.339Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Nepean, Ontario"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"C, embedded firmware, RTL waveform analysis, debugging, leadership, communication","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":146000,"maxValue":219000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_7295b450-03f"},"title":"Principal Digital Verification Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You have spent years building verification environments for complex digital designs where mistakes show up as silicon respins or customer escalations. The difference between a PHY that passes regression and one that works in production is something you understand deeply, and it shapes how you write testplans, model coverage, and design infrastructure.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Develop comprehensive testplans and functional coverage models for training firmware running on RTL models of memory PHYs</li>\n<li>Build and maintain testbench infrastructure in SystemVerilog and UVM that supports complex verification scenarios across multiple product generations</li>\n<li>Create test cases that cover success paths, corner cases, and negative scenarios based on standard specifications and feature enhancements</li>\n<li>Debug complex issues across firmware, RTL, and testbench layers using simulation and waveform analysis tools</li>\n<li>Participate in technical reviews with architecture and implementation teams to influence design decisions from a verification perspective</li>\n<li>Research and evaluate emerging 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adopt will directly improve team productivity and reduce verification time</li>\n<li>Engineers you mentor will carry forward the verification rigor and problem-solving approach that makes complex IP actually work</li>\n<li>Your work with customers (on simulation debug or post-silicon bring-up debug) will strengthen their confidence in our IP and inform future product roadmaps</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>BSc in Electrical Engineering, Computer Engineering, or related field with 12+ years of verification experience, MSc with 10+ years, or PhD with 8+ years</li>\n<li>Deep proficiency in SystemVerilog and UVM, with a track record of building reusable testbench components and verification environments</li>\n<li>Strong command of simulation tools, waveform debuggers, and the ability to trace issues across multiple abstraction layers</li>\n<li>Solid understanding of C and experience with software/hardware co-simulation</li>\n<li>Experience with assertion-based verification, coverage analysis, and protocol-oriented performance debug</li>\n<li>Comfort working in Linux environments with scripting for regression systems, build automation, and source control workflows</li>\n<li>Experience with virtual prototyping or emulation platforms is a strong plus, as is knowledge of LPDDR5/5X and LPDDR6 or other memory interface standards</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family</li>\n<li>In addition to company holidays, we have ETO and FTO Programs</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back</li>\n<li>Save for your future with our retirement plans that vary by region and country</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7295b450-03f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/nepean/principal-digital-verification-engineer/44408/100812692208?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$146000-$219000","x-skills-required":["SystemVerilog","UVM","simulation tools","waveform debuggers","C","assertion-based verification","coverage analysis","protocol-oriented performance debug","Linux","scripting","regression systems","build automation","source control workflows"],"x-skills-preferred":["virtual prototyping","emulation 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As a Sr Staff Engineer in ASIC Physical Design, you will contribute to the development of advanced semiconductor solutions, collaborating with cross-functional teams to design, verify, and manufacture complex SoCs and test chips. Your expertise in the physical design flow and familiarity with industry-leading tools will enable you to drive technical execution and lead complex projects.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Contributing to physical design implementation for test chips across DDR/HBM/UCIe protocols, from RTL to final GDS release to foundry.</li>\n<li>Developing overall floorplan and power/ground strategies tailored for diverse test chip architectures.</li>\n<li>Owning and optimizing the RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.</li>\n<li>Executing and overseeing static timing analysis (STA) and physical verification (EM/IR drop, ERC/DRC/LVS, PERC/ESD analysis).</li>\n<li>Integrating updated covercells, circuit/IP/PLL/hard-macros, and coordinating abutment checking and QA/release of hard-macros.</li>\n<li>Driving tool flow automation and debugging to enhance productivity and design reliability.</li>\n<li>Collaborating closely with architecture, RTL, circuit, and covercell teams throughout test chip development.</li>\n</ul>\n<p>Impact:</p>\n<ul>\n<li>Enable robust validation of Synopsys&#39;s IP blocks for PHYs, ensuring high-quality deliverables prior to customer release or SoC integration.</li>\n<li>Accelerate time-to-market by driving rapid turnaround from RTL to silicon, reducing schedule risks and helping Synopsys meet critical market windows.</li>\n<li>Enhance product reliability and manufacturability through rigorous timing closure, power/thermal analysis, and comprehensive verification signoff.</li>\n<li>Bolster Synopsys&#39;s reputation by delivering high-quality, silicon-proven IP that meets real-world performance and reliability standards.</li>\n<li>Foster seamless cross-functional collaboration, bridging architects, RTL designers, verification teams, and silicon validation groups.</li>\n<li>Champion continuous process and tool improvement, implementing flow automation to keep Synopsys at the forefront of EDA innovation.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>9+ years of experience in ASIC physical design, with a proven track record in complex SoC or test chip implementations at advanced process nodes.</li>\n<li>Deep expertise in the complete ASIC physical design flow: floor planning, synthesis, P&amp;R, timing closure, IR-drop/EM analysis, LVS/DRC, etc.</li>\n<li>Familiarity with IP integration, test chip methodology, and advanced verification flows.</li>\n<li>Proficiency with state-of-the-art CAD tools such as Design Compiler (DC), PrimeTime (PT), IC Compiler II/FC, ICV, Calibre, RedHawk, and FinFet technologies.</li>\n<li>Experience coordinating complex, cross-functional projects and leading technical execution.</li>\n<li>Authorization to work in the USA.</li>\n</ul>\n<p>Team:</p>\n<p>You&#39;ll join the Test Chip PHY development team within Synopsys&#39;s Silicon IP business. This group is dedicated to integrating and validating Synopsys&#39;s broad portfolio of IP blocks,logic, memory, interfaces, analog, security, and embedded processors,into test chips at the forefront of semiconductor innovation. The team works collaboratively across architecture, RTL, circuit, and covercell disciplines to deliver robust, silicon-proven IP solutions that power next-generation products for global customers.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_642c88a4-a92","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/nepean/asic-physical-design-sr-staff-engineer-16724/44408/93743819072?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","RTL-to-GDSII flow","Static timing analysis","Physical verification","Design Compiler","PrimeTime","IC Compiler II/FC","Calibre","RedHawk","FinFet technologies"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:12:52.721Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Nepean"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, RTL-to-GDSII flow, Static timing analysis, Physical verification, Design Compiler, PrimeTime, IC Compiler II/FC, Calibre, RedHawk, FinFet technologies"}]}