{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/city/moreira"},"x-facet":{"type":"city","slug":"moreira","display":"Moreira","count":8},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_fb5e96bd-f2d"},"title":"Senior FPGA Engineer","description":"<p>Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing.</p>\n<p>As a Senior FPGA Engineer at Synopsys, you will contribute to FPGA solutions that enable advanced semiconductor development workflows. You bring extensive experience designing FPGA solutions that meet rigorous performance and reliability standards in production environments.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Prototype and optimize high-performance PCIe-based designs on FPGA platforms using Vivado, driving the implementation flow through synthesis, place and route, timing closure, and hardware bring-up</li>\n<li>Simulate and verify PCIe-based prototype designs using industry-standard verification methodologies such as UVM, ensuring correct functionality and behavior prior to FPGA implementation and hardware bring-up</li>\n<li>Perform timing analysis and optimization across multiple clock domains, resolving setup and hold violations and ensuring designs meet performance targets</li>\n<li>Collaborate with hardware, software, and verification teams to define requirements, evaluate design tradeoffs, and deliver FPGA solutions that meet project goals</li>\n<li>Develop and execute test plans to validate functionality, performance, and reliability of FPGA prototypes in real-world conditions</li>\n<li>Participate in industry events, including PCI-SIG Compliance Workshops, to perform official compliance testing of PCIe prototypes and ensure conformance with applicable PCIe specifications and industry standards</li>\n<li>Debug and resolve hardware, protocol, and system-level issues identified during PCIe compliance testing, working across the FPGA prototype and test environment to achieve successful compliance results</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Enable faster product development cycles by delivering reliable, high-performance FPGA prototypes that allow hardware and software teams to validate complex PCIe designs ahead of silicon availability</li>\n<li>Identify integration, functional and implementation issues early through FPGA prototyping</li>\n<li>Strengthen Synopsys&#39; reputation for technical excellence by attending and getting certifications at industry compliance events</li>\n<li>Improve cross-team productivity by providing clear documentation, responsive support, and designs that integrate cleanly with adjacent systems</li>\n<li>Drive continuous improvement by bringing new techniques, tools, and standards into the team&#39;s design and verification processes</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s in Electrical Engineering, Computer Engineering, or equivalent hands-on experience</li>\n<li>Ideally 8+ years of FPGA design and development experience, with a strong track record of shipping working designs</li>\n<li>Deep proficiency in Verilog and RTL design, including experience with complex state machines, pipelines, and multi-clock domain architectures</li>\n<li>Strong command of Vivado or similar FPGA toolchains, including synthesis, implementation, and timing closure workflows</li>\n<li>Solid understanding of digital design fundamentals: clock domain crossings, metastability, timing constraints, and static timing analysis</li>\n<li>Experience with high-speed interfaces such as PCIe or Ethernet, including protocol-level understanding and debug</li>\n<li>Experience with scripting languages like Python or Tcl for automation and tooling is a plus</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family</li>\n<li>Time away: company holidays, ETO and FTO Programs</li>\n<li>Family support: maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back</li>\n<li>Retirement plans: save for your future with our retirement plans that vary by region and country</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_fb5e96bd-f2d","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/moreira/senior-fpga-engineer/44408/102251697552?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["FPGA design","Vivado","Verilog","RTL design","PCIe","UVM","Python","Tcl"],"x-skills-preferred":["scripting languages","high-speed interfaces","Ethernet"],"datePosted":"2026-10-22T11:27:59.999Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Moreira"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"FPGA design, Vivado, Verilog, RTL design, PCIe, UVM, Python, Tcl, scripting languages, high-speed interfaces, Ethernet"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_a22357d1-552"},"title":"Security Digital Design Engineer, Staff","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You are a passionate and skilled ASIC Digital Design Engineer with knowledge in RTL design and verification and focus on building hardware that must be both performant and secure. Your work in digital design has taught you that security cannot be an afterthought, it must be architected into the IP from the beginning. You understand the interplay between hardware design decisions and security implications, and you make design choices that account for both functional correctness and threat resilience.</p>\n<p><strong>What You&#39;ll Be Doing</strong></p>\n<ul>\n<li>Design and implement RTL in Verilog and SystemVerilog for Security IP cores, translating security requirements into synthesizable, verifiable hardware</li>\n<li>Build and maintain test environments for digital hardware Security IP using SystemVerilog and UVM, ensuring coverage of corner cases and attack scenarios</li>\n<li>Verify IP cores and subsystems using modern verification techniques including UVM testbenches and formal verification tools</li>\n<li>Collaborate with hardware and software security engineers to analyse functional correctness and performance of embedded IP solutions across threat models</li>\n<li>Contribute to detailed design specifications, verification plans, and documentation that support global development and customer integration</li>\n<li>Work within an international team across time zones, coordinating design reviews, debugging sessions, and milestone deliveries</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Strengthen the security posture of IP cores that protect critical systems in automotive, AI, and high-performance computing applications</li>\n<li>Enable faster SoC integration by delivering IP that meets strict performance, power, and area requirements without compromising security</li>\n<li>Reduce customer risk and time-to-market by ensuring IP is verified to the highest standards before it ships</li>\n<li>Driving innovation in the fields of CyberSecurity, High Performance Computing, Artificial Intelligence, and Automotive</li>\n<li>Advance the state of hardware security design within Synopsys, contributing techniques and methods that influence future IP development</li>\n<li>Support the growth of Synopsys Security IP in high-growth markets where trust and resilience are non-negotiable</li>\n<li>Help maintain Synopsys&#39; leadership position in delivering silicon IP that customers depend on for differentiation and compliance</li>\n</ul>\n<p><strong>What You&#39;ll Need</strong></p>\n<ul>\n<li>MSc or PhD in Electrical Engineering or Computer Science</li>\n<li>3+ years of strong working knowledge of RTL design for hardware IP components, with hands-on experience writing synthesizable SystemVerilog</li>\n<li>Ability to create detailed specifications for test environments</li>\n<li>Proficiency in ASIC verification using System Verilog, UVM, and or Verilog</li>\n<li>Strong understanding of IC Design flows and exceptional problem-solving and debugging skills</li>\n<li>Experience with hardware security concepts or cryptographic IP is a plus</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family</li>\n<li>In addition to company holidays, we have ETO and FTO Programs</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back</li>\n<li>Save for your future with our retirement plans that vary by region and country</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_a22357d1-552","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/moreira/security-digital-design-engineer-staff/44408/101317560656?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["RTL design","Verilog","SystemVerilog","ASIC verification","UVM","IC Design flows","problem-solving","debugging"],"x-skills-preferred":["hardware security concepts","cryptographic IP"],"datePosted":"2026-09-30T01:31:07.933Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Moreira"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design, Verilog, SystemVerilog, ASIC verification, UVM, IC Design flows, problem-solving, debugging, hardware security concepts, cryptographic IP"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e42d4606-17e"},"title":"Embedded Functional Safety Engineer","description":"<p>We are seeking an accomplished Functional Safety Engineer with extensive experience in embedded systems and a demonstrated track record of delivering ISO 26262-compliant products in safety-critical industries, particularly automotive.</p>\n<p>You will lead functional safety activities for embedded software and IP projects, ensuring full compliance with ISO 26262 requirements throughout the development lifecycle. You will develop comprehensive FuSa work products including safety plans, safety analyses (FMEA, FTA, FMEDA), safety requirement specifications, and safety cases that meet certification standards.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Conducting hazard analysis and risk assessments, defining safety goals and ASIL classifications, and systematically decomposing safety requirements from system level to software and hardware unit level</li>\n<li>Collaborating with R&amp;D teams across Controller, PHY, FPGA, and verification disciplines to integrate functional safety practices into design, implementation, and verification activities</li>\n<li>Coordinating safety reviews and assessments with internal stakeholders and external certification bodies, ensuring readiness for third-party evaluation</li>\n<li>Establishing and maintaining comprehensive traceability of safety requirements across all development artifacts using requirements management tools such as DOORS or Polarion</li>\n</ul>\n<p>The impact you will have:</p>\n<ul>\n<li>Enabling Synopsys embedded IP and software solutions to meet rigorous ISO 26262 standards, supporting customer success in automotive and safety-critical applications</li>\n<li>Delivering certification-ready functional safety documentation that reduces compliance risk and accelerates customer time-to-market</li>\n<li>Establishing systematic functional safety practices across R&amp;D organizations, strengthening the safety culture and engineering discipline</li>\n<li>Identifying and mitigating safety risks early in the development process, preventing costly downstream remediation and ensuring product integrity</li>\n<li>Enhancing Synopsys&#39; reputation as a trusted provider of automotive-grade IP through consistent delivery of safety-compliant products</li>\n<li>Supporting the advancement of safety-critical embedded systems that enable autonomous vehicles, industrial automation, and mission-critical infrastructure</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>BSc or MSc in Electrical Engineering, Computer Science, or related technical discipline</li>\n<li>Minimum 5 years of professional experience in functional safety engineering, embedded systems development, or safety-critical software in automotive or comparable industries</li>\n<li>Expert knowledge of ISO 26262 with demonstrated proficiency in parts 4 (system), 6 (software), and 8 (supporting processes)</li>\n<li>Proven track record developing functional safety work products that have successfully passed third-party assessment by certification bodies such as TÜV SÜD or TÜV Rheinland</li>\n<li>Strong technical foundation in embedded software development, including proficiency with C programming, RTOS implementations, and safety-relevant architecture patterns</li>\n<li>Professional certification as a Functional Safety Engineer from a recognized certification body is highly valued</li>\n</ul>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e42d4606-17e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/moreira/embedded-functional-safety-engineer/44408/101270640368?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ISO 26262","embedded systems","functional safety engineering","C programming","RTOS implementations"],"x-skills-preferred":["Professional certification as a Functional Safety Engineer"],"datePosted":"2026-09-29T01:14:33.836Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Moreira, Porto"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ISO 26262, embedded systems, functional safety engineering, C programming, RTOS implementations, Professional certification as a Functional Safety Engineer"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_07dace99-0f9"},"title":"UCIe Applications Engineering, Sr Staff","description":"<p>We currently have an opening for a highly motivated and experienced Applications Engineer with a passion for cutting-edge technology. As a UCIe Applications Engineering, Sr Staff at Synopsys, you will provide UCIe IP integration guidance to customers throughout their SoC flow and support silicon/system bring-up.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Understand IIP applications on customer-specific SoCs and systems.</li>\n<li>Keep abreast of the latest ASIC/SoC design flows and EDA tools.</li>\n<li>Provide expert guidance and support to configure and resolve IIP integration challenges including simulation, synthesis, floorplan, STA, DFT, silicon bring-up, and system integration.</li>\n<li>Lead customer integration reviews and major SoC milestones.</li>\n<li>Drive root-cause analysis and resolution of complex technical challenges.</li>\n<li>Partner with R&amp;D teams to produce application notes and improve deployment methodologies.</li>\n<li>Build trusted relationships with customer engineering teams and influence technical implementation decisions.</li>\n<li>Mentor junior applications engineers and contribute to technical knowledge sharing.</li>\n<li>Recommend product improvements based on customer deployment experiences.</li>\n<li>Participate in R&amp;D design reviews to align development with future customer needs.</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Drive successful integration and deployment of Synopsys UCIe IP across complex customer ASIC and SoC programs.</li>\n<li>Build trusted relationships with customer engineering teams through technical leadership and consistent execution.</li>\n<li>Serve as a trusted technical partner helping customers successfully deploy Synopsys UCIe solutions.</li>\n<li>Accelerate resolution of complex integration challenges by effectively coordinating with customers and R&amp;D teams.</li>\n<li>Improve deployment success through technical reviews, best practices, and methodology guidance.</li>\n<li>Influence product quality and usability through actionable customer feedback.</li>\n<li>Strengthen the Applications Engineering organization through mentoring and technical leadership.</li>\n<li>Contribute to long-term customer success as a trusted technical advisor.</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>Bachelor&#39;s and/or Master&#39;s degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields.</li>\n<li>Typically requires at least 8 years of design, verification, implementation, validation, or applications engineering experience.</li>\n<li>Hands-on experience with ASIC Front-End or Back-End development.</li>\n<li>Demonstrated ability to independently lead customer technical discussions and engagements.</li>\n<li>Strong analytical, reasoning, and problem-solving skills.</li>\n<li>Proven verbal and written communication skills.</li>\n</ul>\n<p><strong>Preferred Experience</strong></p>\n<ul>\n<li>Experience with advanced technology processes (10nm/7nm/5nm/3nm), mixed-signal IP, or circuit design.</li>\n<li>Domain knowledge in Die-to-Die and PCIe/CXL protocols.</li>\n<li>Silicon and/or FPGA/hardware debug and troubleshooting skills.</li>\n<li>Knowledge of advanced EDA tool products and expertise in P&amp;R, Physical Verification, Signal Integrity, or Power Integrity.</li>\n</ul>\n<p><strong>Benefits</strong> We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_07dace99-0f9","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/moreira/ucie-applications-engineering-sr-staff/44408/101288479264?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC Front-End","Back-End development","EDA tools","Electrical Engineering","Computer Engineering","Computer Science"],"x-skills-preferred":["advanced technology processes","mixed-signal IP","circuit design","Die-to-Die protocols","PCIe/CXL protocols","FPGA/hardware debug","troubleshooting skills","P&R","Physical Verification","Signal Integrity","Power Integrity"],"datePosted":"2026-09-29T01:04:55.158Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Moreira, Porto"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC Front-End, Back-End development, EDA tools, Electrical Engineering, Computer Engineering, Computer Science, advanced technology processes, mixed-signal IP, circuit design, Die-to-Die protocols, PCIe/CXL protocols, FPGA/hardware debug, troubleshooting skills, P&R, Physical Verification, Signal Integrity, Power Integrity"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_8575414d-558"},"title":"ASIC Digital Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You have at least 3 years of hands-on experience in digital design, writing RTL that has to synthesize cleanly, meet timing, and actually work in silicon. You know the difference between code that passes lint and code that makes the verification activities easier in the next months.</p>\n<p><strong>What You&#39;ll Be Doing</strong></p>\n<ul>\n<li>Design and implement RTL for digital and mixed signal IP blocks using Verilog and SystemVerilog, following established coding standards and quality checks</li>\n<li>Participate in architecture exploration and contribute to design specifications that guide both implementation and verification</li>\n<li>Run synthesis exploration and constraints mapping, analyze timing and power results, and iterate on your RTL to meet performance targets</li>\n<li>Support DFT and ATPG flows and coverage analysis</li>\n<li>Generate high-quality documents targeting different audiences: customer consumable and to support design implementation and verification teams</li>\n<li>Collaborate with verification engineers to define testbenches, debug failures, and close coverage gaps</li>\n<li>Continuously integrate AI-assisted tools into your workflow to improve coding efficiency, debugging speed, and code review quality</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Your RTL will ship as part of Synopsys IP that powers semiconductor designs across automotive, mobile, data center, high-performance computing, and AI applications</li>\n<li>The quality and clarity of your design documentation will directly reduce integration time for customers and internal teams</li>\n<li>Your synthesis and timing work will determine whether IP blocks meet performance and power targets that define product competitiveness</li>\n<li>The DFT structures you design will enable high test coverage and reduce manufacturing defects in silicon</li>\n<li>Your collaboration with verification teams will help to anticipate issue detection, reducing costly respins and schedule delays</li>\n<li>The design patterns and flows you establish will influence how the broader mixed-signal IP team approaches future projects</li>\n<li>Your adoption of AI tools will help the team move faster and set new standards for productivity across the Porto site</li>\n</ul>\n<p><strong>What You&#39;ll Need</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering, Computer Engineering, or a closely related field</li>\n<li>At least 3 years of hands-on experience in ASIC digital design, RTL development, or front-end design flows</li>\n<li>Strong proficiency in Hardware Description Languages (Verilog, SystemVerilog, VHDL) for RTL design and behavioral modeling</li>\n<li>Solid understanding of DFT and ATPG methodologies</li>\n<li>Experience with synthesis flow, constraints mapping, timing analysis, and power optimization in a production design environment</li>\n<li>Fluency in English, both written and spoken, for documentation and cross-site collaboration</li>\n<li>Experience with high-speed memory interfaces such as DDR/HBM is a strong plus</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_8575414d-558","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/moreira/asic-digital-design-staff-engineer/44408/101134959648?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["Verilog","SystemVerilog","VHDL","DFT","ATPG","synthesis flow","constraints mapping","timing analysis","power optimization"],"x-skills-preferred":["high-speed memory interfaces such as DDR/HBM"],"datePosted":"2026-09-26T00:18:03.694Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Moreira"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"Verilog, SystemVerilog, VHDL, DFT, ATPG, synthesis flow, constraints mapping, timing analysis, power optimization, high-speed memory interfaces such as DDR/HBM"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_53f1446a-014"},"title":"Security Digital Design Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You bring solid experience in RTL design with a focus on building hardware that must be both performant and secure. Your work in digital design has taught you that security cannot be an afterthought, it must be architected into the IP from the beginning. You understand the interplay between hardware design decisions and security implications, and you make design choices that account for both functional correctness and threat resilience.</p>\n<p>You will:</p>\n<ul>\n<li>Design and implement RTL in Verilog and SystemVerilog for Security IP cores, translating security requirements into synthesizable, verifiable hardware</li>\n<li>Build and maintain test environments for digital hardware Security IP using SystemVerilog and UVM, ensuring coverage of corner cases and attack scenarios</li>\n<li>Verify IP cores and subsystems using modern verification techniques including UVM testbenches and formal verification tools</li>\n<li>Collaborate with hardware and software security engineers to analyze functional correctness and performance of embedded IP solutions across threat models</li>\n<li>Contribute to detailed design specifications, verification plans, and documentation that support global development and customer integration</li>\n<li>Work within an international team across time zones, coordinating design reviews, debugging sessions, and milestone deliveries</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Strengthen the security posture of IP cores that protect critical systems in automotive, AI, and high-performance computing applications</li>\n<li>Enable faster SoC integration by delivering IP that meets strict performance, power, and area requirements without compromising security</li>\n<li>Reduce customer risk and time-to-market by ensuring IP is verified to the highest standards before it ships</li>\n<li>Advance the state of hardware security design within Synopsys, contributing techniques and methods that influence future IP development</li>\n<li>Support the growth of Synopsys Security IP in high-growth markets where trust and resilience are non-negotiable</li>\n<li>Help maintain Synopsys&#39; leadership position in delivering silicon IP that customers depend on for differentiation and compliance</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Strong working knowledge of RTL design for hardware IP components, with hands-on experience writing synthesizable Verilog or SystemVerilog</li>\n<li>Experience with ASIC verification using SystemVerilog, UVM, or Verilog in real project environments</li>\n<li>Ability to create detailed test environment specifications that map requirements to verification objectives</li>\n<li>MSc or PhD in Electrical Engineering, Computer Science, or a related technical discipline</li>\n<li>Solid understanding of IC design flows including synthesis, timing analysis, and design-for-test concepts</li>\n<li>Strong problem-solving and debugging skills, with the ability to trace issues across RTL, simulation, and tooling layers</li>\n<li>Experience with hardware security concepts or cryptographic IP is a plus</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family</li>\n<li>In addition to company holidays, we have ETO and FTO Programs</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back</li>\n<li>Save for your future with our retirement plans that vary by region and country</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_53f1446a-014","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/moreira/security-digital-design-engineer/44408/101134959712?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL design","Verilog","SystemVerilog","ASIC verification","UVM","IC design flows"],"x-skills-preferred":["hardware security concepts","cryptographic IP"],"datePosted":"2026-09-26T00:17:43.972Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Moreira"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design, Verilog, SystemVerilog, ASIC verification, UVM, IC design flows, hardware security concepts, cryptographic IP"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_00963aa8-2f3"},"title":"Project Engineering Management, Principal Engineer","description":"<p>You are an experienced engineering and project management professional with a strong customer focus and a passion for delivering high-quality results. With 10+ years of experience, you thrive in dynamic environments, lead complex cross-functional initiatives, and communicate effectively at all organizational levels.</p>\n<p>You will partner with cross-functional engineering, product, and business teams to define project scope, requirements, and success criteria. You will develop and maintain comprehensive project plans, track project execution, and communicate project status to internal stakeholders and senior leadership.</p>\n<p>Your responsibilities will also include:</p>\n<ul>\n<li>Representing R&amp;D in customer engagements</li>\n<li>Evaluating and managing change requests and technical issues</li>\n<li>Managing product updates triggered by silicon process updates, design updates, and customer feedback</li>\n<li>Collaborating with Sales, Marketing, Customer Support, and IP Program Management teams</li>\n<li>Ensuring adherence to quality management system processes</li>\n<li>Mentoring and guiding team members</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Enabling the successful delivery of complex engineering programs</li>\n<li>Improving product quality, performance, and reliability</li>\n<li>Establishing and refining project management best practices</li>\n<li>Strengthening cross-functional alignment and collaboration</li>\n<li>Supporting the growth and evolution of the Synopsys IP and product portfolio</li>\n<li>Reinforcing Synopsys&#39; reputation as a technology leader</li>\n</ul>\n<p>What You&#39;ll Need:</p>\n<ul>\n<li>A degree in Engineering, Applied Science, or equivalent practical experience</li>\n<li>10+ years of experience in customer-facing project or program management roles</li>\n<li>Strong ability to manage customer expectations and communicate complex technical topics</li>\n<li>Proficiency with project management tools and issue-tracking systems</li>\n<li>Working knowledge of UNIX/Linux environments</li>\n<li>Familiarity with the development process for Mixed-Signal IP, SoC, or ASIC development programs</li>\n<li>Understanding of quality management system processes and procedures</li>\n<li>Excellent organizational, time-management, and prioritization skills</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_00963aa8-2f3","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/moreira/project-engineering-management-principal-engineer/44408/100992953984?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["project management","engineering","customer-facing","UNIX/Linux","issue-tracking systems"],"x-skills-preferred":["Mixed-Signal IP","SoC","ASIC development programs","quality management system processes"],"datePosted":"2026-09-22T22:09:36.582Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Moreira, Porto"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"project management, engineering, customer-facing, UNIX/Linux, issue-tracking systems, Mixed-Signal IP, SoC, ASIC development programs, quality management system processes"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_f5ce357d-ad0"},"title":"ASIC Digital Design, Principal Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You have spent a decade or more designing digital logic that has to hold up in real silicon, not just pass simulation, and you know that the difference between a block that tapes out clean and one that comes back with a respin is usually a micro-architecture decision made six months earlier. High-speed communication protocols are your territory. You have worked on DDR, HBM, or similar interfaces enough times to know where the edge cases live and how to design around them without overbuilding.</p>\n<p><strong>What You&#39;ll Be Doing</strong></p>\n<ul>\n<li>Define micro-architecture for mixed-signal IP blocks from industry specifications and internal architecture definitions, balancing performance, power, area, latency and timing for HPC applications</li>\n<li>Develop RTL for complex digital blocks within high-speed communication IP, including DDR and HBM interfaces</li>\n<li>Model circuit behavior for analog and mixed-signal components to enable co-design and early validation</li>\n<li>Define and refine synthesis constraints, working closely with physical design and timing closure teams to ensure your blocks meet targets</li>\n<li>Run and review code quality checks (Lint, CDC and RDC analysis), catching issues early in the development cycle</li>\n<li>Evaluate design trade-offs across multiple dimensions and recommend solutions that align with product goals and market requirements</li>\n<li>Mentor engineers on your team, reviewing designs, providing technical guidance, and helping them build the judgment that comes with experience</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Your micro-architecture decisions will define the performance and efficiency profile of next-generation memory IP used in high-performance computing systems</li>\n<li>The RTL you develop will be synthesized, verified, and manufactured in leading-edge process nodes, directly affecting product competitiveness</li>\n<li>Your behavioral models will enable early co-design between digital and analog teams, reducing integration risk and schedule slip</li>\n<li>The constraints and design practices you establish will set the quality bar for the broader IP development team</li>\n<li>Your mentorship will accelerate the growth of engineers around you, building the technical depth the team needs to scale</li>\n<li>The trade-off analysis you provide will inform product roadmap decisions and help leadership prioritize the right features for the right markets</li>\n<li>Your attention to CDC, RDC, and code quality will reduce downstream debug time and improve first-pass silicon success rates</li>\n</ul>\n<p><strong>What You&#39;ll Need</strong></p>\n<ul>\n<li>Master&#39;s degree in Electrical Engineering, Computer Engineering, or a related field</li>\n<li>10+ years of hands-on ASIC digital design experience, with a strong track record of blocks that have taped out and worked</li>\n<li>Deep expertise in high-speed communication protocols, specifically DDR, HBM, or similar memory interfaces</li>\n<li>Solid understanding of low power design techniques and how to apply them in performance-critical contexts</li>\n<li>Strong knowledge of clock domain crossing (CDC) and reset domain crossing (RDC) analysis, and experience resolving violations in complex designs</li>\n<li>Experience with synthesis flows, including physical-aware synthesis and constraint definition for timing closure</li>\n<li>Familiarity with mixed-signal design environments and the ability to work effectively with circuit designers and behavioral models is a strong plus</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family</li>\n<li>In addition to company holidays, we have ETO and FTO Programs</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back</li>\n<li>Save for your future with our retirement plans that vary by region and country</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_f5ce357d-ad0","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/moreira/asic-digital-design-principal-engineer/44408/100442531088?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC digital design","High-speed communication protocols","DDR","HBM","Mixed-signal design","Clock domain crossing analysis","Reset domain crossing analysis","Synthesis flows","Physical-aware synthesis","Constraint definition for timing closure"],"x-skills-preferred":["Familiarity with mixed-signal design environments"],"datePosted":"2026-09-11T15:06:07.434Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Moreira"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC digital design, High-speed communication protocols, DDR, HBM, Mixed-signal design, Clock domain crossing analysis, Reset domain crossing analysis, Synthesis flows, Physical-aware synthesis, Constraint definition for timing closure, Familiarity with mixed-signal design environments"}]}