{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/city/ho-chi-minh-city"},"x-facet":{"type":"city","slug":"ho-chi-minh-city","display":"Ho Chi Minh City","count":33},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_b3b485f3-48e"},"title":"Applications Engineering Engineer","description":"<p>We are seeking an Applications Engineering Engineer to join our team in Ho Chi Minh City, Vietnam. As an Applications Engineering Engineer, you will support customers using Synopsys implementation tools like Fusion Compiler and IC Compiler II, helping them debug timing violations, routing congestion, floorplanning issues, and power/area tradeoffs.</p>\n<p>You will analyze customer design flows from RTL to GDSII, reproduce issues in-house, and work with internal engineering teams to resolve tool-related or methodology challenges. You will also review tool logs, identify root causes of failures or performance bottlenecks, and provide clear technical guidance to customers on next steps.</p>\n<p>Additionally, you will develop and deliver technical documentation, application notes, and best practice guides based on customer engagements and recurring issues. You will participate in customer meetings, debug sessions, and technical reviews, representing Synopsys as a trusted technical resource.</p>\n<p>You will collaborate with product engineering, R&amp;D to escalate complex cases and contribute to product improvement based on real-world customer feedback. You will also build internal knowledge through hands-on work with synthesis, place and route, timing closure, and physical verification flows.</p>\n<p>The ideal candidate will have a solid understanding of digital design fundamentals and the RTL-to-GDSII physical implementation flow. You will have knowledge of synthesis and physical design concepts including timing closure, floorplanning, place and route, and congestion analysis.</p>\n<p>You will be able to work in Linux/Unix environments and navigate command-line workflows. Strong written and verbal communication skills in English are required, as you will be working directly with customers and internal teams.</p>\n<p>Hands-on experience with Fusion Compiler, IC Compiler II, or similar industry-standard implementation tools is a strong plus. Scripting experience in TCL, Python, Perl, or Shell is also a plus and will help you automate tasks and debug faster.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_b3b485f3-48e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/applications-engineering-engineer-19447/44408/102322183104?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["digital design","physical implementation","RTL-to-GDSII flow","synthesis","place and route","timing closure","floorplanning","congestion analysis","Linux/Unix","English"],"x-skills-preferred":["Fusion Compiler","IC Compiler II","TCL","Python","Perl","Shell"],"datePosted":"2026-10-23T12:07:47.460Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City, Ho Chi Minh"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"digital design, physical implementation, RTL-to-GDSII flow, synthesis, place and route, timing closure, floorplanning, congestion analysis, Linux/Unix, English, Fusion Compiler, IC Compiler II, TCL, Python, Perl, Shell"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_8cdd972f-788"},"title":"Technical Engineering Intern - Design for Test (DFT) Internship","description":"<p>Our internship programs offer real-world projects, hands-on experience, and opportunities to collaborate with passionate teams globally.</p>\n<p>As a DFT Intern Engineer, you will contribute to the development of high-quality semiconductor IP and SoC solutions while gaining invaluable hands-on experience in real-world chip development projects.</p>\n<p>Your responsibilities will include:</p>\n<ul>\n<li>Supporting DFT Implementation and Verification: Assist in Design-for-Test activities including scan insertion, ATPG (Automatic Test Pattern Generation), test coverage analysis, and validation to ensure silicon testability and quality.</li>\n<li>Developing Automation Solutions: Create and deliver scripting and automation tools using TCL, Perl, Python, or Shell to improve engineering productivity and streamline DFT workflows.</li>\n<li>Collaborating on Chip Development Projects: Work alongside experienced engineers on innovative technologies powering data center, AI, mobile, and automotive applications, contributing to the successful delivery of trusted silicon solutions.</li>\n<li>Debugging and Problem-Solving: Analyze and resolve design and test-related issues, applying strong analytical skills to enhance design efficiency and manufacturing yield.</li>\n<li>Participating in Technical Reviews: Engage actively in team discussions, technical reviews, and project activities, sharing your ideas and learning from industry experts in semiconductor design and test methodologies.</li>\n</ul>\n<p>Required Qualifications:</p>\n<ul>\n<li>Currently pursuing a final-year undergraduate or graduate degree in Electronics Engineering, Computer Engineering, Telecommunications, Electrical Engineering, or related disciplines.</li>\n<li>Basic understanding of CMOS and digital logic design fundamentals.</li>\n<li>Scripting experience with languages such as TCL, Perl, Python, or Shell.</li>\n<li>Strong analytical and problem-solving skills with a passion for semiconductor technologies.</li>\n<li>Good communication skills in English, both written and verbal.</li>\n<li>Self-motivated, eager to learn, with strong teamwork and collaboration abilities.</li>\n</ul>\n<p>Preferred Qualifications:</p>\n<ul>\n<li>Basic knowledge of Design-for-Test (DFT) concepts, including Scan, ATPG, and JTAG.</li>\n<li>Familiarity with Linux/Unix environments.</li>\n<li>Experience with EDA tools such as Synopsys Design Compiler (DC), Fusion Compiler (FC), PrimeTime, TestMax, Verdi, or similar platforms.</li>\n<li>Participation in academic, research, or personal projects related to digital IC design or ASIC design.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_8cdd972f-788","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/technical-engineering-intern-design-for-test-dft-internship/44408/102251697392?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":null,"x-job-type":"internship","x-salary-range":null,"x-skills-required":["CMOS","digital logic design","TCL","Perl","Python","Shell","analytical skills","semiconductor technologies","English communication"],"x-skills-preferred":["DFT concepts","Scan","ATPG","JTAG","Linux/Unix environments","EDA tools","digital IC design","ASIC design"],"datePosted":"2026-10-22T11:24:53.258Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City, Ho Chi Minh"}},"employmentType":"INTERN","occupationalCategory":"Engineering","industry":"Technology","skills":"CMOS, digital logic design, TCL, Perl, Python, Shell, analytical skills, semiconductor technologies, English communication, DFT concepts, Scan, ATPG, JTAG, Linux/Unix environments, EDA tools, digital IC design, ASIC design"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_7824aa7c-fef"},"title":"Applications Engineering Engineer","description":"<p>We are seeking an early-career engineer who is curious about how digital chips are implemented and eager to build hands-on expertise in ASIC physical design.</p>\n<p>As an Applications Engineering Engineer at Synopsys, you will provide hands-on technical support for customers using Synopsys Design Implementation and Verification tools, including troubleshooting issues in physical design flows like floorplanning, placement, CTS, routing, and timing closure.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Provide hands-on technical support for customers using Synopsys Design Implementation and Verification tools</li>\n<li>Take ownership of customer technical cases from initial investigation through resolution</li>\n<li>Collaborate with R&amp;D engineering teams across regions to escalate complex issues</li>\n<li>Build and maintain strong relationships with customers</li>\n<li>Work with Synopsys Fusion Compiler, ICC2, and related signoff tools to help customers optimize their implementation methodologies</li>\n<li>Create and refine technical documentation, application notes, and best practices</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Directly unblock customer design teams so they can meet tapeout schedules and deliver working silicon on time</li>\n<li>Reduce the time it takes for customers to adopt new Synopsys tools and features</li>\n<li>Surface real-world customer pain points to R&amp;D teams, influencing product roadmaps</li>\n<li>Build trust and long-term partnerships with customers in the region</li>\n<li>Help customers achieve better PPA (power, performance, area) outcomes</li>\n<li>Contribute to a global knowledge base that helps Application Engineers worldwide solve problems faster</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering, Electronics Engineering, Computer Science, or a related technical field</li>\n<li>Understanding of ASIC physical design and implementation methodologies</li>\n<li>Working knowledge of Verilog and digital design fundamentals</li>\n<li>Comfort with Linux or Unix environments and scripting in Tcl, Python, Perl, or Shell</li>\n<li>Strong English communication skills</li>\n<li>Exposure to Synopsys Fusion Compiler, ICC2, or related signoff tools is a strong plus</li>\n</ul>\n<p>Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7824aa7c-fef","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/applications-engineering-engineer-19312/44408/102187025600?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"entry","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","Verilog","digital design fundamentals","Linux","Tcl","Python","Perl","Shell","English communication"],"x-skills-preferred":["Synopsys Fusion Compiler","ICC2","related signoff tools","Application Engineering experience"],"datePosted":"2026-10-20T10:04:28.403Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City, Ho Chi Minh"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, Verilog, digital design fundamentals, Linux, Tcl, Python, Perl, Shell, English communication, Synopsys Fusion Compiler, ICC2, related signoff tools, Application Engineering experience"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c13a0327-769"},"title":"Applications Engineering Engineer","description":"<p>We are seeking an early-career engineer who is curious about how digital chips are implemented and eager to build hands-on expertise in ASIC physical design. As an Applications Engineering Engineer at Synopsys, you will provide hands-on technical support for customers using Synopsys Design Implementation and Verification tools.</p>\n<p>You will work directly with customers using tools that shape how chips get built, and the problems you solve will matter. Your responsibilities will include:</p>\n<ul>\n<li>Providing hands-on technical support for customers using Synopsys Design Implementation and Verification tools, including troubleshooting issues in physical design flows like floorplanning, placement, CTS, routing, and timing closure</li>\n<li>Taking ownership of customer technical cases from initial investigation through resolution, debugging tool behavior, analyzing design data, and working with customers to deploy solutions</li>\n<li>Collaborating with R&amp;D engineering teams across regions to escalate complex issues, communicate customer requirements, and validate fixes or new features before deployment</li>\n<li>Building and maintaining strong relationships with customers by proactively following up on open issues, understanding their design challenges, and ensuring they get the most out of Synopsys tools</li>\n<li>Working with Synopsys Fusion Compiler, ICC2, and related signoff tools to help customers optimize their implementation methodologies and improve design outcomes</li>\n<li>Creating and refining technical documentation, application notes, and best practices based on real customer engagements and lessons learned in the field</li>\n</ul>\n<p>The impact you will have:</p>\n<ul>\n<li>Directly unblock customer design teams so they can meet tapeout schedules and deliver working silicon on time</li>\n<li>Reduce the time it takes for customers to adopt new Synopsys tools and features by providing clear guidance and proven methodologies</li>\n<li>Surface real-world customer pain points to R&amp;D teams, influencing product roadmaps and making tools better for the entire user base</li>\n<li>Build trust and long-term partnerships with customers in the region, expanding Synopsys&#39;s technical footprint and customer satisfaction scores</li>\n<li>Help customers achieve better PPA (power, performance, area) outcomes by optimizing their use of physical design and verification flows</li>\n<li>Contribute to a global knowledge base that helps Application Engineers worldwide solve problems faster and more effectively</li>\n<li>Strengthen Synopsys&#39;s reputation as a company that does not just sell tools but stands behind them with world-class technical support</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering, Electronics Engineering, Computer Science, or a related technical field</li>\n<li>Understanding of ASIC physical design and implementation methodologies, including floorplanning, placement, clock tree synthesis, routing, and static timing analysis</li>\n<li>Working knowledge of Verilog and digital design fundamentals</li>\n<li>Comfort with Linux or Unix environments and scripting in Tcl, Python, Perl, or Shell</li>\n<li>Strong English communication skills, both written and verbal, with the ability to explain technical concepts clearly to customers and internal teams</li>\n<li>Exposure to Synopsys Fusion Compiler, ICC2, or related signoff tools is a strong plus</li>\n<li>Application Engineering experience supporting implementation flows or customer-facing technical roles is a plus</li>\n</ul>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c13a0327-769","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/applications-engineering-engineer-19307/44408/102143953376?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"entry","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","Verilog","digital design","Linux","Tcl","Python","Shell scripting","English communication"],"x-skills-preferred":["Synopsys Fusion Compiler","ICC2","Application Engineering experience"],"datePosted":"2026-10-19T09:20:39.622Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City, Ho Chi Minh"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, Verilog, digital design, Linux, Tcl, Python, Shell scripting, English communication, Synopsys Fusion Compiler, ICC2, Application Engineering experience"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_ae2e33ca-736"},"title":"Applications Engineering Engineer","description":"<p>We are seeking an early-career engineer who is curious about how digital chips are implemented and eager to build hands-on expertise in ASIC physical design.</p>\n<p>As an Applications Engineering Engineer at Synopsys, you will provide hands-on technical support for customers using Synopsys Design Implementation and Verification tools, including troubleshooting issues in physical design flows like floorplanning, placement, CTS, routing, and timing closure.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Provide hands-on technical support for customers using Synopsys Design Implementation and Verification tools</li>\n<li>Take ownership of customer technical cases from initial investigation through resolution</li>\n<li>Collaborate with R&amp;D engineering teams across regions to escalate complex issues</li>\n<li>Build and maintain strong relationships with customers</li>\n<li>Work with Synopsys Fusion Compiler, ICC2, and related signoff tools to help customers optimize their implementation methodologies</li>\n<li>Create and refine technical documentation, application notes, and best practices</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Directly unblock customer design teams so they can meet tapeout schedules and deliver working silicon on time</li>\n<li>Reduce the time it takes for customers to adopt new Synopsys tools and features</li>\n<li>Surface real-world customer pain points to R&amp;D teams, influencing product roadmaps</li>\n<li>Build trust and long-term partnerships with customers in the region</li>\n<li>Help customers achieve better PPA (power, performance, area) outcomes</li>\n<li>Contribute to a global knowledge base that helps Application Engineers worldwide solve problems faster and more effectively</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering, Electronics Engineering, Computer Science, or a related technical field</li>\n<li>Understanding of ASIC physical design and implementation methodologies</li>\n<li>Working knowledge of Verilog and digital design fundamentals</li>\n<li>Comfort with Linux or Unix environments and scripting in Tcl, Python, Perl, or Shell</li>\n<li>Strong English communication skills, both written and verbal</li>\n<li>Exposure to Synopsys Fusion Compiler, ICC2, or related signoff tools is a strong plus</li>\n</ul>\n<p>Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_ae2e33ca-736","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/applications-engineering-engineer-19308/44408/102143953392?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"entry","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","Verilog","digital design fundamentals","Linux","Tcl","Python","Perl","Shell scripting"],"x-skills-preferred":["Synopsys Fusion Compiler","ICC2","related signoff tools","Application Engineering experience"],"datePosted":"2026-10-19T09:19:25.842Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City, Ho Chi Minh"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, Verilog, digital design fundamentals, Linux, Tcl, Python, Perl, Shell scripting, Synopsys Fusion Compiler, ICC2, related signoff tools, Application Engineering experience"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_55a83381-ba2"},"title":"Applications Engineering Engineer","description":"<p>We are seeking an early-career engineer who is curious about how digital chips are implemented and eager to build hands-on expertise in ASIC physical design. As an Applications Engineering Engineer at Synopsys, you will provide hands-on technical support for customers using Synopsys Design Implementation and Verification tools.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Provide technical support for customers using Synopsys Design Implementation and Verification tools</li>\n<li>Troubleshoot issues in physical design flows like floorplanning, placement, CTS, routing, and timing closure</li>\n<li>Collaborate with R&amp;D engineering teams across regions to escalate complex issues</li>\n<li>Build and maintain strong relationships with customers</li>\n<li>Work with Synopsys Fusion Compiler, ICC2, and related signoff tools</li>\n<li>Create and refine technical documentation, application notes, and best practices</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Directly unblock customer design teams so they can meet tapeout schedules and deliver working silicon on time</li>\n<li>Reduce the time it takes for customers to adopt new Synopsys tools and features</li>\n<li>Surface real-world customer pain points to R&amp;D teams, influencing product roadmaps</li>\n<li>Build trust and long-term partnerships with customers in the region</li>\n<li>Help customers achieve better PPA (power, performance, area) outcomes</li>\n<li>Contribute to a global knowledge base that helps Application Engineers worldwide solve problems faster and more effectively</li>\n</ul>\n<p>What You&#39;ll Need:</p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering, Electronics Engineering, Computer Science, or a related technical field</li>\n<li>Understanding of ASIC physical design and implementation methodologies</li>\n<li>Working knowledge of Verilog and digital design fundamentals</li>\n<li>Comfort with Linux or Unix environments and scripting in Tcl, Python, Perl, or Shell</li>\n<li>Strong English communication skills, both written and verbal</li>\n<li>Exposure to Synopsys Fusion Compiler, ICC2, or related signoff tools is a strong plus</li>\n</ul>\n<p>Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_55a83381-ba2","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/applications-engineering-engineer-19309/44408/102143953408?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"entry","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","Verilog","digital design fundamentals","Linux","Tcl","Python","Perl","Shell","English communication"],"x-skills-preferred":["Synopsys Fusion Compiler","ICC2","related signoff tools","Application Engineering experience"],"datePosted":"2026-10-19T09:18:42.789Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City, Ho Chi Minh"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, Verilog, digital design fundamentals, Linux, Tcl, Python, Perl, Shell, English communication, Synopsys Fusion Compiler, ICC2, related signoff tools, Application Engineering experience"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_78542882-453"},"title":"Application Engineering Engineer","description":"<p>We are seeking an Application Engineering Engineer to join our team in Ho Chi Minh City, Vietnam. As an Application Engineering Engineer, you will provide technical support for EDA design and verification tools, including VCS, Verdi, Spyglass, Certitude, and Z01X, troubleshooting customer issues and working toward resolution.</p>\n<p>You will take ownership of tool migrations and validation across different release versions, ensuring customers can move forward without breaking their workflows. You will collaborate with application engineers, R&amp;D teams, and customers globally to understand requirements, escalate complex issues, and support successful tool adoption.</p>\n<p>Your responsibilities will also include building and maintaining strong customer relationships by actively tracking issues, following up on feedback, and ensuring satisfaction throughout the support lifecycle. You will learn and apply new tool features and capabilities, including AI-related functionality, as they become available.</p>\n<p>The ideal candidate will have a bachelor&#39;s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. You should have a basic understanding of design and verification methodologies, or prior experience as an application engineer in the verification field. Working knowledge of Verilog is required, and familiarity with SystemVerilog, UVM, VHDL, or UPF is a plus.</p>\n<p>In return, we offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_78542882-453","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/application-engineering-engineer-19310/44408/102039901040?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":null,"x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Verilog","SystemVerilog","UVM","VHDL","UPF","EDA design and verification tools"],"x-skills-preferred":["AI-related capabilities in EDA","standard protocols and verification IPs such as AMBA VIP"],"datePosted":"2026-10-17T09:22:33.247Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City, Ho Chi Minh"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Verilog, SystemVerilog, UVM, VHDL, UPF, EDA design and verification tools, AI-related capabilities in EDA, standard protocols and verification IPs such as AMBA VIP"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_a97fbebc-dab"},"title":"Analog Design Engineer (Da Nang)","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You are someone who likes working close to the silicon, where the physics and the design meet and where a miscalculation in power distribution can mean the difference between a chip that ships and one that doesn&#39;t. You understand that analog design is not just about drawing schematics, it is about making sure the power gets where it needs to go without melting traces or starving cells.</p>\n<p>You have built a foundation in VLSI and IC design, and you are ready to go deeper into the real constraints that come with tapeout. Power integrity, IR drop, and electromigration are not just checkboxes to you, they are problems you want to understand and solve. You are comfortable with a terminal open, writing scripts in Python or Tcl to automate checks or pull data, and you know your way around Linux well enough to get things done without asking for help every time.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Work on analog and mixed-signal IC design tasks with a focus on power integrity, IR drop analysis, and electromigration checks</li>\n<li>Run physical design flows and signoff checks using industry-standard EDA tools from Synopsys, Cadence, or Ansys</li>\n<li>Write and maintain scripts in Python, Tcl, or Shell to automate design verification, analysis, and reporting tasks</li>\n<li>Collaborate with layout, verification, and backend teams to identify and resolve design issues before tapeout</li>\n<li>Debug power and signal integrity issues using simulation and analysis tools in a Linux environment</li>\n<li>Support design reviews and contribute to documentation of methodologies, results, and learnings</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>You will help ensure that chips meet power and reliability targets before they ever reach fabrication</li>\n<li>Your scripting and automation work will speed up analysis cycles and reduce manual errors across the design flow</li>\n<li>You will catch issues early in the physical design process, saving time and cost downstream</li>\n<li>Your attention to detail will directly contribute to higher quality signoff and fewer respins</li>\n<li>You will build expertise in power integrity and physical design that becomes a foundation for the team&#39;s future work</li>\n<li>You will help establish best practices and repeatable flows that other engineers can build on</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering, Electronics, Microelectronics, or a related field</li>\n<li>Fundamental knowledge of VLSI and IC design principles</li>\n<li>Understanding of Power Integrity, IR Drop, and Electromigration concepts</li>\n<li>Basic scripting ability in Python, TCL, or Shell</li>\n<li>Comfort working in a Linux environment for design and analysis tasks</li>\n<li>Familiarity with physical design and signoff flows, exposure to Synopsys, Cadence, or Ansys EDA tools is a plus</li>\n<li>Strong analytical and problem-solving skills.</li>\n<li>Good communication and teamwork.</li>\n<li>Quick learner, detail-oriented, and self-motivated.</li>\n<li>Good written and verbal English.</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.</li>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n<li>Competitive salaries.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_a97fbebc-dab","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/analog-design-engineer-da-nang/44408/101981588896?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":null,"x-job-type":"Employee","x-salary-range":null,"x-skills-required":["VLSI","IC design","Power Integrity","IR Drop","Electromigration","Python","Tcl","Shell","Linux"],"x-skills-preferred":["physical design","signoff flows","Synopsys","Cadence","Ansys EDA tools"],"datePosted":"2026-10-16T09:28:21.629Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"VLSI, IC design, Power Integrity, IR Drop, Electromigration, Python, Tcl, Shell, Linux, physical design, signoff flows, Synopsys, Cadence, Ansys EDA tools"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_898cd4ab-249"},"title":"SoC Verification Engineer","description":"<p>We are seeking a SoC Verification Engineer to join our team at Synopsys in Ho Chi Minh City, Vietnam. As a SoC Verification Engineer, you will be responsible for designing and developing cutting-edge semiconductor solutions. You will work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>Job Description</strong></p>\n<p>You have spent years in verification knowing that finding the bug before tapeout is the difference between a product that ships and one that doesn&#39;t. You understand that a good testbench is not about coverage numbers on a dashboard, it is about building an environment that stresses the design in ways that matter. You think in corner cases. When someone describes a new protocol feature, you are already mentally mapping the sequences that will break it.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Define block and subsystem verification plans that map directly to design specifications and protocol requirements</li>\n<li>Build UVM testbenches in System Verilog, including agents, scoreboards, coverage models, and assertion monitors</li>\n<li>Write constrained random and directed tests that exercise protocol compliance, corner cases, and error injection scenarios</li>\n<li>Debug RTL and testbench failures using simulators and waveform analysis to root cause and resolve issues</li>\n<li>Collaborate with RTL designers and global verification engineers to align on design intent and coverage goals</li>\n<li>Apply formal verification techniques to prove properties and close coverage gaps</li>\n<li>Drive verification closure by tracking coverage metrics and iterating on test plans until signoff</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering, Computer Engineering, or Computer Science or related fields</li>\n<li>0-4 years of hands-on design verification experience in the semiconductor industry</li>\n<li>Proficiency in System Verilog and UVM for building testbenches and implementing coverage</li>\n<li>Knowledge of at least one protocol such as AMBA, PCI Express, CXL, UCIe, Ethernet, HBM, or DDR</li>\n<li>Experience with industry standard simulators like VCS, Xcelium, or Questa, and version control systems</li>\n<li>Solid scripting skills in Python, Perl, or Tcl for automation and regression management</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family</li>\n<li>In addition to company holidays, we have ETO and FTO Programs</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back</li>\n<li>Save for your future with our retirement plans that vary by region and country</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_898cd4ab-249","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/soc-verification-engineer/44408/101938929984?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"entry","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["System Verilog","UVM","protocol compliance","corner cases","error injection scenarios","debug RTL and testbench failures","formal verification techniques","coverage metrics"],"x-skills-preferred":["Python","Perl","Tcl","VCS","Xcelium","Questa"],"datePosted":"2026-10-15T08:14:19.205Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"System Verilog, UVM, protocol compliance, corner cases, error injection scenarios, debug RTL and testbench failures, formal verification techniques, coverage metrics, Python, Perl, Tcl, VCS, Xcelium, Questa"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_fbe6fd0c-93f"},"title":"Application Engineering Manager (Physical Design)","description":"<p>Lead and manage a team of Physical Design Application Engineers supporting Synopsys implementation solutions across strategic semiconductor customers.</p>\n<p>Drive technical excellence, customer success, and business growth by ensuring high-quality support, successful deployments, and strong customer relationships.</p>\n<p>Partner closely with customers, sales, product management, and R&amp;D organizations to define technical strategies and address critical customer requirements.</p>\n<p>Provide leadership for technical campaigns, customer escalations, methodology development, and adoption of next-generation Physical Design technologies.</p>\n<p>Coach, mentor, and develop team members while building a strong pipeline of technical talent and future leaders.</p>\n<p>Drive operational excellence through effective resource planning, prioritization, service quality management, and performance execution.</p>\n<p>Contribute to long-term business strategies that expand customer engagement, strengthen competitive positioning, and accelerate technology adoption.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Leading a team of Physical Design Application Engineers</li>\n<li>Driving technical excellence and customer success</li>\n<li>Partnering with customers, sales, and R&amp;D organizations</li>\n<li>Providing leadership for technical campaigns and customer escalations</li>\n<li>Coaching and mentoring team members</li>\n<li>Driving operational excellence</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>8+ years of experience in ASIC Physical Design, Design Implementation, or Application Engineering</li>\n<li>2+ years of leadership, team management, or technical leadership experience</li>\n<li>Strong expertise in Physical Design implementation methodologies</li>\n<li>Deep understanding of Synopsys Physical Design solutions</li>\n<li>Proven ability to lead customer engagements and drive successful business outcomes</li>\n<li>Experience supporting advanced technology nodes and complex SoC implementation projects</li>\n<li>Strong people leadership, coaching, and talent development capabilities</li>\n<li>Excellent communication, presentation, and stakeholder management skills</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_fbe6fd0c-93f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/application-engineering-manager-physical-design/44408/101724603616?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC Physical Design","Design Implementation","Application Engineering","Leadership","Team Management","Technical Leadership","Physical Design implementation methodologies","Synopsys Physical Design solutions","Customer Engagement","Business Outcomes","SoC implementation projects","Talent Development","Communication","Presentation","Stakeholder Management"],"x-skills-preferred":[],"datePosted":"2026-10-10T06:18:40.795Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City, Ho Chi Minh"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC Physical Design, Design Implementation, Application Engineering, Leadership, Team Management, Technical Leadership, Physical Design implementation methodologies, Synopsys Physical Design solutions, Customer Engagement, Business Outcomes, SoC implementation projects, Talent Development, Communication, Presentation, Stakeholder Management"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_bde1bc3d-e28"},"title":"Senior Application Engineer – Physical Design","description":"<p>Provide technical support and engineering solutions for advanced Physical Design implementation flows, helping customers successfully deploy leading-edge EDA technologies.</p>\n<p>Work closely with semiconductor customers to debug, optimize, and improve Physical Design methodologies across the design cycle.</p>\n<p>Collaborate with worldwide Application Engineers and R&amp;D teams to reproduce customer issues, analyze root causes, and deliver timely solutions.</p>\n<p>Drive technical engagements involving floorplanning, placement, optimization, CTS, routing, timing closure, and PPA improvement.</p>\n<p>Conduct technical presentations, customer trainings, methodology reviews, and knowledge-sharing sessions.</p>\n<p>Support adoption of Synopsys Physical Design solutions including Fusion Compiler, ICC2, and related implementation technologies.</p>\n<p><strong>Key Skills &amp; Experience:</strong></p>\n<ul>\n<li>3+ years of experience in ASIC Physical Design, Design Implementation, or Application Engineering.</li>\n<li>Strong hands-on experience with Synopsys Fusion Compiler and/or IC Compiler II (ICC2).</li>\n<li>Solid understanding of Physical Design methodologies including Floorplanning, Placement, CTS, Routing, Timing Closure, DRC/LVS Closure, and PPA optimization.</li>\n<li>Good knowledge of STA, extraction, physical verification, and signoff methodologies.</li>\n<li>Experience with PrimeTime (PT), StarRC, IC Validator (ICV), DSO.ai, or AI-driven optimization technologies is a plus.</li>\n<li>Familiarity with Tcl, Perl, Python, or Shell scripting.</li>\n<li>Strong debugging, problem-solving, and customer-facing skills.</li>\n<li>Excellent communication skills in English.</li>\n<li>Passion for solving complex Physical Design challenges and enabling customer success.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_bde1bc3d-e28","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/senior-application-engineer-physical-design/44408/101767928432?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC Physical Design","Design Implementation","Application Engineering","Synopsys Fusion Compiler","IC Compiler II (ICC2)","Physical Design methodologies","STA","extraction","physical verification","signoff methodologies","Tcl","Perl","Python","Shell scripting","debugging","problem-solving","customer-facing skills","English communication"],"x-skills-preferred":["PrimeTime (PT)","StarRC","IC Validator (ICV)","DSO.ai","AI-driven optimization technologies"],"datePosted":"2026-10-10T06:06:06.485Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City, Ho Chi Minh"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC Physical Design, Design Implementation, Application Engineering, Synopsys Fusion Compiler, IC Compiler II (ICC2), Physical Design methodologies, STA, extraction, physical verification, signoff methodologies, Tcl, Perl, Python, Shell scripting, debugging, problem-solving, customer-facing skills, English communication, PrimeTime (PT), StarRC, IC Validator (ICV), DSO.ai, AI-driven optimization technologies"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_0f650b63-54a"},"title":"Business Analysis Manager","description":"<p>Join Razer&#39;s global mission to revolutionize gaming.</p>\n<p>We are seeking a data-driven Business Analysis Manager to serve as the analytical gatekeeper for our mobile game publishing pipeline.</p>\n<p><strong>Job Responsibilities:</strong></p>\n<ul>\n<li>Game Evaluation &amp; Data-Backed Deconstruction (Primary Focus – 60%): thoroughly playtest and evaluate submitted or scouted game builds, analyze raw test data, and produce comprehensive evaluation reports.</li>\n<li>Market Intelligence &amp; Competitive Benchmarking (25%): utilize mobile market intelligence platforms to track top-performing games, extract and synthesize market data, and conduct competitor benchmarking.</li>\n<li>Cross-Functional &amp; Partner Deal Support (15%): prepare partner-facing materials, support deal negotiations, and work closely with internal teams during the pre-publishing phase.</li>\n</ul>\n<p><strong>Pre-Requisites:</strong></p>\n<ul>\n<li>Deep proficiency in data &amp; analytics tools, including market &amp; ad intelligence, product &amp; in-game analytics, and data processing &amp; BI.</li>\n<li>Gaming literacy &amp; deconstruction: extensive experience playing mobile games and connecting gameplay design to operational KPIs.</li>\n<li>Analytical storytelling &amp; communication: ability to translate complex gameplay experiences and raw market datasets into clear evaluation reports.</li>\n</ul>\n<p><strong>Benefits:</strong> Razer offers a unique, gamer-centric #LifeAtRazer experience that puts you in an accelerated growth environment, both personally and professionally.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_0f650b63-54a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Razer","sameAs":"https://razer.com","logo":"https://logos.yubhub.co/razer.com.png"},"x-apply-url":"https://razer.wd3.myworkdayjobs.com/en-US/Careers/job/Ho-Chi-Minh/Business-Analysis-Manager--Mobile-Game-_JR2026007979?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["data analysis","market intelligence","game development","analytics tools","SQL","Excel","Google Sheets","BI visualization tools"],"x-skills-preferred":[],"datePosted":"2026-10-10T01:07:01.218Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Operations","industry":"Technology","skills":"data analysis, market intelligence, game development, analytics tools, SQL, Excel, Google Sheets, BI visualization tools"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_dfab890a-87e"},"title":"Applications Engineering, Sr Supervisor( Verification Tools)","description":"<p>We are seeking an experienced Applications Engineering, Sr Supervisor (Verification Tools) to provide advanced technical support for EDA Design &amp; Verifications tools, addressing complex customer issues and ensuring customer satisfaction.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Provide advanced technical support for EDA Design &amp; Verifications tools (VCS, Verdi, Spyglass, Certitude, Z01X..)</li>\n<li>Take ownership of tool migrations, bring up verification environments, and Verification IPs</li>\n<li>Collaborate with worldwide Application Engineers, R&amp;D teams, and Customers to understand requirements, address escalations, and ensure successful adoption of solutions and tool development</li>\n<li>Develop and share technical documentation, lead knowledge transfer, and mentor junior team members</li>\n<li>Lead the application engineers to technical campaigns and build trust with customers</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>3+ years of Design and Verification or Application Engineer experience</li>\n<li>Leading experience in Design and Verification, with strong skills in Verilog, UVM, System Verilog, VHDL, and UPF</li>\n<li>Experience leading and managing a team of Application Engineers</li>\n<li>Strong expertise in Design and Verification methodologies, Standard protocol, and Verification IPs</li>\n<li>Excellent communication skills in English</li>\n<li>Passion for using new tools and features, as well as AI-related tools</li>\n<li>Ability to manage relationships with customers and internal stakeholders</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_dfab890a-87e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/applications-engineering-sr-supervisor-verification-tools/44408/101580799696?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Verilog","UVM","System Verilog","VHDL","UPF","Design and Verification methodologies","Standard protocol","Verification IPs"],"x-skills-preferred":["AI tool related"],"datePosted":"2026-10-07T04:21:21.043Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City, Ho Chi Minh"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Verilog, UVM, System Verilog, VHDL, UPF, Design and Verification methodologies, Standard protocol, Verification IPs, AI tool related"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_219a7544-3a1"},"title":"Sr/Staff Application Engineer(Verification tools)","description":"<p>As a Senior Application Engineer (Verification tools) at Synopsys, you will provide advanced technical support for EDA Design &amp; Verifications tools, addressing complex customer issues and ensuring customer satisfaction.</p>\n<p>Your responsibilities will include:</p>\n<ul>\n<li>Taking ownership of tool migrations, bringing up verification environments, and Verification IPs</li>\n<li>Collaborating with worldwide Application Engineers, R&amp;D teams, and customers to understand requirements, address escalations, and ensure successful adoption of solutions and tool development</li>\n<li>Actively contributing to strategies that secure and expand market share by understanding the competitive landscape and building strong customer relationships</li>\n<li>Developing and sharing technical documentation, leading knowledge transfer, and mentoring junior team members</li>\n</ul>\n<p>To be successful in this role, you will need:</p>\n<ul>\n<li>1+ years of experience in Design and Verification or as an Application Engineer in the Verification Field</li>\n<li>Good knowledge of Verilog, UVM, System Verilog, VHDL, and UPF</li>\n<li>Expertise in Design and Verification, Verification IPs (AMBA VIP), Static and/or Dynamic Verification</li>\n<li>Excellent communication skills in English, with the ability to work cross-functionally and cross-regionally</li>\n<li>Passion for using new tools and features, as well as AI-related tools</li>\n<li>Ability to manage relationships with both customers and internal stakeholders</li>\n<li>Demonstrated leadership in mentoring, onboarding, or leading technical initiatives</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_219a7544-3a1","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/sr-staff-application-engineer-verification-tools/44408/101580799664?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Verilog","UVM","System Verilog","VHDL","UPF","Design and Verification","Verification IPs","Static and Dynamic Verification","English communication"],"x-skills-preferred":["AI tool related"],"datePosted":"2026-10-07T04:19:17.533Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City, Ho Chi Minh"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Verilog, UVM, System Verilog, VHDL, UPF, Design and Verification, Verification IPs, Static and Dynamic Verification, English communication, AI tool related"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_740c01f3-08d"},"title":"Accounts Receivable Collections Analyst","description":"<p>We are seeking a driven Accounts Receivable Collections Analyst to join our AR Operations department. You will focus on supporting daily operations, setting high standards for exceptional customer service, and managing sensitive external relationships.</p>\n<p><strong>Responsibilities:</strong></p>\n<ul>\n<li><strong>Collections &amp; Account Management</strong></li>\n<li>Oversee day-to-day collections efforts, managing open receivables on assigned accounts via email and phone to drive Flexport&#39;s DSO targets</li>\n<li>Drive against targets by executing workflows and monitoring metrics daily on assigned accounts</li>\n<li>Work on moderately difficult account assignments requiring judgement and independent recommendations</li>\n<li>Partner with the Credit team to arrange payment schedules and collect funds on accounts in arrears</li>\n</ul>\n<ul>\n<li><strong>Client Relationship Management</strong></li>\n<li>Establish relationships with key client Accounts Payable personnel, serving as the dedicated point of contact to facilitate cash collection and credit processes</li>\n<li>Manage the allocation of requests, resolve complex client issues, and handle first-level escalations, maintaining high standards for accuracy, timeliness, and professionalism</li>\n<li>Field general AR/AP questions from clients and assist in researching and resolving payment issues</li>\n</ul>\n<ul>\n<li><strong>Cross-Functional Collaboration</strong></li>\n<li>Build and maintain effective working relationships with Credit, Account Management, Sales, Disputes, and Legal teams to drive collections and resolve past-due account issues</li>\n<li>Partner with the AR Manager to identify opportunities to improve SOPs and processes</li>\n</ul>\n<ul>\n<li><strong>Finance Operations</strong></li>\n<li>Support Finance &amp; Accounting month-end close processes and other ad-hoc projects as needed</li>\n</ul>\n<p><strong>Requirements:</strong></p>\n<ul>\n<li>Strong attention to detail and professional written and verbal communication, with the ability to handle situations tactfully, confidently, and ethically</li>\n<li>A competitive, creative drive to win over customers and internal stakeholders</li>\n<li>Ability to work both independently and collaboratively while managing multiple priorities in a fast-paced environment</li>\n<li>Goal-oriented, proactive self-starter with excellent organisational skills</li>\n<li>Strong problem-solving, research, and follow-up skills with both external and internal contacts</li>\n<li>Ability to adapt to the rapid changes typical of a start-up environment</li>\n<li>Advanced PC skills, including proficiency in Microsoft Office, pivot tables, VLOOKUPs, and formulas, with the ability to interpret and analyse data to make recommendations</li>\n<li>German language skills are a plus</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_740c01f3-08d","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Flexport","sameAs":"https://flexport.com","logo":"https://logos.yubhub.co/flexport.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/flexport/jobs/8242629?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":null,"x-job-type":null,"x-salary-range":null,"x-skills-required":["Microsoft Office","pivot tables","VLOOKUPs","data analysis","problem-solving","communication","organisational skills"],"x-skills-preferred":["German language"],"datePosted":"2026-10-02T03:04:54.057Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"occupationalCategory":"Finance","industry":"Logistics","skills":"Microsoft Office, pivot tables, VLOOKUPs, data analysis, problem-solving, communication, organisational skills, German language"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_d87ccdc0-f55"},"title":"Layout Design Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You have spent years translating circuit concepts into physical silicon, and you understand that layout is not just about fitting shapes into a floorplan, it is about making decisions that affect performance, power, and manufacturability at every turn. A well-placed via or carefully routed power rail can mean the difference between a memory cell that works at corner conditions and one that fails in the field.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Design and develop custom layouts for Embedded Memory IPs, Standard Cells, and IO structures using proficiency with Cadence Virtuoso Layout Suite, Synopsys Custom Compiler, and Calibre DRC/LVS verification tools.</li>\n<li>Optimize layout topologies for density, performance, power, and manufacturability across advanced process nodes.</li>\n<li>Collaborate with circuit designers and verification teams to ensure layouts meet electrical and physical design requirements</li>\n<li>Debug and resolve DRC, LVS, and antenna violations in complex hierarchical designs</li>\n<li>Develop and refine layout methodologies and automation flows to improve efficiency across the IP portfolio</li>\n<li>Participate in design reviews and provide technical feedback on layout strategies</li>\n<li>Maintain documentation of layout guidelines, design decisions, and process updates</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Deliver high-performance, high-density memory layouts that enable customers to meet aggressive PPA targets</li>\n<li>Reduce time-to-market for Foundation IP products by improving layout development efficiency</li>\n<li>Enable successful tape-outs by catching and resolving physical design issues early</li>\n<li>Contribute to layout methodology improvements that scale across multiple process nodes. The team develops Foundation IP solutions across multiple advanced technology nodes.</li>\n<li>Support Synopsys&#39; position as the leading provider of silicon-proven Foundation IP</li>\n<li>Help customers achieve first-pass silicon success with layouts that meet manufacturing requirements</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electronics Engineering, Telecommunication, Physics, or related field</li>\n<li>2+ years of hands-on experience in custom IC layout design, with focus on memory compilers, standard cells, or analog/mixed-signal blocks</li>\n<li>Deep understanding of layout fundamentals including device matching, parasitic extraction, electromigration, and IR drop</li>\n<li>Proficiency with industry-standard layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or equivalent</li>\n<li>Solid grasp of DRC/LVS verification flows and ability to debug complex rule violations</li>\n<li>Strong documentation and communication skills for cross-functional collaboration</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</li>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n<li>Competitive salaries.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_d87ccdc0-f55","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/layout-design-sr-engineer/44408/101344394704?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["Cadence Virtuoso Layout Suite","Synopsys Custom Compiler","Calibre DRC/LVS","custom IC layout design","memory compilers","standard cells","analog/mixed-signal blocks"],"x-skills-preferred":[],"datePosted":"2026-10-01T02:24:42.513Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"Cadence Virtuoso Layout Suite, Synopsys Custom Compiler, Calibre DRC/LVS, custom IC layout design, memory compilers, standard cells, analog/mixed-signal blocks"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_0042c469-546"},"title":"ASIC Physical Design, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You are a highly motivated individual with a passion for physical design and implementation of complex Mixed Signal IPs and test chips. With a strong background in physical design, you thrive on solving intricate problems and enjoy collaborating with cross-functional teams. You have a deep understanding of the full design cycle from RTL to GDSII and are adept at using Synopsys tools and methodologies. Your excellent communication skills and problem-solving mindset enable you to convey complex ideas to various stakeholders, deliver robust solutions and mentor others, making you a key contributor to innovative projects.</p>\n<p><strong>What You&#39;ll Be Doing:</strong></p>\n<ul>\n<li>Leading the physical implementation of high-speed interface IPs from RTL to GDS, ensuring timing and physical sign-off.</li>\n<li>Collaborating with cross-functional teams to integrate and verify IP designs to achieve project goals.</li>\n<li>Providing technical guidance and mentorship.</li>\n<li>Continuously improving design methodologies and processes to enhance efficiency and quality.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Driving the development of high-performance physical IP that powers next-generation technologies.</li>\n<li>Ensuring the reliability and efficiency of physical design solutions in our products.</li>\n<li>Contributing to the success of Synopsys&#39; strategic goals through innovative design solutions.</li>\n<li>Sharing technical expertise to elevate team capabilities.</li>\n<li>Fostering a culture of continuous improvement and excellence within the engineering team.</li>\n<li>Supporting the adoption and usability of our products by providing top-tier engineering expertise.</li>\n</ul>\n<p><strong>What You&#39;ll Need:</strong></p>\n<ul>\n<li>BE or MSEE with 2+ years of direct physical design experience.</li>\n<li>Proficiency in full design cycle from RTL to GDSII, with a focus on Physical Design.</li>\n<li>Solid engineering understanding of IC design, implementation flows, and methodologies for deep submicron design.</li>\n<li>Advanced PnR and sign-off skills (STA, PV, EMIR) to validate design robustness.</li>\n<li>Excellent problem-solving abilities and a keen eye for detail.</li>\n</ul>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.</li>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n<li>Competitive salaries.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_0042c469-546","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/asic-physical-design-sr-engineer-in-hcmc-or-da-nang/44408/101338136352?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Physical Design","Mixed Signal IPs","RTL to GDSII","PnR","STA","PV","EMIR"],"x-skills-preferred":[],"datePosted":"2026-10-01T02:22:56.767Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Physical Design, Mixed Signal IPs, RTL to GDSII, PnR, STA, PV, EMIR"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_fcebd8e4-de5"},"title":"ASIC Physical Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You are a highly motivated individual with a passion for physical design and implementation of complex Mixed Signal IPs and test chips. With a strong background in physical design, you thrive on solving intricate problems and enjoy collaborating with cross-functional teams. You have a deep understanding of the full design cycle from RTL to GDSII and are adept at using Synopsys tools and methodologies. Your excellent communication skills and problem-solving mindset enable you to convey complex ideas to various stakeholders, deliver robust solutions and mentor others, making you a key contributor to innovative projects.</p>\n<p><strong>What You&#39;ll Be Doing:</strong></p>\n<ul>\n<li>Leading the physical implementation of high-speed interface IPs from RTL to GDS, ensuring timing and physical sign-off.</li>\n<li>Collaborating with cross-functional teams to integrate and verify IP designs to achieve project goals.</li>\n<li>Providing technical guidance and mentorship.</li>\n<li>Continuously improving design methodologies and processes to enhance efficiency and quality.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Driving the development of high-performance physical IP that powers next-generation technologies.</li>\n<li>Ensuring the reliability and efficiency of physical design solutions in our products.</li>\n<li>Contributing to the success of Synopsys&#39; strategic goals through innovative design solutions.</li>\n<li>Sharing technical expertise to elevate team capabilities.</li>\n<li>Fostering a culture of continuous improvement and excellence within the engineering team.</li>\n<li>Supporting the adoption and usability of our products by providing top-tier engineering expertise.</li>\n</ul>\n<p><strong>What You&#39;ll Need:</strong></p>\n<ul>\n<li>BE or MSEE with 5+ years of direct physical design experience.</li>\n<li>Proficiency in full design cycle from RTL to GDSII, with a focus on Physical Design.</li>\n<li>Solid engineering understanding of IC design, implementation flows, and methodologies for deep submicron design.</li>\n<li>Advanced PnR and sign-off skills (STA, PV, EMIR) to validate design robustness.</li>\n<li>Excellent problem-solving abilities and a keen eye for detail.</li>\n</ul>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.</li>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n<li>Competitive salaries.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_fcebd8e4-de5","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/asic-physical-design-staff-engineer-in-hcmc-or-da-nang/44408/101338136384?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["Physical Design","Mixed Signal IPs","RTL to GDSII","PnR","STA","PV","EMIR"],"x-skills-preferred":[],"datePosted":"2026-10-01T02:22:26.386Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"Physical Design, Mixed Signal IPs, RTL to GDSII, PnR, STA, PV, EMIR"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_d7e7996d-9e9"},"title":"Senior Digital Marketing Specialist","description":"<p>Join Razer&#39;s global team to revolutionize gaming.</p>\n<p>We are seeking a highly motivated and data-driven Senior Digital Marketing Specialist to join our dynamic team in Vietnam.</p>\n<p><strong>Job Responsibilities :</strong></p>\n<ul>\n<li>Develop and execute marketing campaigns across various channels, including user acquisition, brand awareness, community events, and offline events.</li>\n<li>Prepare the marketing budget and define the marketing mix based on CPI and install volume targets.</li>\n<li>Execute performance marketing and user acquisition plans at different stages of a game&#39;s lifecycle.</li>\n<li>Maintain the marketing roadmap for a portfolio of games.</li>\n<li>Manage and optimize digital advertising campaigns across multiple channels.</li>\n<li>Analyze and report on the effectiveness of marketing campaigns and provide recommendations for optimization.</li>\n<li>Oversee the creation of marketing assets.</li>\n<li>Perform competitor marketing execution analysis.</li>\n<li>Measure and report on cohorted campaign performance.</li>\n<li>Scale up social media reach, engagement, and conversion.</li>\n<li>Collaborate with cross-functional teams and external partners.</li>\n</ul>\n<p><strong>Pre-Requisites :</strong></p>\n<ul>\n<li>Bachelor’s degree in marketing, Advertising, or a related field.</li>\n<li>3-5 years of experience in the gaming industry.</li>\n<li>In-depth knowledge of mobile marketing channels.</li>\n<li>Proficiency in digital advertising platforms such as Meta, Google, TikTok, Twitter, and third-party ad networks.</li>\n<li>Experience with performance marketing metrics and optimization.</li>\n<li>Strong analytical skills.</li>\n<li>Ability to thrive in a fast-paced and dynamic environment.</li>\n<li>Passion for gaming and a deep understanding of the mobile gaming industry.</li>\n<li>Based in Ho Chi Minh City.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_d7e7996d-9e9","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Razer","sameAs":"https://razer.com","logo":"https://logos.yubhub.co/razer.com.png"},"x-apply-url":"https://razer.wd3.myworkdayjobs.com/en-US/Careers/job/Ho-Chi-Minh/Senior-Digital-Marketing-Specialist--Gaming-_JR2026007895?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["digital marketing","mobile marketing","performance marketing","data analysis","gaming industry"],"x-skills-preferred":[],"datePosted":"2026-09-28T21:07:06.513Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Marketing","industry":"Technology","skills":"digital marketing, mobile marketing, performance marketing, data analysis, gaming industry"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_58941b72-e1b"},"title":"Sales Manager","description":"<p>As a Sales Manager at Flexport, your goal is to drive growth by closing new business while building and expanding a diversified portfolio of clients.</p>\n<p>You&#39;ll have autonomy in achieving growth goals with continued guidance and coaching to ramp and have long-term success.</p>\n<p>Your day-to-day role will be diverse, with activities such as:</p>\n<ul>\n<li>Leading discovery calls with prospects to uncover information about their supply chain processes</li>\n<li>Discussing onboarding strategies with fellow Flexporters across offices</li>\n<li>Meeting with prospective clients to set up trial projects</li>\n<li>Sharing best practices with the broader sales team in peer learning sessions</li>\n</ul>\n<p>You will:</p>\n<ul>\n<li>Play a key role in driving revenue growth by identifying new business opportunities and managing key accounts</li>\n<li>Help Vietnamese importers and exporters optimize their international logistics operations using Flexport&#39;s platform, services, and global network</li>\n<li>Proactively consult with clients to understand their logistics and supply chain needs through a solutions-based selling approach</li>\n<li>Create value-driven solutions built on deep research and a full understanding of the client&#39;s end-to-end, order-to-cash cycle</li>\n<li>Establish and implement systems, methods, and processes to build scalable commercial capabilities</li>\n<li>Provide insightful market intel and data analysis</li>\n<li>Identify opportunities for account growth by having a thorough understanding of Flexport&#39;s diversified and growing product line while retaining and expanding revenue within the book of business</li>\n<li>Collaborate with Flexport&#39;s client operations teams to identify upsell opportunities, source pipeline, and develop strategic account plans</li>\n</ul>\n<p>You should have:</p>\n<ul>\n<li>5-8 years of experience in commercial and analytics-heavy functions</li>\n<li>Strong understanding of ocean/air freight, customs, and international shipping</li>\n<li>Experience working with clients on key trade lanes (Trans-Pacific, Intra-Asia, Asia-Europe)</li>\n<li>Proven relationship management and project/program/process management skills</li>\n<li>Competitive and creative drive to win over customers and think outside the box to get a deal done</li>\n<li>Demonstrated ability to run a sales discovery and demo meeting and run a structured sales process</li>\n<li>Proven success building and maintaining long-term commercial relationships</li>\n<li>Ability to deliver on a broad portfolio of responsibilities on your own and &#39;figure stuff out&#39; quickly and effectively</li>\n<li>Excellent communication in English (both written and spoken)</li>\n<li>Strong negotiation, presentation, and consultative selling skills</li>\n<li>Self-starter, target-driven, organized, and able to thrive in a fast-paced environment</li>\n<li>Highly effective communicator with good people instincts - able to build trust and work well with a diverse group internally and externally</li>\n<li>Eager for a very hands-on role, where you&#39;ll be asked to take on and run with a range of projects outside your comfort zone, and learn quickly</li>\n<li>Courage to challenge the internal and external status quo when logic and reason require it</li>\n<li>A &#39;compliance first&#39; attitude to keep regulators happy and enthusiastic about Flexport</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_58941b72-e1b","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Flexport","sameAs":"https://flexport.com","logo":"https://logos.yubhub.co/flexport.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/flexport/jobs/8229684?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["international shipping","customs","logistics","sales","relationship management","project management","data analysis","English language"],"x-skills-preferred":[],"datePosted":"2026-09-25T00:04:47.939Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City, Vietnam"}},"employmentType":"FULL_TIME","occupationalCategory":"Sales","industry":"Logistics","skills":"international shipping, customs, logistics, sales, relationship management, project management, data analysis, English language"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e9c1fc2f-928"},"title":"Soc Engineer (Physical Design)","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You are a seasoned SOC Engineering professional with a passion for innovation and problem-solving. With a strong background in Electronics Engineering, Electromechanics, or Telecommunications, you bring hands-on experience in Place &amp; Route domains using advanced tools like Fusion Compiler/ICC2. You have a keen understanding of P&amp;R, extraction, timing, IREM, and Physical Verification fundamentals. Your proficiency in scripting languages such as TCL and PERL, combined with your ability to guide and mentor junior team members, sets you apart.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Developing and implementing SOC design using Synopsys EDA tools and IP, covering all stages from Verilog to GDS.</li>\n<li>Contributing to both turnkey projects and serving as a trusted advisor to customer design and CAD teams.</li>\n<li>Innovating solutions to problems independently, with occasional guidance.</li>\n<li>Setting task-level goals and consistently meeting schedules.</li>\n<li>Collaborating with other Synopsys teams, including BU AE and Sales, to broaden and deploy tool and IP solutions.</li>\n<li>Providing technical guidance and mentorship to junior team members.</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Enhancing the efficiency and effectiveness of SOC design processes.</li>\n<li>Driving innovation in chip design and verification methodologies.</li>\n<li>Ensuring the successful deployment of Synopsys&#39; EDA tools and IP solutions.</li>\n<li>Improving customer satisfaction through expert advisory and technical support.</li>\n<li>Contributing to the development of high-performance silicon chips and software content.</li>\n<li>Supporting the continuous technological advancements at Synopsys.</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>BS/MS/PhD in Electronics Engineering, Electromechanics, or Telecommunications.</li>\n<li>5 to 10 years of hands-on experience in Place &amp; Route domains using Fusion Compiler/ICC2 tool.</li>\n<li>Strong debugging skills and a good understanding of P&amp;R, extraction, timing, IREM, and Physical Verification fundamentals.</li>\n<li>Experience with signoff tools like PT, Redhawk, StarRC, ICV is an advantage.</li>\n<li>Proficiency in TCL/PERL scripting.</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.</li>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n<li>Competitive salaries.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e9c1fc2f-928","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/soc-engineer-physical-design/44408/101064191552?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["Fusion Compiler/ICC2","TCL/PERL scripting","P&R","extraction","timing","IREM","Physical Verification"],"x-skills-preferred":["PT","Redhawk","StarRC","ICV"],"datePosted":"2026-09-24T23:43:28.641Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City, Ho Chi Minh"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"Fusion Compiler/ICC2, TCL/PERL scripting, P&R, extraction, timing, IREM, Physical Verification, PT, Redhawk, StarRC, ICV"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_ad2d00ef-303"},"title":"R&D Engineering, Sr Engineer","description":"<p>Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing.</p>\n<p>You have spent years deep in the physics and trade-offs of embedded memory design, and you understand that a well-designed SRAM bitcell is not just smaller or faster, it is the difference between a chip that ships and one that does not.</p>\n<p><strong>What You&#39;ll Be Doing</strong></p>\n<ul>\n<li>Design and optimize embedded memory circuits including SRAM, ROM, and Register File blocks for advanced process nodes</li>\n<li>Lead bitcell development from concept through characterization, including transistor-level simulation, corner analysis, and reliability validation</li>\n<li>Supervise and collaborate with layout engineers to ensure design intent is maintained through physical implementation</li>\n<li>Work with CAD and compiler teams to integrate memory designs into automated generation flows and verification environments</li>\n<li>Drive yield and performance improvements by analyzing silicon data, identifying failure modes, and iterating on design or test methodologies</li>\n<li>Mentor junior engineers on circuit design techniques, simulation best practices, and design-for-manufacturability principles</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Deliver memory IP that powers semiconductor products across automotive, mobile, AI, and high-performance computing markets</li>\n<li>Improve memory compiler quality and turnaround time by tightening integration between circuit design and automation infrastructure</li>\n<li>Reduce time-to-market for new process nodes by building reusable, well-characterized bitcell libraries and design methodologies</li>\n<li>Strengthen the technical capability of the team by sharing knowledge, reviewing designs, and establishing best practices that scale</li>\n<li>Solve yield and reliability issues that directly affect customer tape-outs and production ramps</li>\n<li>Enable cross-functional teams including verification, product engineering, and applications to resolve complex technical challenges faster</li>\n</ul>\n<p><strong>What You&#39;ll Need</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering, Electronics Engineering, or a related technical discipline</li>\n<li>2+ years of hands-on experience in embedded CMOS memory design, with a focus on SRAM, ROM, or Register File development</li>\n<li>Deep expertise in SRAM bitcell design, including read/write stability analysis, leakage optimization, and statistical variation modeling</li>\n<li>Proficiency with circuit simulation tools such as HSPICE or Spectre, and layout tools for design review and verification</li>\n<li>Strong scripting skills in C-Shell and Perl for automation and data analysis, experience with C++ or JavaScript is a plus</li>\n<li>Fluency in English and Vietnamese for technical communication and collaboration across global teams</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_ad2d00ef-303","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/r-and-d-engineering-sr-engineer/44408/100992953856?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Embedded CMOS memory design","SRAM bitcell design","Circuit simulation tools","Layout tools","Scripting skills in C-Shell and Perl"],"x-skills-preferred":["C++","JavaScript"],"datePosted":"2026-09-22T22:07:11.419Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Embedded CMOS memory design, SRAM bitcell design, Circuit simulation tools, Layout tools, Scripting skills in C-Shell and Perl, C++, JavaScript"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_6c1dceee-500"},"title":"Soc Engineer (synthesis/timing) -18607","description":"<p>We are seeking a SOC engineer to work on ASIC/SOC projects at Synopsys in Ho Chi Minh City, District 7.</p>\n<p>The successful candidate will be responsible for the development and implementation of System Design Solutions using Synopsys EDA tools and IP to solve customer problems as part of a service project team.</p>\n<p><strong>Responsibilities and Duties</strong></p>\n<ul>\n<li>Synthesis</li>\n<li>LEC</li>\n<li>LDRC</li>\n<li>GCA</li>\n<li>STA</li>\n<li>PTPX</li>\n</ul>\n<p>The engineer will contribute to both turnkey projects and act as a trusted advisor to customer design. They will develop innovative solutions to problems with little guidance and implement them independently. The engineer will set task-level goals and consistently meet schedules. They will work with other Synopsys teams, including BU AEs and Sales, to develop, broaden, and deploy Tool and IP solutions.</p>\n<p><strong>Qualifications</strong></p>\n<ul>\n<li>2-4 years of related experience</li>\n<li>Good understanding of ASIC/SOC design, synthesis, and timing closure</li>\n<li>Familiarity with Synthesis, LEC, STA flow</li>\n<li>Experience in low-power, high-performance design, and advanced nodes under 12nm is a plus</li>\n<li>Knowledge of RTL, DFT, LDRC, GCA, VCLP, PTPX, IREM is advantageous</li>\n<li>Familiarity with scripting languages such as TCL, Perl, Python</li>\n<li>Good English communication skills and willingness to work with customers</li>\n<li>BS or MS degree in EE or a related major</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans</li>\n<li>Time away programs, including ETO and FTO</li>\n<li>Family support, including maternity and paternity leave, parenting resources, adoption, and surrogacy assistance</li>\n<li>ESPP: purchase Synopsys common stock at a 15% discount</li>\n<li>Retirement plans that vary by region and country</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_6c1dceee-500","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/soc-engineer-synthesis-timing-18607/44408/100750939712?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC/SOC design","synthesis","timing closure","LEC","STA flow","RTL","DFT","LDRC","GCA","VCLP","PTPX","IREM","TCL","Perl","Python"],"x-skills-preferred":["low-power design","high-performance design","advanced nodes under 12nm"],"datePosted":"2026-09-17T19:06:37.250Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC/SOC design, synthesis, timing closure, LEC, STA flow, RTL, DFT, LDRC, GCA, VCLP, PTPX, IREM, TCL, Perl, Python, low-power design, high-performance design, advanced nodes under 12nm"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_7882a8df-269"},"title":"Analog design, Sr Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You have spent years designing analog circuits that do not just simulate cleanly, they work in silicon, under real conditions, with real noise and real margin pressure. You know that a CTLE that looks perfect in SPICE can still fail in a testchip if you did not account for substrate coupling or layout parasitics, and you are the kind of engineer who catches those issues before tapeout.</p>\n<p>You think in tradeoffs. Power versus speed. Area versus performance. Testability versus complexity. You do not need someone to hand you a perfect spec, you work with system architects and digital teams to figure out what the circuit actually needs to do, then you build it. When layout comes back with a question about metal stack or guard ring placement, you sit down and work through it because you know the circuit does not exist until it is drawn.</p>\n<p>Leading a design block or mentoring a junior engineer is part of how you work. You have done this long enough to know that the best designs come from teams that ask hard questions early. At Synopsys, you will work on high speed mixed signal PHYs that power AI, data center, and 5G applications.</p>\n<p><strong>What You&#39;ll Be Doing</strong></p>\n<ul>\n<li>Design analog circuits for high speed IO blocks (CTLE, FFE, TCOIL, DFE …) PLL, DLL, bandgap references, clock trees, and calibration circuits for UCIe and die-to-die PHY products</li>\n<li>Collaborate with layout engineers to ensure design intent translates into clean layout, then run post-layout verification to confirm performance holds</li>\n<li>Analyze and solve signal integrity, power integrity, noise, and margin issues across complex mixed signal systems</li>\n<li>Work with digital and system engineers to integrate analog blocks into full PHY designs and run mixed signal verification</li>\n<li>Design testchip architectures to validate circuits, then build test cases and run silicon bring-up in the lab to prove the design works in hardware</li>\n<li>Lead design reviews with global teams and mentor junior engineers on circuit design, layout collaboration, and verification</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Your circuits will enable Tbps die-to-die connectivity in next generation AI accelerators, data center processors, and 5G infrastructure</li>\n<li>The design quality and margin you build in will determine whether products meet performance targets in production silicon</li>\n<li>Your collaboration with layout and digital teams will reduce iteration cycles and get products to tapeout faster</li>\n<li>The testchip architectures you create will de-risk new IP and give the business confidence to commit to new product roadmaps</li>\n<li>Your mentorship will build the next generation of analog design capability in the Vietnam engineering team</li>\n<li>Your work in the lab during silicon bring-up will close the loop between design intent and measured results</li>\n</ul>\n<p><strong>What You&#39;ll Need</strong></p>\n<ul>\n<li>BS, MS, or PhD in Electronics Engineering, Electromechanics, or Telecommunications</li>\n<li>8+ years of hands-on experience designing high speed mixed signal PHY circuits with a track record of designs that have taped out and worked in silicon</li>\n<li>3+ years leading design teams, managing projects, or owning full design blocks from spec to silicon</li>\n<li>Deep understanding of analog circuit design fundamentals including noise analysis, signal integrity, power integrity, and layout effects</li>\n<li>Strong English communication skills for presenting design reviews, writing documentation, and collaborating with global teams</li>\n<li>Experience with academic research or publishing is a plus</li>\n</ul>\n<p><strong>Who You Are</strong></p>\n<ul>\n<li>You are a strong team player who pulls the right people together to solve cross-functional problems instead of waiting for someone else to act</li>\n<li>You approach ambiguity with curiosity, asking the right questions when specs are incomplete and moving forward with what you learn</li>\n<li>You have a growth mindset and stay current with new circuit techniques, process nodes, and design tools</li>\n<li>You are easy going and humble, giving credit where it is due and comfortable saying &quot;I don&#39;t know, let me find out&quot;</li>\n</ul>\n<p><strong>The Team You&#39;ll Be Part Of</strong></p>\n<p>You will join the Vietnam analog design team within Synopsys IP, the world&#39;s number one IP provider. This is a highly motivated team working on bleeding edge 2.5D and 3D IC technologies, collaborating daily with experts across the US, Europe, and Asia.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7882a8df-269","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/analog-design-sr-staff-engineer/44408/100768195952?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["analog circuit design","high speed mixed signal PHY circuits","noise analysis","signal integrity","power integrity","layout effects","English communication"],"x-skills-preferred":["academic research","publishing"],"datePosted":"2026-09-17T19:06:17.836Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City, Ho Chi Minh"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"analog circuit design, high speed mixed signal PHY circuits, noise analysis, signal integrity, power integrity, layout effects, English communication, academic research, publishing"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_7a68b8d3-4e9"},"title":"B2B Account Manager – Strategic Verticals","description":"<p>Logitech is seeking a B2B Account Manager – Strategic Verticals to drive growth in Vietnam.</p>\n<p>The role involves developing Logitech&#39;s presence across strategic verticals, winning new customer logos, expanding existing accounts, and building an effective ecosystem of channel partners.</p>\n<p>Key responsibilities:</p>\n<ul>\n<li>Own and grow Logitech&#39;s business across assigned strategic verticals in Vietnam</li>\n<li>Develop vertical sales strategies and strategic account plans</li>\n<li>Drive business growth through direct sales activities and relevant channel partners</li>\n<li>Build and maintain strong relationships with procurement authorities, decision-makers, and customers</li>\n<li>Recruit and develop relevant channel partners</li>\n<li>Understand customer pain points and decision criteria, translating technical product information into relevant value propositions</li>\n<li>Manage the complete sales cycle, including prospecting, qualification, presentations, and closure</li>\n<li>Identify and manage RFP, RFQ, ITQ, and tender opportunities</li>\n<li>Coordinate with various teams to deliver high-quality customer and tender responses</li>\n<li>Maintain accurate account, opportunity, pipeline, and forecast information in Salesforce</li>\n</ul>\n<p>Mandatory eligibility requirements:</p>\n<ul>\n<li>At least 7 years of direct account management experience across multiple verticals, including Public Sector, Banking, Financial Services and Insurance (BFSI), Manufacturing, Education, or Healthcare</li>\n<li>Experience recruiting and working directly with relevant channel partners serving these verticals</li>\n</ul>\n<p>Qualifications and skills:</p>\n<ul>\n<li>Bachelor&#39;s degree</li>\n<li>Proven track record of managing complex sales, tender, and procurement processes</li>\n<li>Experience managing complex accounts and extended sales cycles</li>\n<li>Strong knowledge of the channel ecosystem serving specified verticals</li>\n<li>Familiarity with Unified Communications and Collaboration, Personal Workspace solutions, and enterprise-grade hardware, software, or cloud services</li>\n<li>Proficiency in Salesforce (SFDC)</li>\n<li>Strong communication, presentation, negotiation, influencing, and closing skills</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7a68b8d3-4e9","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Logitech","sameAs":"https://logitech.com","logo":"https://logos.yubhub.co/logitech.com.png"},"x-apply-url":"https://logitech.wd5.myworkdayjobs.com/en-US/Logitech/job/Ho-Chi-Minh-City-Vietnam/B2B-Account-Manager---Strategic-Verticals_148161?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["account management","sales strategy","channel partner development","Unified Communications and Collaboration","Personal Workspace solutions","Salesforce"],"x-skills-preferred":[],"datePosted":"2026-09-11T12:05:54.547Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City, Vietnam"}},"employmentType":"FULL_TIME","occupationalCategory":"Sales","industry":"Technology","skills":"account management, sales strategy, channel partner development, Unified Communications and Collaboration, Personal Workspace solutions, Salesforce"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_569e3716-83a"},"title":"Senior Software Development Engineer in Test - SDET","description":"<p>NVIDIA is seeking a Senior Software Development Engineer in Test - SDET to collaborate with multi-functional groups. As a Software QA Development Engineer at NVIDIA, you will be responsible for test planning, execution, and reporting. You will also write scripts to automate testing, design and develop tools for the QA team, and develop integration tests for validation.</p>\n<p><strong>Responsibilities:</strong></p>\n<ul>\n<li>Review product requirements and develop test matrix.</li>\n<li>Build test plans, design test cases, execute and report test progress, bugs, and results to management.</li>\n<li>Automate test cases and assist in the architecture, crafting, and implementing of test frameworks.</li>\n<li>Manage bug lifecycle and co-work with inter-groups to drive for solutions.</li>\n<li>In-house repro and verify customer issues/fixes.</li>\n</ul>\n<p><strong>Requirements:</strong></p>\n<ul>\n<li>BS or higher degree or equivalent experience in CS/EE/CE plus equivalent with 5+ years QA experience.</li>\n<li>Proficient in Unix/Linux and shell/python programming skills.</li>\n<li>Rich experience in test cases development, tests automation in API/UI, and failure analysis.</li>\n<li>Solid experience with AI development tools, including creating test cases, automating test cases, and ensuring comprehensive code coverage.</li>\n<li>Good knowledge and hands-on experience in model testing and LLM benchmarking.</li>\n<li>Good QA sense including attention to detail, problem-solving, data analysis, quality standards knowledge, time management, etc.</li>\n<li>Excellent communicator, fluent written and verbal English.</li>\n<li>Good teamwork with ability to work independently.</li>\n</ul>\n<p><strong>Preferred Qualifications:</strong></p>\n<ul>\n<li>Experience working with NVIDIA GPU hardware is a strong plus.</li>\n<li>Background in deep learning frameworks is a plus.</li>\n<li>Experience in parallel programming ideally CUDA/OpenCL is a plus.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_569e3716-83a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"NVIDIA","sameAs":"https://www.nvidia.com","logo":"https://logos.yubhub.co/nvidia.com.png"},"x-apply-url":"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Vietnam-Ho-Chi-Minh-City/Senior-Software-Development-Engineer-in-Test---SDET_JR2024404-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Unix/Linux","shell programming","python programming","test cases development","tests automation","API/UI","failure analysis","AI development tools","model testing","LLM benchmarking","problem-solving","data analysis","quality standards knowledge","time management"],"x-skills-preferred":["NVIDIA GPU hardware","deep learning frameworks","parallel programming","CUDA/OpenCL"],"datePosted":"2026-09-04T08:04:53.042Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Unix/Linux, shell programming, python programming, test cases development, tests automation, API/UI, failure analysis, AI development tools, model testing, LLM benchmarking, problem-solving, data analysis, quality standards knowledge, time management, NVIDIA GPU hardware, deep learning frameworks, parallel programming, CUDA/OpenCL"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e9f3c1ee-337"},"title":"Senior SWQA Test Developer Engineer, SDET","description":"<p>NVIDIA is seeking a Senior Software QA Test Developer Engineer to collaborate with multi-functional groups. As a Senior SWQA Test Developer Engineer at NVIDIA, you will be responsible for test planning, execution, and reporting. You will also write scripts to automate testing, design and develop tools for the QA team, and develop integration tests for validation.</p>\n<p><strong>Responsibilities:</strong></p>\n<ul>\n<li>Review product requirements and develop test matrix.</li>\n<li>Build test plans, design test cases, execute and report test progress, bugs, and results to management.</li>\n<li>Automate test cases and assist in the architecture, crafting, and implementing of test frameworks.</li>\n<li>Manage bug lifecycle and co-work with inter-groups to drive for solutions.</li>\n<li>In-house repro and verify customer issues/fixes.</li>\n</ul>\n<p><strong>Requirements:</strong></p>\n<ul>\n<li>BS or higher degree or equivalent experience in CS/EE/CE plus equivalent with 5+ years QA experience.</li>\n<li>Proficient in Unix/Linux and shell/python programming skills.</li>\n<li>Rich experience in test cases development, tests automation in API/UI and failure analysis.</li>\n<li>Solid experience with AI development tools, including creating test cases, automating test cases, and ensuring comprehensive code coverage.</li>\n<li>Good knowledge and hands-on experience in model testing and LLM benchmarking.</li>\n<li>Good QA sense including attention to detail, problem-solving, data analysis, quality standards knowledge, time management etc.</li>\n<li>Excellent communicator, fluent written and verbal English.</li>\n<li>Good teamwork with ability to work independently.</li>\n</ul>\n<p><strong>Preferred Qualifications:</strong></p>\n<ul>\n<li>Experience working with NVIDIA GPU hardware is a strong plus.</li>\n<li>Background in deep learning frameworks is a plus.</li>\n<li>Experience in parallel programming ideally CUDA/OpenCL is a plus.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e9f3c1ee-337","directApply":true,"hiringOrganization":{"@type":"Organization","name":"NVIDIA","sameAs":"https://www.nvidia.com","logo":"https://logos.yubhub.co/nvidia.com.png"},"x-apply-url":"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Vietnam-Ho-Chi-Minh-City/Senior-SWQA-Test-Developer-Engineer--SDET_JR2024507?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Unix/Linux","shell programming","python programming","test cases development","tests automation","API/UI","failure analysis","AI development tools","model testing","LLM benchmarking","problem-solving","data analysis","quality standards"],"x-skills-preferred":["NVIDIA GPU hardware","deep learning frameworks","parallel programming","CUDA/OpenCL"],"datePosted":"2026-08-29T03:52:58.147Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Unix/Linux, shell programming, python programming, test cases development, tests automation, API/UI, failure analysis, AI development tools, model testing, LLM benchmarking, problem-solving, data analysis, quality standards, NVIDIA GPU hardware, deep learning frameworks, parallel programming, CUDA/OpenCL"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c9316ae2-70d"},"title":"Artist & Label Partnerships Contractor","description":"<p>Spotify is seeking a short-term contractor for the Artist &amp; Label Partnerships team in Vietnam. The successful candidate will serve as the primary point of contact for record labels, distributors, and artists, ensuring they are familiar with Spotify&#39;s standard methodologies, resources, and tools.</p>\n<p>The role involves maintaining positive partnerships across the artist and label communities in Vietnam, supporting key partners on Spotify tools and insights, and collaborating with cross-functional teams to promote artists and labels.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Maintain positive partnerships across artist and label communities within Vietnam.</li>\n<li>Support key partners in Vietnam on Spotify tools, resources, and insights.</li>\n<li>Work closely with cross-functional teams to support artists and labels on priority releases in Vietnam.</li>\n<li>Collaborate with the regional Music team to ensure content strategies are localized and successfully executed.</li>\n<li>Ensure Spotify has the best possible content offering in Vietnam to further its appeal to existing and new users.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>At least 3+ years of working experience in the music/entertainment industry.</li>\n<li>Extremely well-organized, dedicated, with the ability to plan, deliver on tight deadlines, and pay outstanding attention to detail.</li>\n<li>Deep understanding and established network within the local music industry in Vietnam.</li>\n<li>Strong background in music and technology.</li>\n<li>Excellent stakeholder management skills.</li>\n<li>Fluency in written and spoken English and Vietnamese.</li>\n</ul>\n<p>Location: Ho Chi Minh City, Vietnam.</p>\n<p>This is a fixed-term, 6-month contractor role.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c9316ae2-70d","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Spotify","sameAs":"https://www.spotify.com","logo":"https://logos.yubhub.co/spotify.com.png"},"x-apply-url":"https://jobs.lever.co/spotify/d87833d0-fb78-4794-b45d-3fe5c8274bc8?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"contract","x-salary-range":null,"x-skills-required":["music industry","entertainment","Spotify tools","stakeholder management","English","Vietnamese"],"x-skills-preferred":["regional and global experience","content strategies","music and technology"],"datePosted":"2026-08-28T05:16:39.971Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"CONTRACTOR","occupationalCategory":"Other","industry":"Technology","skills":"music industry, entertainment, Spotify tools, stakeholder management, English, Vietnamese, regional and global experience, content strategies, music and technology"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_91dad886-5fc"},"title":"Physical Design Engineer (Senior/Staff) in District 7","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You have spent years in physical design where routing decisions determine whether a chip tapes out clean or burns weeks in ECO. You know Fusion Compiler or ICC2 from debugging congestion hotspots and timing violations at 2am, not from training slides. P&amp;R is equal parts science and pattern recognition, and you have developed both.</p>\n<p>You do not wait for a perfect floorplan. You flag what will break and propose something workable before it becomes a schedule problem. When extraction results look wrong, you dig until you understand why. The best solutions often come from walking to the frontend team and asking the right question.</p>\n<p>Mentorship matters to you. You remember staring at a million DRC violations as a junior engineer, so you take time to show someone how to read a timing report or why their power grid will not close. You script your way out of repetitive work in TCL or PERL, and you know when automation helps versus when manual is faster.</p>\n<p>At Synopsys, you will work on real SOC designs using the tools the industry depends on. The problems are hard, the work is real, and what you build will matter.</p>\n<p><strong>What You&#39;ll Be Doing</strong></p>\n<ul>\n<li>Own physical implementation using Fusion Compiler or ICC2, from floorplanning through routing and signoff closure</li>\n<li>Debug complex P&amp;R issues including timing, congestion, IR drop, and physical verification failures across hierarchical designs</li>\n<li>Guide customer design and CAD teams on tool usage, methodology, and design closure as a trusted technical advisor</li>\n<li>Develop physical design flows and automation scripts in TCL, PERL, or Python to improve efficiency</li>\n<li>Work with Synopsys BU and Sales teams to deploy tool and IP solutions that solve real customer problems</li>\n<li>Mentor junior engineers on P&amp;R fundamentals, debugging techniques, and tool best practices</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Accelerate customer tapeout schedules by solving physical design bottlenecks that would otherwise cause weeks of delay</li>\n<li>Improve Synopsys physical design methodologies through real-world deployment and customer feedback</li>\n<li>Enable successful Fusion Compiler and ICC2 adoption across customer teams, directly influencing tool ROI</li>\n<li>Reduce design respins by catching physical implementation problems early in the flow</li>\n<li>Build long-term team capability by elevating junior engineer skills and reducing external support dependency</li>\n<li>Shape EDA tool development by surfacing customer pain points that matter</li>\n<li>Contribute to silicon products powering AI, automotive, mobile, and data center applications worldwide</li>\n</ul>\n<p><strong>What You&#39;ll Need</strong></p>\n<ul>\n<li>Bachelor&#39;s, Master&#39;s, or PhD in Electronics Engineering, Electromechanics, Telecommunications, or equivalent</li>\n<li>3 to 6+ years hands-on Place and Route experience using Fusion Compiler or ICC2 on complex SOC or ASIC designs</li>\n<li>Strong knowledge of P&amp;R, extraction, static timing analysis, IR drop, and physical verification fundamentals</li>\n<li>Proficiency in TCL, PERL, or Python scripting for automation and flow development</li>\n<li>Solid debugging skills to trace root causes across timing, power, signal integrity, and DRC/LVS domains</li>\n<li>Experience with signoff tools like PrimeTime, Redhawk, StarRC, or ICV is a plus</li>\n<li>Effective English communication skills for customer-facing and cross-functional work</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_91dad886-5fc","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/physical-design-engineer-senior-staff-in-district-7/44408/98736242784?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Fusion Compiler","ICC2","Place and Route","TCL","PERL","Python","Static Timing Analysis","IR Drop","Physical Verification"],"x-skills-preferred":["PrimeTime","Redhawk","StarRC","ICV"],"datePosted":"2026-08-04T21:29:06.883Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Fusion Compiler, ICC2, Place and Route, TCL, PERL, Python, Static Timing Analysis, IR Drop, Physical Verification, PrimeTime, Redhawk, StarRC, ICV"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_a9596e5b-11a"},"title":"Site Reliability Senior Staff","description":"<p>Synopsys is expanding its Synopsys.ai alongside traditional EDA engineering compute for semiconductor customers in Vietnam. We are looking for an experienced Unix/Linux infrastructure professional to keep these platforms reliable, secure, and operable in Synopsys sites and at major customer environments.</p>\n<p>You will join the regional EDA Engineering Compute / platform operations team working with global IT, AE engineering, and product teams. Your work directly enables R&amp;D and customer engineering teams to run EDA and GenAI workloads,from HPC batch grids through containerized AI gateways, vector data services, and agent/MCP-based tool execution on the grid.</p>\n<p>The successful candidate will support Synopsys Vietnam engineering compute and data center services, and partner on in-country deployment and sustainment of the related platform components for key semiconductor accounts.</p>\n<p><strong>Responsibilities</strong></p>\n<p><strong>Engineering Compute and Data Center</strong></p>\n<ul>\n<li>Maintain Synopsys Vietnam engineering compute and data center environments per corporate IT, data center, and security standards.</li>\n<li>Support server hardware lifecycle activities: installation, provisioning, maintenance, upgrade planning, retirement, and decommissioning.</li>\n<li>Perform capacity planning, performance troubleshooting, and vendor/customer coordination at customer sites.</li>\n<li>Operate and troubleshoot Linux-based EDA compute: virtualization, engineering resource management, job schedulers, license connectivity, and remote access services.</li>\n<li>Run HPC operations: cluster health, scheduler integration (LSF, Slurm, or similar), InfiniBand where deployed, and performance-related incidents.</li>\n<li>Collaborate with corporate network and information security on data center connectivity, switching, firewalls, routing, and circuits.</li>\n</ul>\n<p><strong>Synopsys.ai Platform Operations</strong></p>\n<ul>\n<li>Support deployment and day-2 operations for Synopsys EDA and AI reference patterns in Vietnam: customer-hosted and air-gapped container environments, API/AI gateways, LLM gateway integration (cloud or on-prem inference endpoints per customer policy), and customer-controlled vector database/GPU compute where applicable.</li>\n<li>Partner on install, upgrade, and configuration of platform components that connect user/agent workflows to the engineering grid,e.g., job services, unified MCP server patterns, and tool execution on LSF/Slurm-backed clusters (in coordination with products and global platform teams).</li>\n<li>Implement and maintain observability, alerting, authentication/authorization integration (e.g., customer IdP, OIDC/SSO/OAuth patterns), and operational documentation for platform services.</li>\n<li>Support agentic AI platform rollouts where components run locally, centrally, or on the grid; escalate design questions to global architecture and engineering teams.</li>\n</ul>\n<p><strong>Reliability, Improvement, and Customer Engagement</strong></p>\n<ul>\n<li>Own or co-own runbooks, monitoring/alerting policies, and automation (scripts, IaC, or equivalent) to reduce toil across the APAC team.</li>\n<li>Apply AI-assisted workflows to improve troubleshooting, knowledge management, and routine operations.</li>\n<li>On-call and incident response: shared rotation (weekday nights, weekends, and holidays); lead or support incident bridges; produce post-incident reports in English.</li>\n<li>Customer air-gapped and on-site support: planned upgrades, break-fix, and customer training for isolated HPC and on-prem AI sites. Travel within Vietnam and APAC as needed (typically 10–20% of time).</li>\n<li>Cross-regional collaboration: handoffs, documentation, and mentor junior staff where applicable.</li>\n</ul>\n<p><strong>Required Skills and Experience</strong></p>\n<p><strong>Technical</strong></p>\n<ul>\n<li>5+ years in Linux system administration, infrastructure engineering, or production network/storage support.</li>\n<li>Enterprise data center experience: servers, storage, networking, monitoring, and operational processes.</li>\n<li>HPC or EDA engineering compute: Linux clusters, workload schedulers (LSF, Slurm, or similar), and production support.</li>\n<li>Ability to support GPU-enabled compute and containerized platform services in customer-controlled environments.</li>\n<li>Familiarity with virtualization, remote access, observability stacks, and infrastructure automation.</li>\n<li>Understanding of secure multi-tier deployments: gateways, service-to-service auth, and operational telemetry (logs, metrics, tracing) for distributed platform components.</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family.</li>\n<li>In addition to company holidays, we have ETO and FTO Programs.</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.</li>\n<li>Save for your future with our retirement plans that vary by region and country.</li>\n<li>Competitive salaries.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_a9596e5b-11a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/site-reliability-senior-staff/44408/98572441664?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Linux system administration","infrastructure engineering","production network/storage support","Enterprise data center experience","HPC or EDA engineering compute","Linux clusters","workload schedulers","GPU-enabled compute","containerized platform services","virtualization","remote access","observability stacks","infrastructure automation"],"x-skills-preferred":[],"datePosted":"2026-07-31T21:22:22.166Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City, Ho Chi Minh"}},"employmentType":"FULL_TIME","occupationalCategory":"IT","industry":"Technology","skills":"Linux system administration, infrastructure engineering, production network/storage support, Enterprise data center experience, HPC or EDA engineering compute, Linux clusters, workload schedulers, GPU-enabled compute, containerized platform services, virtualization, remote access, observability stacks, infrastructure automation"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_353ffc0e-ea6"},"title":"ASIC Physical Design, Principal Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>As a Principal Engineer in ASIC Physical Design, you will lead the physical implementation of high-speed interface IPs from RTL to GDS, ensuring timing and physical sign-off. You will collaborate with cross-functional teams to integrate and verify IP designs to achieve project goals. You will also provide technical guidance and mentorship, continuously improving design methodologies and processes to enhance efficiency and quality.</p>\n<p>The impact you will have is driving the development of high-performance physical IP that powers next-generation technologies, ensuring the reliability and efficiency of physical design solutions in our products, contributing to the success of Synopsys&#39; strategic goals through innovative design solutions, sharing technical expertise to elevate team capabilities, fostering a culture of continuous improvement and excellence within the engineering team, and supporting the adoption and usability of our products by providing top-tier engineering expertise.</p>\n<p>What you&#39;ll need is a BE or MSEE with 10+ years of direct physical design experience, proficiency in full design cycle from RTL to GDSII, solid engineering understanding of IC design, implementation flows, and methodologies for deep submicron design, advanced PnR and sign-off skills (STA, PV, EMIR) to validate design robustness, excellent problem-solving abilities and a keen eye for detail.</p>\n<p>You will be part of the Synopsys Mixed-Signal IP organization, a team dedicated to the physical implementation of complex Mixed Signal IPs and test chips. This team collaborates closely with multiple functional groups including front-end, analog, CAD, and product teams to deliver high-quality design solutions that meet the unique performance, power, and size requirements of our customers&#39; applications.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_353ffc0e-ea6","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/asic-physical-design-principal-engineer-in-tan-binh-district-hcmc-or-da-nang/44408/91117302576?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Physical Design","RTL to GDSII","IC Design","Implementation Flows","Methodologies for Deep Submicron Design","PnR and Sign-off Skills (STA, PV, EMIR)","Problem-Solving Abilities","Keen Eye for Detail"],"x-skills-preferred":[],"datePosted":"2026-05-29T08:07:37.091Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Physical Design, RTL to GDSII, IC Design, Implementation Flows, Methodologies for Deep Submicron Design, PnR and Sign-off Skills (STA, PV, EMIR), Problem-Solving Abilities, Keen Eye for Detail"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_89a82cda-38e"},"title":"ASIC Physical Design, Sr Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are seeking a highly motivated individual with a passion for physical design and implementation of complex Mixed Signal IPs and test chips. With a strong background in physical design, you thrive on solving intricate problems and enjoy collaborating with cross-functional teams. You have a deep understanding of the full design cycle from RTL to GDSII and are adept at using Synopsys tools and methodologies. Your excellent communication skills and problem-solving mindset enable you to convey complex ideas to various stakeholders, deliver robust solutions and mentor others, making you a key contributor to innovative projects.</p>\n<p>As a Sr Staff Engineer, you will lead the physical implementation of high-speed interface IPs from RTL to GDS, ensuring timing and physical sign-off. You will collaborate with cross-functional teams to integrate and verify IP designs to achieve project goals. You will also provide technical guidance and mentorship, continuously improving design methodologies and processes to enhance efficiency and quality.</p>\n<p>The impact you will have is driving the development of high-performance physical IP that powers next-generation technologies, ensuring the reliability and efficiency of physical design solutions in our products, contributing to the success of Synopsys&#39; strategic goals through innovative design solutions, sharing technical expertise to elevate team capabilities, fostering a culture of continuous improvement and excellence within the engineering team, and supporting the adoption and usability of our products by providing top-tier engineering expertise.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_89a82cda-38e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/asic-physical-design-sr-staff-engineer-in-hcmc-or-da-nang/44408/94030515824?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Physical Design","Mixed Signal IPs","Test Chips","RTL to GDSII","Synopsys Tools and Methodologies"],"x-skills-preferred":["Chip Architecture","Circuit Design","Verification","Problem-Solving","Communication"],"datePosted":"2026-04-24T14:11:10.554Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Physical Design, Mixed Signal IPs, Test Chips, RTL to GDSII, Synopsys Tools and Methodologies, Chip Architecture, Circuit Design, Verification, Problem-Solving, Communication"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_989e07eb-cc7"},"title":"Soc Engineer (synthesis/timing)","description":"<p>Opening. Our team is looking for a SOC engineer to work on ASIC/SOC projects in Synopsys Ho Chi Minh City, District 7.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Responsible for the development and implementation of System Design Solutions using Synopsys EDA tools and IP to solve customer problems as part of a service project team. Contributes to both turnkey projects and as a trusted advisor to customer design. Develop innovative solutions to problems with little guidance and implement them independently. Set task-level goals and consistently meet schedules. Works with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tool and IP solutions.</p>\n<ul>\n<li>Synthesis</li>\n<li>LEC</li>\n<li>LDRC</li>\n<li>GCA</li>\n<li>STA</li>\n<li>PTPX</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>6-12 years of related experience.</li>\n<li>Good of ASIC/SOC design, synthesis, timing closure.</li>\n<li>Familiar with Synthesis, LEC, STA flow.</li>\n<li>It’s a plus if you have experience in low-power, high-performance design, advanced nodes under 12nm.</li>\n<li>Knowledge of RTL, DFT, LDRC, GCA, VCLP, PTPX, IREM is advantageous.</li>\n<li>Familiar with scripting languages, such as TCL, Perl, Python.</li>\n<li>Good English/communication skills and willingness to work with customer.</li>\n<li>BS or MS with an EE or related major</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_989e07eb-cc7","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/soc-engineer-synthesis-timing/44408/92181994832?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["Synthesis","LEC","STA","PTPX"],"x-skills-preferred":["low-power","high-performance design","advanced nodes under 12nm","RTL","DFT","LDRC","GCA","VCLP","IREM","TCL","Perl","Python"],"datePosted":"2026-03-04T17:09:47.992Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"Synthesis, LEC, STA, PTPX, low-power, high-performance design, advanced nodes under 12nm, RTL, DFT, LDRC, GCA, VCLP, IREM, TCL, Perl, Python"}]}