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Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.</p>\n<p>You have spent 10+ years keeping compute infrastructure running for engineers who need it to just work, not sort of work, actually work when they are pushing a deadline or running a critical simulation at 2 a.m. You know that the difference between a good HPC environment and one that slows down a product launch is usually a decision about job scheduling, storage latency, or cloud bursting made six weeks earlier, and you are the kind of engineer who sees that coming and fixes it before anyone files a ticket.</p>\n<p>You will work with engineering teams building the tools that design the chips that power everything. The compute environments you manage are not back-office infrastructure. They are the platform that makes the work possible.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Enable engineering teams across Synopsys IPG to use on-premises and cloud compute environments for design, verification, and simulation workloads</li>\n<li>Translate requirements from business, engineering, cybersecurity, and data governance stakeholders into a technical roadmap and execute on it</li>\n<li>Manage and optimize job scheduler environments including LSF, UGE, or Slurm across large-scale HPC systems</li>\n<li>Support and troubleshoot Linux/UNIX systems in production, ensuring uptime and performance for engineering workflows</li>\n<li>Build and maintain DevOps automation using Python and other scripting languages to improve reliability and reduce manual toil</li>\n<li>Coordinate with IT, R&amp;D, and infrastructure teams to align compute strategy, resolve issues, and deliver on engineering needs</li>\n<li>Manage cloud compute operations across GCP, AWS, or Azure, including cost optimization, security compliance, and hybrid cloud integration</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Engineering teams will have reliable, performant compute environments that let them focus on their work instead of fighting infrastructure</li>\n<li>The roadmap you build will shape how Synopsys scales compute capacity for next-generation IP and EDA development</li>\n<li>Your automation and scripting will reduce manual operations overhead and improve system reliability across the HPC environment</li>\n<li>R&amp;D teams will be able to burst to cloud when needed without waiting weeks for approvals or configurations</li>\n<li>Your coordination across IT, security, and engineering will prevent bottlenecks and misaligned priorities before they slow down product timelines</li>\n<li>The job scheduler optimizations you implement will improve throughput and reduce queue wait times for critical engineering runs</li>\n<li>Your deep technical knowledge will make you the go-to resource when something breaks and needs to be fixed fast</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Deep hands-on experience with Linux/UNIX system administration in production environments</li>\n<li>Proven experience managing and optimizing job schedulers such as LSF, UGE, or Slurm in large-scale HPC or engineering compute environments</li>\n<li>Strong scripting and automation skills, particularly in Python</li>\n<li>Experience supporting engineering teams using cloud platforms like GCP, AWS, or Azure</li>\n<li>Background in DevOps practices, tooling, and workflows</li>\n<li>Ability to translate technical, business, and security requirements into actionable roadmaps and coordinate across multiple stakeholder groups</li>\n<li>Experience managing HPC systems in large compute data centers is a strong plus</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family</li>\n<li>Time away programs including ETO and FTO</li>\n<li>Family support including maternity and paternity leave, parenting resources, adoption and surrogacy assistance</li>\n<li>ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back</li>\n<li>Retirement plans that vary by region and country</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_a74a86d3-002","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hillsboro/r-and-d-engineering-principal-engineer/44408/102223400864?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$166000-$249000","x-skills-required":["Linux","UNIX","Python","LSF","UGE","Slurm","DevOps","GCP","AWS","Azure"],"x-skills-preferred":[],"datePosted":"2026-10-21T11:06:27.203Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hillsboro, Oregon"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Linux, UNIX, Python, LSF, UGE, Slurm, DevOps, GCP, AWS, Azure","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":166000,"maxValue":249000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e14346b8-613"},"title":"Physical Therapist","description":"<p>We are seeking a Physical Therapist to join our team at ATI, a leader in Outpatient Physical Therapy. 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As a leader in engineering solutions, we enable customers to rapidly innovate AI-powered products. You will work on the hardest physical design problems in the industry, on the most advanced nodes, with customers who are building the chips that power everything.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Support customer engagements on advanced-node designs at 7nm, 5nm, and below using Synopsys physical design tools including Fusion Compiler, helping them hit PPA targets under real schedule and resource constraints</li>\n<li>Develop and enhance physical design methodologies and automation solutions using TCL, Python, and Perl to improve design quality, predictability, and team efficiency across the RTL-to-GDS flow</li>\n<li>Debug complex physical design challenges including placement, clock tree synthesis, routing, timing closure, and power optimization on FinFET designs with multi-patterning and electromigration constraints</li>\n<li>Build and deliver methodology recommendations tailored to customer design constraints, process technologies, and project timelines, not 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dozens of designs</li>\n<li>Shape the roadmap of Synopsys physical design tools by feeding real customer challenges directly into R&amp;D, influencing features that thousands of engineers will use</li>\n<li>Reduce design cycle time and improve PPA outcomes for customers working at the cutting edge of semiconductor technology, where every percentage point of performance or power matters</li>\n<li>Mentor field teams and customers on advanced physical design techniques, raising the bar for how complex designs get implemented across the industry</li>\n<li>Help drive adoption of AI-driven optimization methodologies that change how physical design gets done, not just incrementally but fundamentally</li>\n<li>Strengthen customer relationships by being the engineer they call when a design is stuck and they need someone who can actually solve the problem, not just escalate it</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>Bachelor&#39;s degree in electrical engineering or a related field with 5+ years of hands-on ASIC physical design experience, or a master&#39;s degree with 3+ years of experience</li>\n<li>Proficiency with industry-standard implementation tools such as Synopsys ICC2, Fusion Compiler, or Cadence Innovus, you have used these tools on real tapeouts, not just in training</li>\n<li>Strong scripting and automation skills using TCL, Python, or Perl to build flows, analyze data, and solve problems that do not have a button in the GUI</li>\n<li>Solid understanding of advanced-node design challenges at 7nm and below, including FinFET effects, multi-patterning, electromigration, and the tradeoffs that come with each</li>\n<li>Experience with logical and physical synthesis flows, and familiarity with AI-driven optimization methodologies is a strong plus</li>\n<li>Excellent communication and presentation skills, you can explain a complex timing closure strategy to a customer engineering team and a high-level roadblock to their management in the same meeting</li>\n<li>Willingness to travel to customer sites as needed, sometimes on short notice, to provide onsite support during critical design phases</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_a9e79350-5d4","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hillsboro/physical-design-staff-application-engineer/44408/101580799888?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"staff","x-job-type":"full-time","x-salary-range":"$112000-$168000","x-skills-required":["physical design","ASIC design","Fusion Compiler","TCL","Python","Perl","AI-driven optimization"],"x-skills-preferred":["Cadence Innovus","logical and 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As a Post-Silicon Validation, Principal Engineer, you will define how Synopsys validates UCIe die-to-die IP, own the silicon sign-off decision, and be the technical authority customers call when their multi-die product is stuck.</p>\n<p>You have spent a decade or more bringing silicon to life, and you know that the hardest problems do not show up in simulation. They show up in a customer&#39;s lab when the link will not train and nobody can explain why. You are the person who can connect observations across the analog, digital, protocol, package, and system domains, identify the most likely failure mechanisms, and drive the investigation to a defensible conclusion.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Define the post-silicon validation and characterization strategy for UCIe-based die-to-die interface IP, including the methodology, coverage models, and sign-off criteria that determine whether silicon is ready to ship</li>\n<li>Act as the final technical escalation point for silicon issues where root cause is not evident from the data, requiring you to evaluate intangibles across analog circuit behavior, package and interposer channel effects, link training firmware, protocol layer state machines, and system integration constraints</li>\n<li>Lead the bring up and debug of customer silicon, working remotely or sometimes on-site in customer labs to resolve sideband and mainband link training failures, lane repair and reversal issues, degraded mode operation, and chiplet interoperability problems</li>\n<li>Own the architecture and technical direction of the validation software platform in Python, including lab automation frameworks, data infrastructure, measurement correlation engines, and the instrumentation the organization depends on</li>\n<li>Establish how die-to-die links are characterized when direct probe access is limited or unavailable, defining the use of on-die instrumentation, eye margining techniques, built-in monitors, and the correlation of that data back to bench measurements and simulation results</li>\n<li>Drive validation programs that span multiple related areas of the business, coordinating across analog design, digital design, firmware, product engineering, applications, and marketing to reach shared technical outcomes and silicon readiness milestones</li>\n<li>Represent Synopsys in technical engagements with major customers and, where appropriate, in industry and standards forums such as the UCIe Consortium</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Resolve the class of silicon problems that would otherwise stall a program or delay a customer&#39;s multi-die product launch, directly affecting time-to-market and revenue outcomes</li>\n<li>Raise the technical capability of the entire validation discipline through the methodology, tooling, and measurement standards you establish and the engineers you coach</li>\n<li>Shape how the organization and industry approaches validation of next-generation UCIe data rates, packaging technologies, and chiplet topologies before those problems arrive, influencing roadmap and design decisions upstream</li>\n<li>Deliver measurable impact on department targets including sign-off schedules, silicon respin avoidance, and the speed at which new IP reaches production readiness</li>\n<li>Establish Synopsys as the credible technical partner customers turn to when their silicon does not work, strengthening customer relationships and competitive positioning</li>\n<li>Feed silicon reality back into the design process, influencing architecture, circuit design, and packaging strategy with data that only post-silicon validation can provide</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>Bachelor&#39;s degree in Electrical Engineering or Computer Engineering with a minimum of 10 years of related experience, or an advanced degree with a minimum of 8 years of related experience</li>\n<li>Extensive expertise in post-silicon validation, characterization, and debug of high-speed mixed-signal interface IP across multiple silicon generations and process nodes</li>\n<li>Authoritative command of the UCIe specification, including the PHY and D2D adapter layers, link initialization and training, sideband operation, lane repair and reversal, and the tradeoffs between standard and advanced packaging; direct UCIe or other die-to-die interface experience is strongly preferred, and deep high-speed SerDes experience is applicable</li>\n<li>Recognized depth in high-speed link analysis, including equalization, jitter decomposition, crosstalk, and package, interposer, and substrate channel behavior, grounded in signals and systems concepts and transmission line theory</li>\n<li>Advanced software architecture capability across multiple languages including Python, with experience building large-scale lab automation frameworks, data infrastructure, and measurement correlation systems</li>\n<li>Expert-level command of high-speed oscilloscopes, BERTs, spectrum analyzers, and network analyzers, including understanding the limits of the instruments themselves and how to validate links that cannot be directly probed</li>\n<li>Demonstrated success leading customer silicon bring up and debug engagements, working in customer lab environments and owning the technical relationship with external engineering teams; experience with software version control systems such as GitLab and with issue and task tracking through Jira and Confluence is a plus</li>\n</ul>\n<p><strong>Benefits</strong> We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_030d78b7-e1f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hillsboro/post-silicon-validation-principal-engineer/44408/101617800480?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$151000-$227000","x-skills-required":["post-silicon validation","characterization","debug of high-speed mixed-signal interface IP","UCIe specification","high-speed link analysis","Python","lab automation frameworks","data infrastructure","measurement correlation systems","high-speed oscilloscopes","BERTs","spectrum analyzers","network analyzers"],"x-skills-preferred":["direct UCIe or other die-to-die interface experience","deep high-speed SerDes experience","software version control systems such as GitLab","issue and task tracking through Jira and Confluence"],"datePosted":"2026-10-07T04:08:38.960Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hillsboro, Oregon"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"post-silicon validation, characterization, debug of high-speed mixed-signal interface IP, UCIe specification, high-speed link analysis, Python, lab automation frameworks, data infrastructure, measurement correlation systems, high-speed oscilloscopes, BERTs, spectrum analyzers, network analyzers, direct UCIe or other die-to-die interface experience, deep high-speed SerDes experience, software version control systems such as GitLab, issue and task tracking through Jira and Confluence","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":151000,"maxValue":227000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_2dbcfd76-212"},"title":"Post-Silicon Validation, Senior Staff Engineer","description":"<p>We are seeking a Post-Silicon Validation, Senior Staff Engineer at Synopsys.</p>\n<p>You will engineer the future with us, focusing on post-silicon electrical validation and characterization strategy for UCIe die-to-die interface IP. You will own the validation and characterization process from test plan definition through silicon sign-off.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Own the post-silicon electrical validation and characterization strategy for UCIe die-to-die interface IP</li>\n<li>Architect and develop software solutions for lab automation, result processing, and silicon debug</li>\n<li>Lead complex debug efforts that span circuit design, package and interposer channel behavior, link training firmware, and protocol layer interactions</li>\n<li>Support customers directly with the bring up and debug of their silicon</li>\n<li>Develop characterization methodology for die-to-die links where direct probe access is limited</li>\n<li>Design and develop UIs and data presentation tools used for customer evaluations, marketing demonstrations, and internal reporting</li>\n<li>Review and approve the work of other validation engineers, provide technical mentorship and coaching to junior and mid-level team members</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Ensure the reliability and performance of Synopsys&#39; UCIe die-to-die interface IP</li>\n<li>Deliver validation results and methodology that have measurable impact on department targets</li>\n<li>Establish the technical foundation and tooling that the validation team builds upon</li>\n<li>Shorten debug cycles on complex, first-of-a-kind silicon issues</li>\n<li>Strengthen customer confidence through credible, well-correlated silicon data and compelling evaluation demonstrations</li>\n<li>Accelerate customer time-to-market by getting their silicon up and running quickly and resolving field issues</li>\n<li>Grow the next generation of validation engineers through mentorship, technical review, and coaching</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Bachelor&#39;s degree in Electrical Engineering or Computer Engineering with a minimum of 8 years of related experience, or a Master&#39;s degree with a minimum of 6 years of related experience</li>\n<li>Extensive hands-on experience in post-silicon validation, characterization, and debug of high-speed mixed-signal interface IP</li>\n<li>Working knowledge of the UCIe specification</li>\n<li>Advanced software development capability across multiple languages including Python, C, and C++</li>\n<li>Demonstrated experience architecting complex software projects</li>\n<li>Expert-level debug experience with high-speed oscilloscopes, BERTs, spectrum analyzers, and network analyzers</li>\n<li>Experience supporting customer silicon bring up and debug</li>\n</ul>\n<p>Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2dbcfd76-212","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hillsboro/post-silicon-validation-senior-staff-engineer/44408/101617800512?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$127000-$191000","x-skills-required":["Python","C","C++","UCIe","high-speed mixed-signal interface IP","post-silicon validation","characterization","debug"],"x-skills-preferred":["high-speed SerDes","Signals & Systems concepts","transmission line theory","high-speed link analysis"],"datePosted":"2026-10-07T04:07:26.965Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hillsboro, Oregon"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Python, C, C++, UCIe, high-speed mixed-signal interface IP, post-silicon validation, characterization, debug, high-speed SerDes, Signals & Systems concepts, transmission line theory, high-speed link analysis","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":127000,"maxValue":191000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_571b92de-fac"},"title":"Post-Silicon Validation, Senior Manager","description":"<p>You will engineer the future with Synopsys, leading a team of validation and characterization engineers supporting UCIe-based die-to-die interface IP. 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You will architect and develop software solutions for lab automation, result processing, and silicon debug. You will lead complex debug efforts that span circuit design, package and interposer channel behavior, link training firmware, and protocol layer interactions. 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You will be leading the efficient execution of accurate monthly forecasts and headcount planning to achieve annual financial targets and key business objectives.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Prepare reviews of budgets and forecasts, analyze trends, and provide insights and recommendations to keep the business group on track to meet goals.</li>\n<li>Report actual financial results, review monthly accruals, and provide insightful commentary on variances in collaboration with the extended team.</li>\n<li>Alert leadership to unforeseen expenses, risks, and emerging opportunities.</li>\n<li>Execute ad hoc projects and analysis as needed to support leadership on key business decisions.</li>\n<li>Leverage advanced analytical tools like Anaplan, SAP, Oracle, and Excel to deliver support with optimal efficiency.</li>\n<li>Conduct variance analysis, identify trends, track operational metrics, and recommend improvements for greater efficiency.</li>\n<li>Maintain key performance indicators (KPIs) to assess financial health and operational performance.</li>\n<li>Collaborate with the accounting team to ensure compliance and accuracy in financial reporting.</li>\n<li>Drive process improvements, including creating standard and ad-hoc reports and dashboards in Anaplan and Excel.</li>\n<li>Ensure high data accuracy and attention to detail in all financial analyses.</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Influence Synopsys&#39; financial strategy through accurate budgeting, forecasting, and reporting.</li>\n<li>Support sustainable growth and operational efficiency by providing insightful financial analysis and projections.</li>\n<li>Promote transparency and flexibility in financial processes through innovative reporting tools and dashboards.</li>\n<li>Build credibility and trust with stakeholders through reliable and actionable financial insights.</li>\n<li>Ensure compliance and data integrity in all financial reporting, supporting Synopsys&#39; reputation for excellence.</li>\n<li>Foster a culture of continuous improvement in financial operations and analysis.</li>\n</ul>\n<p><strong>What You&#39;ll Need</strong></p>\n<ul>\n<li>Professional qualification: MBA or CPA preferred.</li>\n<li>At least 8 years of experience in Financial Planning &amp; Analysis, analytics, preferably within a high-tech company.</li>\n<li>Expertise in general accounting, expense analysis, and capital expenditure analysis.</li>\n<li>Exceptional analytical abilities; adept at converting complex data into actionable information.</li>\n<li>Proficiency in Anaplan, SAP, Oracle, advanced Excel, PowerPoint. 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Join ATI, a leader in Outpatient Physical Therapy, where you’ll be part of a team redefining musculoskeletal (MSK) care. With a mission to deliver exceptional patient outcomes and empower clinicians to succeed, we provide the resources and opportunities to help you grow professionally and personally. Your salary will be between $82K-$100K annually.</p>\n<p><strong>Why Choose ATI?</strong></p>\n<p>At ATI, you join a team at the forefront of MSK care, with a strong track record of outcomes, reputation, and growth opportunities.</p>\n<ul>\n<li><strong>Award-Winning Outcomes</strong>: Recognised five years in a row in the Merit-Based Incentive Payment System (MIPS), with a 90% patient satisfaction rate and a 74% Net Promoter Score.</li>\n<li><strong>Outstanding Reputation</strong>: Our clinics average a 4.9 / 5 Google Review rating across locations, reflecting our commitment to exceptional care and patient experience.</li>\n<li><strong>Certified Expertise</strong>: More than a decade of ABPTRFE-accredited Sports and Orthopedic Residencies (with a 96%+ first-time exam pass rate), plus an Upper Extremity Athlete Fellowship with graduates serving across collegiate and professional sports.</li>\n<li><strong>Research Leadership</strong>: Our partnering nonprofit, the Institute for Musculoskeletal Advancement (iMSKA), contributes to the field with 10–15 published papers and 30+ scientific presentations each year.</li>\n<li><strong>Community Impact</strong>: Through the ATI Foundation, we support individuals with physical disabilities in the communities we serve.</li>\n</ul>\n<p><strong>Clinician Support and Development</strong></p>\n<p>At ATI, we prioritise your growth, your well-being, and your ability to focus on patients.</p>\n<ul>\n<li><strong>Collaborative Care</strong>: Work alongside various specialties with manageable caseloads.</li>\n<li><strong>Ongoing Learning</strong>: Access structured mentorship, residency programs, and leadership training.</li>\n<li><strong>Comprehensive CEU Support</strong>: Take advantage of an external CEU benefit and 100’s of live and on-demand development sessions to stay at the forefront of evidence-based care.</li>\n</ul>\n<p><strong>Benefits Highlights</strong></p>\n<p>We offer a competitive compensation package with an incentive plan, and comprehensive benefits, including:</p>\n<ul>\n<li><strong>Paid Time Off</strong>: Generous PTO, holiday pay, CEU, and “Be Well Days” to recharge, prioritise mental and physical health.</li>\n<li><strong>Medical, Dental &amp; Vision Coverage</strong>: Flexible plan options.</li>\n<li><strong>401(k) Match</strong>: Competitive employer matching.</li>\n<li><strong>Loan Reimbursement</strong>: Up to $25,000 in select markets.</li>\n<li><strong>Childcare Tuition Assistance</strong>: Discounted rates.</li>\n<li><strong>Health Savings &amp; Flexible Spending Accounts</strong>: Tax-saving options.</li>\n<li><strong>Short- &amp; Long-Term Disability</strong>: 100% employer-paid income protection plans.</li>\n<li><strong>Life Insurance</strong>: Employer-paid and voluntary options.</li>\n<li><strong>Parental Leave &amp; Adoption Assistance</strong>: Paid time for new parents and support for adoption costs.</li>\n<li><strong>Wellness Programs</strong>: Including weight-loss and lifestyle coaching, digital mental-health support, and 24/7 virtual telehealth access.</li>\n<li><strong>Corporate Discounts</strong>: Exclusive deals for employees.</li>\n</ul>\n<p><strong>Responsibilities</strong></p>\n<p>You will be empowered to make a difference for your patients: performing detailed assessments, creating tailored treatment plans, and working side-by-side with a team of healthcare experts to deliver care that’s truly patient-centred.</p>\n<p><strong>Qualifications</strong></p>\n<ul>\n<li>Degree from an accredited Physical Therapy Program</li>\n<li>Current professional licensure as a Physical Therapist or license eligible based on the rules and regulations of the state in which you are applying for role</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_089ac4ca-581","directApply":true,"hiringOrganization":{"@type":"Organization","name":"ATI","sameAs":"https://careers.atipt.com","logo":"https://logos.yubhub.co/careers.atipt.com.png"},"x-apply-url":"https://careers.atipt.com/hillsboro-or/physical-therapist/203A9EB3A16F413B939944FB10AA5727/job/?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":null,"x-experience-level":null,"x-job-type":"full-time","x-salary-range":"$82K-$100K Annual","x-skills-required":["Physical Therapy","Patient Assessment","Treatment Planning"],"x-skills-preferred":[],"datePosted":"2026-06-22T10:18:01.818Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hillsboro, OR"}},"employmentType":"FULL_TIME","occupationalCategory":"Healthcare","industry":"Healthcare","skills":"Physical Therapy, Patient Assessment, Treatment Planning","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":82000,"maxValue":100000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_614b79d2-214"},"title":"Physical Therapist Assistant","description":"<p>Are you a Physical Therapist Assistant looking to thrive in a supportive, balanced environment? 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