As a Design Verification Intern, you will play an important role in supporting the development of high-quality semiconductor IP and EDA solutions by assisting with the verification of complex digital designs.

Your responsibilities will include:

• Developing and Executing Verification Testcases: Create comprehensive testcases using SystemVerilog and UVM methodologies to verify complex digital designs, including constrained-random testing scenarios and functional coverage analysis.
• Simulation and Debugging: Run simulations using industry-standard EDA tools, analyze results, and debug design issues to identify and resolve functional problems, contributing to improved product quality and reliability.
• Testbench Development: Assist in building and enhancing verification environments and testbenches, implementing verification IP (VIP) for various protocols such as PCIe, UCIe, DDR, AXI, APB, AHB, and other industry-standard interfaces.
• Coverage-Driven Verification: Develop functional coverage models and analyze coverage metrics to ensure comprehensive verification of design features, helping to reduce design risk and accelerate project execution.
• Collaboration and Learning: Work closely with design, verification, and validation teams to understand product architecture, verification flows, and methodologies, while contributing fresh perspectives and innovative solutions to technical challenges.

Required Qualifications:

• Currently pursuing a degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or related technical discipline.
• Basic understanding of Digital Design fundamentals, including combinational/sequential logic, finite state machines (FSM), clocking, and reset concepts.
• Knowledge of Verilog/SystemVerilog for RTL design and verification.
• Familiarity with design verification methodologies, preferably UVM (Universal Verification Methodology) concepts.
• Understanding of verification techniques such as testcase development, constrained-random testing, functional coverage, and debugging.
• Familiarity with Linux/Unix operating environments and simulation tools.
• Strong analytical and problem-solving skills with the ability to investigate and debug complex technical issues.
• Good communication skills, both written and verbal, to effectively collaborate with design, verification, and validation teams.
• Ability to work independently as well as in a team-oriented environment.

Preferred Qualifications:

• Experience with assertion-based verification (SVA) and coverage-driven verification techniques.
• Knowledge of scripting languages such as Python, Perl, Shell, or TCL.
• Familiarity with version control systems like Git.
• Understanding of industry-standard protocols such as PCIe, UCIe, DDR, AXI, APB, AHB, SPI, I2C, or UART.
• Experience with FPGA or hardware verification projects.

Program Length: December 2026 – May 2027 (6 months) Location: Vietnam (VN10) Working Model: Onsite Full-Time/Part-Time: Full-Time Start Date: December 2026

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As a Technical Engineering Intern - AI Research and Development Internship at Synopsys, you will explore the exciting intersection of artificial intelligence and semiconductor design.

Your responsibilities will include:

• Exploring AI-Driven Automation: Research and prototype AI agent solutions to assist selected tasks in digital design and verification workflows with a focus on practical use cases and proof-of-concept development.
• Building AI Prototypes: Design and implement AI prototypes that can analyze results, identify possible root causes, recommend potential solutions, and improve workflow efficiency, demonstrating the practical application of generative AI and LLMs in real-world engineering scenarios.
• Learning Design and Verification Flows: Learn the fundamentals of semiconductor design and verification processes, including RTL design, and identify common engineering challenges that can benefit from AI automation.
• Developing Intelligent Solutions: Create AI agents using frameworks and automation tools that can intelligently assist engineers in their daily tasks, from code analysis to problem detection and resolution.
• Collaborating on Innovation: Work with experienced engineers to explore practical applications of agentic AI in semiconductor development, contributing fresh perspectives and creative solutions.
• Evaluating AI Solutions: Develop simple evaluation methods to measure the accuracy, usefulness, and limitations of AI prototypes. Document the results and share key findings with the team.

To be considered, you will need:

• Currently pursuing a degree in Computer Science, Electrical Engineering, Computer Engineering, or related technical discipline.
• Basic knowledge of AI and Large Language Models (LLMs), with understanding of how they can be applied to solve real-world problems.
• Good Python programming skills with ability to write clean, efficient code.
• Familiarity with Python-based AI tools, LLM APIs, or AI agent frameworks is a plus.
• Basic understanding of digital design and verification concepts and workflows.
• Strong problem-solving skills with ability to tackle complex technical challenges.
• Curious and eager to learn, with passion for exploring new technologies and methodologies in AI and semiconductor design.
• Ability to document work clearly and communicate technical findings to the team.

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As an Applications Engineering Engineer at Synopsys, you will provide hands-on technical support for customers using Synopsys Design Implementation and Verification tools, including troubleshooting issues in physical design flows like floorplanning, placement, CTS, routing, and timing closure.

Responsibilities:

• Provide hands-on technical support for customers using Synopsys Design Implementation and Verification tools
• Take ownership of customer technical cases from initial investigation through resolution
• Collaborate with R&D engineering teams across regions to escalate complex issues
• Build and maintain strong relationships with customers
• Work with Synopsys Fusion Compiler, ICC2, and related signoff tools to help customers optimize their implementation methodologies
• Create and refine technical documentation, application notes, and best practices

The Impact You Will Have:

• Directly unblock customer design teams so they can meet tapeout schedules and deliver working silicon on time
• Reduce the time it takes for customers to adopt new Synopsys tools and features
• Surface real-world customer pain points to R&D teams, influencing product roadmaps
• Build trust and long-term partnerships with customers in the region
• Help customers achieve better PPA (power, performance, area) outcomes
• Contribute to a global knowledge base that helps Application Engineers worldwide solve problems faster

Requirements:

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Science, or a related technical field
• Understanding of ASIC physical design and implementation methodologies
• Working knowledge of Verilog and digital design fundamentals
• Comfort with Linux or Unix environments and scripting in Tcl, Python, Perl, or Shell
• Strong English communication skills
• Exposure to Synopsys Fusion Compiler, ICC2, or related signoff tools is a strong plus

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

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You have spent years designing analog circuits that do not just simulate cleanly, they work in silicon, under real conditions, with real noise and real margin pressure. You know that a CTLE that looks perfect in SPICE can still fail in a testchip if you did not account for substrate coupling or layout parasitics, and you are the kind of engineer who catches those issues before tapeout.

You think in tradeoffs. Power versus speed. Area versus performance. Testability versus complexity. You do not need someone to hand you a perfect spec, you work with system architects and digital teams to figure out what the circuit actually needs to do, then you build it. When layout comes back with a question about metal stack or guard ring placement, you sit down and work through it because you know the circuit does not exist until it is drawn.

Leading a design block or mentoring a junior engineer is part of how you work. You have done this long enough to know that the best designs come from teams that ask hard questions early. At Synopsys, you will work on high speed mixed signal PHYs that power AI, data center, and 5G applications.

What You'll Be Doing

• Design analog circuits for high speed IO blocks (CTLE, FFE, TCOIL, DFE …) PLL, DLL, bandgap references, clock trees, and calibration circuits for UCIe and die-to-die PHY products
• Collaborate with layout engineers to ensure design intent translates into clean layout, then run post-layout verification to confirm performance holds
• Analyze and solve signal integrity, power integrity, noise, and margin issues across complex mixed signal systems
• Work with digital and system engineers to integrate analog blocks into full PHY designs and run mixed signal verification
• Design testchip architectures to validate circuits, then build test cases and run silicon bring-up in the lab to prove the design works in hardware
• Lead design reviews with global teams and mentor junior engineers on circuit design, layout collaboration, and verification

The Impact You Will Have

• Your circuits will enable Tbps die-to-die connectivity in next generation AI accelerators, data center processors, and 5G infrastructure
• The design quality and margin you build in will determine whether products meet performance targets in production silicon
• Your collaboration with layout and digital teams will reduce iteration cycles and get products to tapeout faster
• The testchip architectures you create will de-risk new IP and give the business confidence to commit to new product roadmaps
• Your mentorship will build the next generation of analog design capability in the Vietnam engineering team
• Your work in the lab during silicon bring-up will close the loop between design intent and measured results

What You'll Need

• BS, MS, or PhD in Electronics Engineering, Electromechanics, or Telecommunications
• 3+ years of hands-on experience designing high speed mixed signal PHY circuits with a track record of designs that have taped out and worked in silicon
• Deep understanding of analog circuit design fundamentals including noise analysis, signal integrity, power integrity, and layout effects
• Strong English communication skills for presenting design reviews, writing documentation, and collaborating with global teams
• Experience with academic research or publishing is a plus

Who You Are

• You are a strong team player who pulls the right people together to solve cross-functional problems instead of waiting for someone else to act
• You approach ambiguity with curiosity, asking the right questions when specs are incomplete and moving forward with what you learn
• You have a growth mindset and stay current with new circuit techniques, process nodes, and design tools
• You are easy going and humble, giving credit where it is due and comfortable saying "I don't know, let me find out"

The Team You'll Be Part Of

You will join the Vietnam analog design team within Synopsys IP, the world's number one IP provider. This is a highly motivated team working on bleeding edge 2.5D and 3D IC technologies, collaborating daily with experts across the US, Europe, and Asia.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

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You are a highly motivated individual with a passion for physical design and implementation of complex Mixed Signal IPs and test chips. With a strong background in physical design, you thrive on solving intricate problems and enjoy collaborating with cross-functional teams. You have a deep understanding of the full design cycle from RTL to GDSII and are adept at using Synopsys tools and methodologies. Your excellent communication skills and problem-solving mindset enable you to convey complex ideas to various stakeholders, deliver robust solutions and mentor others, making you a key contributor to innovative projects.

What You'll Be Doing:

• Leading the physical implementation of high-speed interface IPs from RTL to GDS, ensuring timing and physical sign-off.
• Collaborating with cross-functional teams to integrate and verify IP designs to achieve project goals.
• Providing technical guidance and mentorship.
• Continuously improving design methodologies and processes to enhance efficiency and quality.

The Impact You Will Have:

• Driving the development of high-performance physical IP that powers next-generation technologies.
• Ensuring the reliability and efficiency of physical design solutions in our products.
• Contributing to the success of Synopsys' strategic goals through innovative design solutions.
• Sharing technical expertise to elevate team capabilities.
• Fostering a culture of continuous improvement and excellence within the engineering team.
• Supporting the adoption and usability of our products by providing top-tier engineering expertise.

What You'll Need:

• BE or MSEE with 8+ years of direct physical design experience.
• Proficiency in full design cycle from RTL to GDSII, with a focus on Physical Design.
• Solid engineering understanding of IC design, implementation flows, and methodologies for deep submicron design.
• Advanced PnR and sign-off skills (STA, PV, EMIR) to validate design robustness.
• Excellent problem-solving abilities and a keen eye for detail.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

XML job scraping automation by YubHub

You have spent years designing analog circuits that do not just simulate cleanly, they work in silicon, under real conditions, with real noise and real margin pressure. You know that a CTLE that looks perfect in SPICE can still fail in a testchip if you did not account for substrate coupling or layout parasitics, and you are the kind of engineer who catches those issues before tapeout.

You think in tradeoffs. Power versus speed. Area versus performance. Testability versus complexity. You do not need someone to hand you a perfect spec, you work with system architects and digital teams to figure out what the circuit actually needs to do, then you build it. When layout comes back with a question about metal stack or guard ring placement, you sit down and work through it because you know the circuit does not exist until it is drawn.

Leading a design block or mentoring a junior engineer is part of how you work. You have done this long enough to know that the best designs come from teams that ask hard questions early. At Synopsys, you will work on high speed mixed signal PHYs that power AI, data center, and 5G applications.

What You'll Be Doing

• Design analog circuits for high speed IO blocks (CTLE, FFE, TCOIL, DFE …) PLL, DLL, bandgap references, clock trees, and calibration circuits for UCIe and die-to-die PHY products
• Collaborate with layout engineers to ensure design intent translates into clean layout, then run post-layout verification to confirm performance holds
• Analyze and solve signal integrity, power integrity, noise, and margin issues across complex mixed signal systems
• Work with digital and system engineers to integrate analog blocks into full PHY designs and run mixed signal verification
• Design testchip architectures to validate circuits, then build test cases and run silicon bring-up in the lab to prove the design works in hardware
• Lead design reviews with global teams and mentor junior engineers on circuit design, layout collaboration, and verification

The Impact You Will Have

• Your circuits will enable Tbps die-to-die connectivity in next generation AI accelerators, data center processors, and 5G infrastructure
• The design quality and margin you build in will determine whether products meet performance targets in production silicon
• Your collaboration with layout and digital teams will reduce iteration cycles and get products to tapeout faster
• The testchip architectures you create will de-risk new IP and give the business confidence to commit to new product roadmaps
• Your mentorship will build the next generation of analog design capability in the Vietnam engineering team
• Your work in the lab during silicon bring-up will close the loop between design intent and measured results

What You'll Need

• BS, MS, or PhD in Electronics Engineering, Electromechanics, or Telecommunications
• 8+ years of hands-on experience designing high speed mixed signal PHY circuits with a track record of designs that have taped out and worked in silicon
• 3+ years leading design teams, managing projects, or owning full design blocks from spec to silicon
• Deep understanding of analog circuit design fundamentals including noise analysis, signal integrity, power integrity, and layout effects
• Strong English communication skills for presenting design reviews, writing documentation, and collaborating with global teams
• Experience with academic research or publishing is a plus

Who You Are

• You are a strong team player who pulls the right people together to solve cross-functional problems instead of waiting for someone else to act
• You approach ambiguity with curiosity, asking the right questions when specs are incomplete and moving forward with what you learn
• You have a growth mindset and stay current with new circuit techniques, process nodes, and design tools
• You are easy going and humble, giving credit where it is due and comfortable saying "I don't know, let me find out"

The Team You'll Be Part Of

You will join the Vietnam analog design team within Synopsys IP, the world's number one IP provider. This is a highly motivated team working on bleeding edge 2.5D and 3D IC technologies, collaborating daily with experts across the US, Europe, and Asia.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

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As a Staff Application Engineer – Physical Design, you will provide advanced technical leadership and customer support for Synopsys Physical Design solutions across advanced technology nodes.

Key responsibilities include:

• Leading strategic customer engagements, driving technical methodologies, deployment success, and solution adoption for complex implementation challenges.
• Taking ownership of critical escalations, resolving complex design issues, and influencing solution development through close collaboration with R&D teams.
• Driving technical campaigns, methodology innovations, benchmarking activities, and best practices across customer programs.
• Acting as a trusted technical advisor to customers, helping define implementation strategies and achieve optimal PPA and design convergence.
• Mentoring and guiding Application Engineers while contributing to knowledge development and organizational capability growth.

The ideal candidate will have:

• 5+ years of experience in ASIC Physical Design, Design Implementation, or Application Engineering.
• Deep expertise in advanced Physical Design flows including Floorplanning, Placement, Optimization, CTS, Routing, Timing Closure, Signoff, and Design Convergence.
• Strong hands-on experience with Fusion Compiler, ICC2, and implementation methodologies at advanced technology nodes.
• Proven experience supporting complex customer engagements and driving issue resolution across cross-functional teams.
• Strong understanding of STA, extraction, physical verification, signoff, and methodology development.
• Experience with PrimeTime, StarRC, IC Validator, DSO.ai, or AI-driven implementation technologies.
• Strong scripting capabilities using Tcl, Perl, Python, or Shell.
• Demonstrated leadership through mentoring, technical ownership, or leading major customer initiatives.
• Excellent communication and stakeholder management skills.
• Ability to influence customer success, technology adoption, and business growth.

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Job Description

As an Embedded Memory Design Manager at Synopsys, you will be responsible for leading architecture, circuit design, and physical implementation of embedded memory IP including SRAM, register files, TCAM, and ROM across advanced nodes.

Key Responsibilities:

• Lead architecture, circuit design, and physical implementation of embedded memory IP
• Define block specifications with system architects, translating customer requirements into concrete design targets
• Manage circuit and layout engineers, assign work packages, track progress, and coordinate with project management
• Execute design and layout reviews, create documentation including datasheets and design reports
• Model and simulate memory blocks using VerilogA and SystemVerilog to validate architecture before tapeout
• Support silicon evaluation, analyze field issues, and drive root cause analysis when designs fail
• Drive continuous improvement in design methodologies and technology evaluation with global teams

Requirements:

• Bachelor's or Master's in Electrical Engineering, Computer Science, or equivalent
• 10+ years in full embedded memory design flow: architecture, circuit design, physical implementation, compiler automation, characterization, timing, and model generation
• Deep expertise in SRAM, register file, TCAM, and ROM architectures with advanced custom circuit implementations
• Direct experience designing memory IP in advanced nodes (7nm, 5nm, or beyond) with variation-aware design understanding
• Strong knowledge of digital design, verification methodologies, ASIC design flow, and industry-standard EDA tools
• Experience managing engineering teams including task delegation, performance management, and technical mentorship

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You have spent a decade in memory design, where the difference between a working SRAM and one that fails at corner cases comes down to understanding transistor-level physics at 5nm. Embedded memory is not just another block, it is what makes or breaks power, performance, and area targets for the entire SoC.

As an Embedded Memory Design Manager at Synopsys, you will lead architecture, circuit design, and physical implementation of embedded memory IP including SRAM, register files, and ROM across advanced nodes. You will define block specifications with system architects, translating customer requirements into concrete design targets. You will manage circuit and layout engineers, assign work packages, track progress, and coordinate with project management.

Your responsibilities will include:

• Lead architecture, circuit design, and physical implementation of embedded memory IP including SRAM, register files, and ROM across advanced nodes
• Define block specifications with system architects, translating customer requirements into concrete design targets
• Manage circuit and layout engineers, assign work packages, track progress, and coordinate with project management
• Execute design reviews, create documentation including datasheets and design reports
• Support silicon evaluation, analyze field issues, and drive root cause analysis when designs fail
• Drive continuous improvement in design methodologies and technology evaluation with global teams

The impact you will have includes:

• Deliver memory IP meeting aggressive power, performance, and area targets for AI, automotive, mobile, and data center SoCs
• Enable faster customer time-to-market with robust, variation-aware memory solutions that work across process corners
• Build and mentor engineers who can independently own complex memory design challenges
• Influence memory architecture direction across Synopsys IP portfolio through technical reviews
• Reduce design risk and silicon respins by catching issues early through rigorous modeling and simulation
• Expand Synopsys memory IP capabilities into next-generation process nodes
• Strengthen the technical depth of the Da Nang Design Center through targeted mentorship, knowledge sharing, and continuous process improvement initiatives.

To be successful in this role, you will need:

• Bachelor's or Master's in Electrical Engineering, Computer Science, or equivalent
• 10+ years in full embedded memory design flow: architecture, circuit design, physical implementation, compiler automation, characterization, timing, and model generation
• Deep expertise in SRAM, register file, and ROM architecture with advanced custom circuit implementations
• Direct experience designing memory IP in advanced nodes (7nm, 5nm, or beyond) with variation-aware design understanding
• Strong knowledge of digital design, verification methodologies, and industry-standard EDA tools
• Experience managing engineering teams including task delegation, performance management, and technical mentorship

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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You have spent a decade in physical design, and you know that the difference between a chip that tapes out clean and one that burns months in respins is usually a decision made during floorplanning that nobody questioned hard enough. You are the person who questions it. You have closed timing on designs running north of 2 GHz, and you understand that at those frequencies, every picosecond matters and every SI issue that looks small in simulation becomes a showstopper in silicon.

Managing a team is not about delegation for you. It is about building engineers who can see three steps ahead, who understand why a clock tree decision today affects yield six months from now. You are comfortable in the gap between what the spec says and what will actually work. When a design review surfaces a conflict between performance targets and physical constraints, you pull the right people together, sketch the tradeoffs, and drive to a decision the team can execute against.

You know the Synopsys toolchain deeply because you have lived in it. ICC2, Fusion Compiler, PrimeTime, these are instruments you have tuned to deliver results on 7nm, 5nm, and 3nm nodes where the margin for error is measured in atoms. At Synopsys, you will lead physical design for the interconnect technology that makes AI infrastructure possible.

Responsibilities

• Lead the complete physical design flow for high-speed die-to-die interconnect chips operating at 2 GHz and above, from RTL handoff through tape-out
• Drive floorplanning, power planning, clock tree synthesis, place-and-route, and physical verification on advanced nodes including 7nm, 5nm, and 3nm
• Own timing closure across all corners and modes, working with front-end teams to resolve critical paths and ensure SI/PI integrity
• Build, manage, and mentor a global physical design team, setting technical direction and developing engineers at multiple levels
• Collaborate with architecture, design, verification, and package teams to align physical implementation with product requirements and manage milestones
• Champion automation and methodology improvements using Tcl, Python, and Perl scripts that increase team productivity and design quality

The Impact You Will Have

• Deliver the physical implementation for high-bandwidth, ultra-low latency chip-to-chip communication that powers AI training and inference infrastructure
• Set the standard for advanced-node physical design quality and methodology across Synopsys silicon engineering
• Drive multiple successful tape-outs on cutting-edge process nodes, ensuring first-pass silicon success
• Shape the physical design tool flows, automation frameworks, and best practices adopted across the organization
• Grow a team of engineers who become the next generation of technical leaders in physical design
• Advance Synopsys' position as a leader in AI silicon innovation through interconnect technology that enables next-generation systems

Requirements

• 10+ years of hands-on experience in physical design with deep expertise in high-frequency chip implementation and timing closure
• Proven track record leading physical design on advanced process nodes including 7nm, 5nm, or 3nm with multiple successful tape-outs
• Expert-level proficiency with Synopsys physical design tools including ICC2, Fusion Compiler, PrimeTime, StarRC, and RedHawk
• Strong scripting and automation skills in Tcl, Python, and Perl for flow development
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field, PhD is a strong plus
• Experience managing and mentoring engineering teams with a history of developing talent

Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• Time away: company holidays, ETO and FTO Programs
• Family support: maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Retirement plans: save for your future with our retirement plans that vary by region and country
• Competitive salaries

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The ideal candidate has spent years in the trenches of memory layout, where a single transistor out of place can mean the difference between a chip that ships and one that doesn't. SRAM, ROM, eDRAM, you know these structures at the cell level, not just conceptually but in the way you know a tool you have used every day for years.

As a staff engineer, you will lead physical layout design for advanced memory IP including SRAM, ROM, and eDRAM at the cell, array, and peripheral circuit levels. You will ensure every layout meets foundry process design rules and memory-specific constraints, resolving DRC and LVS issues with precision.

Key responsibilities include:

• Leading physical layout design for advanced memory IP
• Ensuring layouts meet foundry process design rules and memory-specific constraints
• Optimizing layouts for area efficiency, performance targets, power consumption, yield improvement, and manufacturability
• Performing RC extraction and parasitic analysis on dense memory arrays
• Debugging complex layout issues
• Collaborating with circuit designers, verification engineers, and process teams

The impact you will have includes delivering memory IP that powers chips for AI, mobile, automotive, and high-performance computing at leading tech companies, reducing risk and accelerating time to market with layouts that are correct, optimized, and manufacturable before tapeout, and driving innovation in layout techniques and automation that improve efficiency and quality across the memory IP portfolio.

Requirements include a bachelor's or master's degree in electronics engineering, telecommunications, physics, or a related technical field, at least 5 years of hands-on experience in custom layout design with significant focus on memory structures like SRAM, ROM, or eDRAM, deep expertise in memory layout at the transistor and cell level, and proficiency with layout tools such as Custom Compiler, Virtuoso, or IC Compiler for physical design and verification.

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Key responsibilities include:

• Designing and verifying embedded memory compilers for advanced nodes.
• Collaborating with layout, methodology, and testchip teams to solve technical issues.
• Optimizing memory architectures for performance and efficiency.
• Using spice simulators for circuit validation.
• Communicating technical updates effectively.

The successful candidate will accelerate delivery of high-performance memory IP, drive innovation in Foundation IP Group projects, enable cutting-edge chip designs for global clients, and support team collaboration and technical excellence.

To succeed in this role, you will need expertise in embedded memory (SRAM/ROM/RF/CAM) design, experience with FinFET/advanced technologies, proficiency with spice simulators and schematic architecture, strong technical communication in Vietnamese and English, and team collaboration skills.

As a member of the team, you will be analytical, collaborative, and detail-oriented, adaptable and proactive, and committed to continuous learning.

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