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You bring a strong foundation in high-speed interface technologies such as DDR and UCIe, combined with hands-on experience delivering complex ASIC designs from concept through implementation.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Architect, design, and develop high-performance digital logic for PHY, DDRIO, and UCIe-based solutions.</li>\n<li>Define and implement RTL architectures while working closely with verification, physical design, and system teams.</li>\n<li>Drive chip- and block-level design activities through all phases of the ASIC development cycle.</li>\n<li>Optimize designs for performance, power, area (PPA), and product scalability.</li>\n<li>Develop and evaluate complex physical IP solutions, including SERDES and DDR subsystems.</li>\n<li>Review designs and mentor engineers to ensure technical excellence and development best practices.</li>\n<li>Collaborate with cross-functional teams to deliver high-quality silicon solutions on schedule.</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Enable next-generation high-speed connectivity solutions used in advanced semiconductor products.</li>\n<li>Influence architectural decisions that improve performance, power efficiency, and scalability.</li>\n<li>Contribute to industry-leading PHY and interface IP development.</li>\n<li>Drive innovation that strengthens Synopsys&#39; leadership in semiconductor design solutions.</li>\n<li>Support technical growth across the engineering organization through collaboration and mentorship.</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>BS in Electrical Engineering, Computer Engineering, or related field with 12+ years of relevant experience, or MS with 10+ years of experience.</li>\n<li>Strong experience in ASIC RTL design and digital logic development.</li>\n<li>Expertise in PHY design, DDRIO, UCIe, SERDES, or related high-speed interface technologies.</li>\n<li>Solid understanding of the complete SoC design cycle, from architecture through implementation.</li>\n<li>Experience with design verification methodologies and hardware debugging.</li>\n<li>Strong problem-solving, analytical, and communication skills.</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<ul>\n<li>Comprehensive medical and healthcare plans</li>\n<li>Time away programs, including ETO and FTO</li>\n<li>Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance</li>\n<li>ESPP: purchase Synopsys common stock at a 15% discount</li>\n<li>Retirement plans that vary by region and country</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_bd958704-703","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/boxborough/rtl-design-engineer/44408/101381296240?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$138000-$208000","x-skills-required":["ASIC RTL design","digital logic development","PHY design","DDRIO","UCIe","SERDES","SoC design cycle","design verification methodologies","hardware debugging"],"x-skills-preferred":["complex IPs for advanced process technologies","low-power design techniques","clocking architectures","mentoring engineers","leading technical projects","industry-standard EDA tools","design methodologies"],"datePosted":"2026-10-02T02:06:20.283Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Boxborough, Massachusetts"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC RTL design, digital logic development, PHY design, DDRIO, UCIe, SERDES, SoC design cycle, design verification methodologies, hardware debugging, complex IPs for advanced process technologies, low-power design techniques, clocking architectures, mentoring engineers, leading technical projects, industry-standard EDA tools, design methodologies","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":138000,"maxValue":208000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_a37ee138-691"},"title":"Analog Design, Sr.Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>In this role, you will work on the design, development, and refinement of Multi-Gbps NRZ &amp; PAM4 SERDES IP. You will be part of a fast-growing analog and mixed signal R&amp;D team developing high speed (&gt;200Gbps) analog integrated circuits in the latest FinFET process nodes.</p>\n<p>As an accomplished analog design engineer, you will thrive on solving complex technical challenges and collaborate with cross-functional teams to deliver best-in-class silicon solutions. Your expertise in SerDes and high-speed analog circuit design will be complemented by your hands-on experience in developing, verifying, and optimizing circuits for high performance, low power, and minimal area.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Ownership of Analog Macro level design</li>\n<li>Tracking and reviewing the work of sub-block owners</li>\n<li>Review SerDes standards and architecture documents to develop analog specifications</li>\n<li>Identify and refine circuit implementations to achieve optimal power, area and performance targets.</li>\n<li>Propose design and verification strategies that efficiently use simulator features to ensure highest quality design.</li>\n<li>Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.</li>\n<li>Collaborate with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits.</li>\n<li>Present simulation data for peer and customer review.</li>\n<li>Mentor and review the progress of junior engineers.</li>\n<li>Document design features and test plans.</li>\n<li>Consult on the electrical characterization of your circuit within the SerDes IP product.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Advanced degree with 4+ years of SerDes/High-Speed analog design experience.</li>\n<li>In-depth familiarity with transistor level circuit design - sound CMOS design fundamentals.</li>\n<li>Silicon-proven experience implementing circuits for the TX, RX and Clock paths within a SerDes</li>\n<li>Experience in leading a small team of designers collaborating on building blocks of a Macro level design</li>\n<li>Detailed design experience with several of the following SerDes sub-circuits:</li>\n</ul>\n<p>receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC</p>\n<ul>\n<li>Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.</li>\n<li>Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.).</li>\n<li>Experience with EDA tools for schematic entry, physical layout, and design verification.</li>\n<li>Knowledge of SPICE simulators and simulation methods.</li>\n<li>Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.</li>\n<li>Experience with TCL, Perl, C, Python, MATLAB.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_a37ee138-691","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/boxborough/analog-design-sr-staff-engineer-15024/44408/91213465776?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$136000-$204000","x-skills-required":["SerDes","High-Speed Analog Circuit Design","CMOS Design Fundamentals","Transistor Level Circuit Design","FinFET CMOS Layout","ESD Issues","Design for Reliability","EDA Tools","SPICE Simulators","Verilog-A","TCL","Perl","C","Python","MATLAB"],"x-skills-preferred":[],"datePosted":"2026-05-29T08:07:05.837Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Boxborough, Massachusetts"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"SerDes, High-Speed Analog Circuit Design, CMOS Design Fundamentals, Transistor Level Circuit Design, FinFET CMOS Layout, ESD Issues, Design for Reliability, EDA Tools, SPICE Simulators, Verilog-A, TCL, Perl, C, Python, MATLAB","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":136000,"maxValue":204000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_dfb98ecf-dd6"},"title":"Engineering Architect (Analog Mixed-Signal Architect)","description":"<p><strong>Overview</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>15195</p>\n<p><strong>Base Salary Range</strong></p>\n<p>$181000-$272000</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>02/16/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are an accomplished engineering leader with a passion for advancing the frontiers of analog mixed-signal technology. With a deep understanding of memory and die-to-die interfaces, you thrive in environments where innovation meets real-world impact. You have a proven track record of architecting high-performance solutions, particularly in the realm of High Bandwidth Memory (HBM) interface design. You are committed to continuous learning, keeping pace with evolving technologies and industry trends. Your communication skills enable you to articulate ideas clearly and work effectively across sites and disciplines. Above all, you are driven by the opportunity to contribute to critical components powering AI systems, knowing your work has a lasting impact on the future of technology.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Reviewing and integrating the latest multichip and interposer technologies from various foundries into Synopsys’ HBM PHY products.</li>\n</ul>\n<ul>\n<li>Defining bump maps and top-level floorplans for HBM PHY products to ensure optimal performance, power, and area (PPA).</li>\n</ul>\n<ul>\n<li>Collaborating with layout teams to deliver top metal covercells optimized for performance and reliability in HBM PHY designs.</li>\n</ul>\n<ul>\n<li>Working with layout and SIPI teams to design interposer geometries that maximize performance and signal integrity.</li>\n</ul>\n<ul>\n<li>Mentoring junior engineers and providing technical guidance across multi-site teams.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Elevate the performance and reliability of Synopsys’ HBM PHY products, directly contributing to the advancement of AI and high-performance computing systems.</li>\n</ul>\n<ul>\n<li>Enable successful integration of cutting-edge multichip and interposer technologies, ensuring Synopsys remains at the forefront of semiconductor innovation.</li>\n</ul>\n<ul>\n<li>Improve manufacturability and scalability of memory interface IPs, supporting the needs of leading semiconductor companies worldwide.</li>\n</ul>\n<ul>\n<li>Drive technical excellence across cross-functional teams, fostering collaboration and knowledge sharing.</li>\n</ul>\n<ul>\n<li>Enhance customer satisfaction by delivering robust, high-quality solutions that meet demanding market requirements.</li>\n</ul>\n<ul>\n<li>Support Synopsys’ reputation as a trusted IP provider through leadership, innovation, and problem-solving.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>MS or PhD in Electrical Engineering or related field.</li>\n</ul>\n<ul>\n<li>15+ years of experience in memory or die-to-die interface design.</li>\n</ul>\n<ul>\n<li>Expertise in floorplan optimization for IPs integrating full-custom analog and synthesized digital blocks.</li>\n</ul>\n<ul>\n<li>Strong experience with power grid design and EMIR analysis.</li>\n</ul>\n<ul>\n<li>Proficiency in interposer design and implementation.</li>\n</ul>\n<ul>\n<li>Solid understanding of analog principles and designs (bandgaps, LDO regulators, current mirrors, DLL/PLLs).</li>\n</ul>\n<ul>\n<li>Deep knowledge of signal-integrity and power integrity principles.</li>\n</ul>\n<ul>\n<li>Experience with layout impact on circuit performance and reliability.</li>\n</ul>\n<ul>\n<li>Ability to troubleshoot and debug memory interfaces effectively.</li>\n</ul>\n<ul>\n<li>Excellent communication and collaboration skills across multi-site teams.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>A collaborative leader who inspires and guides teams to technical excellence.</li>\n</ul>\n<ul>\n<li>Detail-oriented, analytical, and able to balance multiple priorities.</li>\n</ul>\n<ul>\n<li>Innovative thinker, open to new approaches and emerging technologies.</li>\n</ul>\n<ul>\n<li>Effective communicator, capable of translating complex technical concepts for diverse audiences.</li>\n</ul>\n<ul>\n<li>Resilient and proactive in addressing challenges and driving solutions.</li>\n</ul>\n<ul>\n<li>Committed to continuous learning and professional growth.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You’ll join our High Bandwidth Memory interface design team, a group of passionate engineers dedicated to developing best-in-class IP for the world’s most advanced computing systems. Our team collaborates across multiple sites and disciplines, leveraging expertise in analog mixed-signal design, layout, and signal integrity to deliver innovative solutions that power the next generation of AI and high-performance devices.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_dfb98ecf-dd6","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/boxborough/engineering-architect-analog-mixed-signal-architect-15195/44408/91852130944?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$181000-$272000","x-skills-required":["MS or PhD in Electrical Engineering or related field","15+ years of experience in memory or die-to-die interface design","Expertise in floorplan optimization for IPs integrating full-custom analog and synthesized digital blocks","Strong experience with power grid design and EMIR analysis","Proficiency in interposer design and implementation","Solid understanding of analog principles and designs (bandgaps, LDO regulators, current mirrors, DLL/PLLs)","Deep knowledge of signal-integrity and power integrity principles","Experience with layout impact on circuit performance and reliability","Ability to troubleshoot and debug memory interfaces effectively","Excellent communication and collaboration skills across multi-site teams"],"x-skills-preferred":[],"datePosted":"2026-03-09T11:02:26.298Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Boxborough, Massachusetts"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"MS or PhD in Electrical Engineering or related field, 15+ years of experience in memory or die-to-die interface design, Expertise in floorplan optimization for IPs integrating full-custom analog and synthesized digital blocks, Strong experience with power grid design and EMIR analysis, Proficiency in interposer design and implementation, Solid understanding of analog principles and designs (bandgaps, LDO regulators, current mirrors, DLL/PLLs), Deep knowledge of signal-integrity and power integrity principles, Experience with layout impact on circuit performance and reliability, Ability to troubleshoot and debug memory interfaces effectively, Excellent communication and collaboration skills across multi-site teams","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":181000,"maxValue":272000,"unitText":"YEAR"}}}]}